Prosecution Insights
Last updated: October 01, 2026
Application No. 18/450,537

CIRCUIT BOARD ASSEMBLY AND ELECTRONIC DEVICE

Non-Final OA §102§103
Filed
Aug 16, 2023
Priority
Aug 17, 2022 — CN 202210986834.9
Examiner
WU, JAMES
Art Unit
2841
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Huawei Technologies Co., Ltd.
OA Round
3 (Non-Final)
71%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
521 granted / 737 resolved
+2.7% vs TC avg
Strong +33% interview lift
Without
With
+33.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
26 currently pending
Career history
752
Total Applications
across all art units

Statute-Specific Performance

§103
53.2%
+13.2% vs TC avg
§102
19.0%
-21.0% vs TC avg
§112
23.2%
-16.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 737 resolved cases

Office Action

§102 §103
DETAILED ACTION Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/20/2026 has been entered. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Taguchi (US 9,867,274). Regarding claim 1, Taguchi discloses a circuit board assembly (Fig. 2), comprising: a conductive plate (15, Fig. 2; col. 2, lns. 51-64: “… wiring layer 15 of the circuit board 10 is made of conductive plate or foil that is thicker than each of the wiring layers 32… may bear a higher current than the circuit 33…”) configured to carry a current (col. 5, lns. 3-11: “…wiring 15 for high current is suitable…”); and a circuit board (30, Fig. 2) comprising a substrate (no reference number, but can be one of the insulating/dielectric layer alternating with the wiring layers 32 in PCB 30 shown in Fig. 2) and a conductive trace (bottom 32 in Fig. 2), wherein the circuit board comprises a first surface (bottom surface of 30 in Fig. 2) and a second surface (top surface of 30 in Fig. 2) that are disposed opposite to each other, the conductive trace being disposed on the first surface (bottom 32 on bottom surface of 30 as shown in Fig. 2), the conductive plate being a plate body distinct from the circuit board (15 is a conductive plate body distinct from the circuit board 30 as shown in Fig. 2 and mentioned in col. 2, lns. 51-64) and being fastened to the circuit board in a first region (region of 30 for 15 and fastened by 41 as shown in Fig. 2), the first region being a portion of the first surface (15 on bottom surface of 30 as shown in Fig. 2), the conductive plate being disposed on the first surface in the first region (15 fastened to 30 by 41 and 43 as shown in Fig. 2); and a current-carrying capacity of the conductive plate is greater than that of the conductive trace (col. 2, lns. 51-64: “…wiring layer 15… may bear a higher current than the circuit 33…”; note 32 is part of 33). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Taguchi, and further in view of Dünsbier (US 10,488,441). Regarding claim 13, Taguchi teaches the circuit board assembly according to claim 1. Taguchi does not teach wherein a thickness of the conductive plate is greater than or equal to 0.3 mm. However, Dünsbier teaches a thickness of a conductive plate (high current conductor 5, Fig. 4) is greater than or equal to 0.3 mm (col. 2, lns. The high current conductor… preferred …. a thickness of at least 0.5mm.). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a thickness of the conductive plate is greater than or equal to 0.3 mm in Taguchi, as taught by Dünsbier, in order to provide high current capacity and prevent overheating. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Taguchi, and further in view of Langner et al. (US 2019/0235588). Regarding claim 15, Taguchi teaches the circuit board assembly according to claim 1. Taguchi does not explicitly teach an electronic device, comprising a housing and wherein the circuit board assembly is fastened in the housing. However, Langner teaches an electronic device (1, Fig. 1), comprising a housing (2, Fig. 1) and a circuit board assembly (4, Fig. 1), wherein the circuit board assembly is fastened in the housing (4 is fastened in 2 by screws 7 as shown in Fig. 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have an electronic device, comprising a housing and wherein the circuit board assembly is fastened in the housing in Taguchi, as taught by Langner, in order to protect and secure the circuit board assembly inside a housing of an electronic device. Response to Arguments Applicant's arguments with respect to claims 1, 13 and 15 have been considered but are moot in view of the new ground(s) of rejection. Applicant also made the following argument: 1. Applicant alleges, in regards to claim 1, that the Office Action's mapping does not satisfy this structure. The Office Action relies on Taguchi's wiring layer 15 as the claimed conductive plate and printed circuit board 30 as the claimed circuit board. Under that mapping, wiring layer 15 is not disposed on the first surface of printed circuit board 30 in a first region. Instead, Taguchi describes wiring layer 15 as being embedded in plate member 11 of circuit board 10. See Taguchi, FIG. 2, col. 2, 11. 51-58. In other words, the structure relied upon as the conductive plate is located in circuit board 10, not on a first surface of printed circuit board 30. Although Taguchi describes wiring layer 15 as being made of conductive plate or foil, that description concerns the material or form of embedded wiring layer 15, not a plate body distinct from printed circuit board 30 and disposed on a first surface of printed circuit board 30 (response at pg. 7). Note that Examiner has now considered first surface at the bottom surface of 30 in Fig. 2 of Taguchi. Furthermore, 15 is not in circuit board 30 and distinct from circuit board 30. Thus, Examiner respectfully disagrees with Applicant’s argument. 2. Applicant further alleges that Taguchi's connection structure confirms the same distinction. Taguchi explains that terminals 12 provided on plate member 11 are pressed against printed circuit board 30, whereby circuit 16 of circuit board 10 is electrically connected with circuit 33 of printed circuit board 30. See Taguchi, FIG. 2, col. 3, 11. 10-24. Thus, Taguchi electrically connects circuits of two separate boards through terminals 12, rather than providing a conductive plate that is a plate body distinct from the circuit board and disposed on the first surface of that same circuit board in the first region. Nor does Taguchi satisfy amended claim 1 by treating circuit board 10 as the claimed circuit board. If circuit board 10 were treated as the claimed circuit board, wiring layer 15 would not be a plate body distinct from circuit board 10. Rather, Taguchi describes wiring layer 15 as an embedded wiring layer of plate member 11 of circuit board 10. See Taguchi, FIG. 2, col. 2, 11. 51- 58. An embedded wiring layer of a board is not a distinct plate body fastened to and disposed on a first surface of that same board. Accordingly, whether printed circuit board 30 or circuit board 10 is treated as the claimed circuit board, Taguchi does not disclose the amended structural relationship among the conductive trace, the conductive plate, and the circuit board. Taguchi therefore does not anticipate amended claim 1, and withdrawal of the rejection under 35 U.S.C. § 102(a)(1) is respectfully requested (Respond at pg. 7-8). Note again that Taguchi’s conductive plate 15 is not part of circuit board 30. Examiner only considered 30 as the required circuit board by the claimed limitation, and circuit board 10 is not part of the circuit board 30. Thus, Taguchi satisfies the new limitation “the conductive plate being a plate body distinct from the circuit board (15 is a conductive plate body distinct from the circuit board 30 as shown in Fig. 2 and mentioned in col. 2, lns. 51-64) and being fastened to the circuit board in a first region (region of 30 for 15 and fastened by 41 as shown in Fig. 2), the first region being a portion of the first surface (15 on bottom surface of 30 as shown in Fig. 2), the conductive plate being disposed on the first surface in the first region (15 fastened to 30 by 41 and 43 as shown in Fig. 2); and a current-carrying capacity of the conductive plate is greater than that of the conductive trace (col. 2, lns. 51-64: “…wiring layer 15… may bear a higher current than the circuit 33…”; note 32 is part of 33).” Thus, examiner respectfully disagrees with Applicant’s argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES WU whose telephone number is (571)270-7974. The examiner can normally be reached Monday - Friday, 9:00AM - 5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Allen Parker can be reached at (303)297-4722. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAMES WU/Primary Examiner, Art Unit 2841
Read full office action

Prosecution Timeline

Show 1 earlier event
Sep 11, 2023
Response after Non-Final Action
Nov 26, 2025
Non-Final Rejection mailed — §102, §103
Feb 12, 2026
Response Filed
Apr 28, 2026
Final Rejection mailed — §102, §103
Jul 20, 2026
Response after Non-Final Action
Jul 28, 2026
Request for Continued Examination
Jul 30, 2026
Response after Non-Final Action
Aug 21, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
71%
Grant Probability
99%
With Interview (+33.3%)
2y 4m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 737 resolved cases by this examiner. Grant probability derived from career allowance rate.

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