Prosecution Insights
Last updated: October 01, 2026
Application No. 18/450,664

Method of Transferring Patterned Micro-LED Die onto a Silicon Carrier for Wafer-to-Wafer Hybrid Bonding to a CMOS Backplane

Final Rejection §103
Filed
Aug 16, 2023
Priority
Sep 16, 2022 — provisional 63/376,039
Examiner
SHEKER, RHYS PONIENTE
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Apple Inc.
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
2m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
57 granted / 68 resolved
+15.8% vs TC avg
Moderate +7% lift
Without
With
+6.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
34 currently pending
Career history
110
Total Applications
across all art units

Statute-Specific Performance

§103
64.6%
+24.6% vs TC avg
§102
19.3%
-20.7% vs TC avg
§112
16.2%
-23.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 68 resolved cases

Office Action

§103
DETAILED ACTION This Office Action is in response to Applicant’s Remarks filed on 04/28/2026. Currently, claims 1-4, 6-7, and 9-24 are pending in the application. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendments Applicant's arguments with respect to claim(s) 1-4, 6-7, and 9-24 have been considered but are moot because the new ground of rejection does not rely on the same combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Information Disclosure Statement The information disclosure statement (IDS) submitted on 01/23/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the Examiner. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, 6-7, 9, 18-20, and 22-24 are rejected under 35 U.S.C. 103 as being obvious over HAHN (US Pub. No. 2022/0059740) in view of GOWARD et al. (US Pub. No. 2021/0151649). Regarding independent claim 1, Hahn teaches an optoelectronic structure (Fig. 17) comprising: a backplane (Fig. 17A, 1710, ¶ [0143]) including driving circuitry (Fig. 17A, 1720, ¶ [0143]) and an array of contact pads (Fig. 17A, 1730, ¶ [0143]); a device layer (layers of Fig. 17B) bonded to the backplane, the device layer including: an array of micro-sized diodes (Fig. 17B, 1770, ¶ [0144]); an array of landing pads (Fig. 17B, conductive layer in-between 1780 and semiconductor layers, see Fig. 15, 1550, ¶ [0132]) underneath the array of micro-sized diodes, each landing pad corresponding to a micro-sized diode; and a wiring layer including an array of via contacts (Fig. 17B, 1780, ¶ [0144]) connected to the array of landing pads, each via contact corresponding to a landing pad; wherein the wiring layer is directly bonded with the array of contact pads with metal-metal bonds (Fig. 17C, ¶ [0145]). However, Hahn does not explicitly teach a diced coupon including an array of micro-sized diodes (the Examiner notes that Hahn does teach that Hahn’s device can include arrays of LEDs that can be diced and then bonded to driver circuits on a separate wafer using hybrid bonding); a gap fill layer laterally surrounding the diced coupon; and a reconstituted wiring layer spanning across the diced coupon and the gap fill layer. However, Goward is a pertinent art that teaches a diced coupon (Fig. 13D, 1355, ¶ [0124] teaches an LED array that is separated into multiple sub-arrays corresponding to Hahn’s diced LED array) including an array of micro-sized diodes; a gap fill layer (Figs. 13D & 14D, 1370/1470, ¶ [0126] teaches an underfill layer in gaps between Goward’s separated sub-arrays) laterally surrounding (Fig. 13D, underfill 1370 at least partially surrounds Goward’s separated sub-arrays. Further, it would be obvious that Goward’s device would include a separated sub-array completely surrounded by Goward’s underfill depending on the number and arrangement of separated sub-arrays) the diced coupon; and a reconstituted wiring layer spanning (Fig. 13B, 1350 + 1340 teaches n/p contacts corresponding to Hahn’s contacts) across the diced coupon and the gap fill layer. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hahn’s device to include multiple adjacent LED sub arrays and an underfill according to the teaching of Goward (Fig. 13D) in order to reduce the impact of the difference in thermal expansion during manufacturing (Goward ¶ [0124]). Regarding claim 2, Hahn modified by Goward teaches the optoelectronic structure of claim 1, and Hahn teaches that the array of via contacts (Fig. 17B, 1780, ¶ [0144]) is a damascene array (¶ [0144] teaches that 1780 can be made of copper and are formed within dielectric layer 1760). Further, the language, term, or phrase "damascene array", is directed towards the process of making a contact. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “damascene array" only requires an array of contacts, which does not distinguish the invention from Hahn, who teaches the structure as claimed. Regarding claim 3, Hahn modified by Goward teaches the optoelectronic structure of claim 1, and Hahn teaches that the array of via contacts (Fig. 17B, 1780, ¶ [0144]) is at least partially embedded within a dielectric build-up layer (Fig. 17B, 1760, ¶ [0144]). Regarding claim 4, Hahn modified by Goward teaches the optoelectronic structure of claim 3, and Hahn teaches that the dielectric build-up layer (Fig. 17B, 1760, ¶ [0144]) is bonded directly to a top dielectric layer (Fig. 17C, 1740, ¶ [1043]) of the backplane (Fig. 17A, 1710, ¶ [0143]). Regarding claim 6, Hahn modified by Goward teaches the optoelectronic structure of claim 1 and Hahn modified by Goward teaches that the diced coupon (Goward Fig. 13D, 1355, ¶ [0124] teaches an LED array that is separated into multiple sub-arrays corresponding to Hahn’s diced LED array) includes a dielectric fill layer (Hahn Fig. 17B, portion of 1760 corresponding to 1770, ¶ [0144]) underneath the array of micro-sized diodes (¶ [0131]), and the array of via contacts (Hahn Fig. 17B, 1780, ¶ [0144]) extends through the dielectric fill layer. Regarding claim 7, Hahn modified by Goward teaches the optoelectronic structure of claim 6, and Hahn teaches a pitch between the via contacts (Fig. 17B, 1780, ¶ [0144]) is 5 pm or less (¶ [0075] teaches that Hahn’s LEDs can have a pitch of less than 2 μm. Hahn’s contacts correspond to Hahn’s LED’s and would therefore fulfill this limitation). Regarding claim 9, Hahn modified by Goward teaches the optoelectronic structure of claim 1, and Hahn teaches that the array of via contacts (Fig. 17B, 1780, ¶ [0144]) extends through (Fig. 17B) a portion of the gap fill layer (Fig. 17B, portion of 1760 inbetween and corresponding to diodes 1770, ¶ [0144]). Regarding claim 18, Hahn modified by Goward teaches the optoelectronic structure of claim 1, and Hahn modified by Goward that the diced coupon (Goward Fig. 13D, 1355, ¶ [0124] teaches an LED array that is separated into multiple sub-arrays corresponding to Hahn’s diced LED array) is one of a plurality of diced coupons and a plurality of dummy vias (Hahn Fig. 17C, 1782, ¶ [0144]) adjacent the array of via contacts. Regarding claim 19, Hahn modified by Goward teaches the optoelectronic structure of claim 18, and Hahn teaches that the plurality of dummy vias (Fig. 17C, 1782, ¶ [0144]) does not vertically overlap with the plurality of diced (see Goward Fig. 13D and Hahn ¶ [0135]) coupons (Fig. 17C, contacts 1782 does not vertically overlap with the array of Hahn’s LEDs 1770). Regarding claim 20, Hahn modified by Goward teaches the optoelectronic structure of claim 1, and Hahn teaches that the micro-sized diodes (Fig. 17B, 1770, ¶ [0144]) of the array of micro-sized diodes are light emitting diodes (LEDs) (¶ [0144]). Regarding claim 22, Hahn modified by Goward teaches the optoelectronic structure of claim 1, wherein the driving circuitry (Fig. 17A, 1720, ¶ [0143]) includes CMOS driving circuitry (¶ [0135] teaches that Hahn’s driver circuits can be made using CMOS processes). Regarding claim 23, Hahn modified by Goward teaches the optoelectronic structure of claim 1, and Hahn teaches that the driving circuitry (Fig. 17A, 1720, ¶ [0143]) includes an array of pixel driver chips (¶ [0137]). Regarding claim 24, Hahn teaches the optoelectronic structure of claim 1, and Hahn teaches that the micro-sized diodes includes a sub-array of regrown micro-size diodes, each regrown micro-sized diode including a p-doped layer (Fig. 15, 1540, ¶ [0131]), an n-doped layer (Fig. 15, 1520, ¶ [0131]), an active layer (Fig. 15, 1530, ¶ [0131]) between the p-doped layer and the n-doped layer, and a regrown layer (Fig. 15, 1560, ¶ [0132]) spanning across sidewalls of the p-doped layer the active layer and the n-doped layer. Further, the language, term, or phrase "regrown layer", is directed towards the process of making a layer. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “regrown layer" only requires a sidewall layer, which does not distinguish the invention from Hahn, who teaches the structure as claimed. Claims 14-16 are rejected under 35 U.S.C. 103 as being obvious over HAHN (US Pub. No. 2022/0059740) in view of GOWARD et al. (US Pub. No. 2021/0151649) and further in view of LUTGEN et al. (US Pub. No. 2022/0173159). Regarding claim 14, Hahn modified by Goward teaches the optoelectronic structure of claim 10, and Hahn modified by Goward teaches that the diced coupon (Goward Fig. 13D, 1355, ¶ [0124] teaches an LED array that is separated into multiple sub-arrays corresponding to Hahn’s diced LED array) includes a p-n diode layer (Fig. 17B, layer above 1750 including 1770, ¶ [0144] teaches that 1770 include n type and p type layers grown on carrier wafer 1750) comprising the array of micro-sized diodes (Fig. 17B, 1770, ¶ [0144]). However, Hahn modified by Goward does not explicitly teach that an opening through the p-n diode layer, and a back side contact layer within the opening and in electrical contact with a top electrode layer. However, Lutgen is a pertinent art that teaches an opening through (Fig. 13V, area of 1326 and 1330, ¶¶ [0125]-[0126]) the p-n diode layer (Fig. 13V, 1314 + 1310, ¶ [0124]), and a back side contact layer (Fig. 13V, 1326, ¶ [0125]) within the opening and in electrical contact with a top electrode layer (Fig. 13V, 1328, ¶¶ [0125]-[0126] teaches that contacts 1326 and 1328 can be made out of a conductive metal and that metal layer 1330 are deposited on both contacts. Therefore, 1326 and 1328 are in electrical contact through 1330). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hahn modified by Goward’s device to further comprise contacts and a metal layer according to the teaching of Lutgen (Fig. 13V) in order to improve contrast ratio (¶ [0125]). Regarding claim 15, Hahn modified by Goward modified by Lutgen teaches the optoelectronic structure of claim 14, and Lutgen teaches that the back side contact layer (Fig. 13V, 1326, ¶ [0125]) is electrically connected with a supplemental via contact (Lutgen Fig. 13V, 1348 to the left of 1326, ¶ [0130]) that is electrically connected with a contact pad (the Examiner notes that although not pictured in Fig. 13V, it would be obvious that Lutgen’s metal plugs 1348 would be connected to an additional layer in a similar manner to 1216 and 1214 in Fig. 12 (¶ [0122]) and 1882/1830 in Fig. 18D (¶ [0165])) of the array of contact pads. Regarding claim 16, Hahn modified by Goward modified by Lutgen teaches the optoelectronic structure of claim 15 and Hahn modified by Goward modified by Lutgen teaches that the diced coupon (Goward Fig. 13D, 1355, ¶ [0124] teaches an LED array that is separated into multiple sub-arrays corresponding to Hahn’s diced LED array) further comprises an array of reflector layers (Lutgen Fig. 13V, 1330, ¶ [0126] teaches that 1330 can be reflective. Further, 1330 at least partially conforms around Lutgen’s n-type later 1310, p-type layer 1314, and active layer 1312) wrapping conformally around the array of micro-sized diodes (Lutgen Fig. 13V, layers under 1370, ¶ [0136]) and the supplemental via contact (Lutgen Fig. 13V, 1348 to the left of 1326, ¶ [0130]) is connected to a reflector layer (Fig. 13V, portion of 1330 underneath the rightmost 1370) of the sub-array array of reflector layers. Claim 17 is rejected under 35 U.S.C. 103 as being obvious over HAHN (US Pub. No. 2022/0059740) and further in view of GOWARD et al. (US Pub. No. 2021/0151649) and further in view of LEI et al. (US Pub. No. 2023/0335518). Regarding claim 17, Hahn modified by Goward teaches the optoelectronic structure of claim 5. However, Hahn modified by Goward does not explicitly teach that a placement distribution of the array of landing pads across the backplane is characterized by a first order standard deviation of displacement values of the array of landing pads to the array of contact pads, and position distribution of the array of via contacts across the backplane is characterized by a first order standard deviation of displacement values of the array of via contacts to the array of contact pads, and the first order standard deviation for the placement distribution of the array of landing pads across the backplane is larger than the first order standard deviation for the position distribution of the array of via contacts across the backplane. However, Lei is a pertinent art that teaches a placement distribution of the array of landing pads (Fig. 15A, 1570, ¶ [0167]) across the backplane is characterized by a first order standard deviation of displacement values of the array of landing pads to the array of contact pads (Fig. 15A, 1530, ¶ [0167]), and position distribution of the array of via contacts across the backplane is characterized by a first order standard deviation of displacement values of the array of via contacts to the array of contact pads, and the first order standard deviation for the placement distribution of the array of landing pads across the backplane is larger than the first order standard deviation for the position distribution of the array of via contacts across the backplane (Fig. 15A, the placement/position distribution of Lei’s metal layers result in an offset deviation from the center of Lei’s micro LEDs (Fig. 15A, 1550, ¶ [0167]). Therefore, Hahn modified by Lei would fulfill this limitation). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the placement/position of Hahn’s contacting layers according to the teaching of Lei (Fig. 15A) in order to improve thermal performance (Lei ¶¶ [0002] & [0138]). Claim 21 is rejected under 35 U.S.C. 103 as being obvious over HAHN (US Pub. No. 2022/0059740) in view of GOWARD et al. (US Pub. No. 2021/0151649) and further in view of INOUE (US Pub. No. 2023/0132555). Regarding claim 21, Hahn modified by Goward teaches the optoelectronic structure of claim 1, and Hahn teaches that the micro-sized diodes (Fig. 17B, 1770, ¶ [0144]) of the array of micro-sized diodes are photodetectors (PD) (Hahn’s micro LEDs would be capable of functioning as photodetectors because it is known in the art that LEDs can be used as photodetectors depending on the bias voltage. As evidence, see ¶ [0102] of Inoue). Allowable subject matter Claims 10-13 are objected to as being dependent upon a rejected base claim (claim 1), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record. With respect to dependent claim 10, the cited prior art does not anticipate or make obvious, inter alia, the step of: “he diced coupon includes a p-n diode layer comprising: the array of micro-sized diodes;a pattern of intermediate p-n diode layer material laterally between the micro-sized diodes of the array of micro-sized diodes;wherein the pattern of intermediate p-n diode layer material is separated from the array of micro-sized diodes by trenches.” Claims 11-13 are dependent on claim 10. Cited Prior Art The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to RHYS P. SHEKER whose telephone number is (703)756-1348. The examiner can normally be reached Monday - Friday 7:30 am to 5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached on 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /R.P.S./ Examiner, Art Unit 2813 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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Prosecution Timeline

Aug 16, 2023
Application Filed
Feb 17, 2026
Non-Final Rejection mailed — §103
Apr 28, 2026
Response Filed
Jul 28, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
91%
With Interview (+6.9%)
3y 4m (~2m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 68 resolved cases by this examiner. Grant probability derived from career allowance rate.

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