DETAILED ACTION
This Office Action is in response to the Applicant Election filed on 12/10/2025.
Currently, claims 1-24 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 12/10/2025 is acknowledged. Claims 1-24 are examined in this Office action.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 08/16/2023 and 04/02/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the Examiner.
Claim Objections
Claim 24 is objected to because of the following informality:
In claim 24, “the p-doped layer the active layer and the n-doped layer” should read “the p-doped layer, the active layer, and the n-doped layer”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9, 18-20, and 22-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HAHN (US Pub. No. 2022/0059740).
Regarding independent claim 1, Hahn teaches an optoelectronic structure (Fig. 17) comprising:
a backplane (Fig. 17A, 1710, ¶ [0143]) including driving circuitry (Fig. 17A, 1720, ¶ [0143]) and an array of contact pads (Fig. 17A, 1730, ¶ [0143]);
a device layer (layers of Fig. 17B) bonded to the backplane, the device layer including:
an array of micro-sized diodes (Fig. 17B, 1770, ¶ [0144]);
an array of landing pads (Fig. 17B, conductive layer in-between 1780 and semiconductor layers, see Fig. 15, 1550, ¶ [0132]) underneath the array of micro-sized diodes, each landing pad corresponding to a micro-sized diode; and
an array of via contacts (Fig. 17B, 1780, ¶ [0144]) connected to the array of landing pads, each via contact corresponding to a landing pad;
wherein the array of via contacts is part of a reconstituted wiring layer that is directly bonded with the array of contact pads with metal-metal bonds (Fig. 17C, ¶ [0145]).
Regarding claim 2, Hahn teaches the optoelectronic structure of claim 1, and Hahn teaches that the array of via contacts (Fig. 17B, 1780, ¶ [0144]) is a damascene array (¶ [0144] teaches that 1780 can be made of copper and are formed within dielectric layer 1760).
Further, the language, term, or phrase "damascene array", is directed towards the process of making a contact. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “damascene array" only requires an array of contacts, which does not distinguish the invention from Hahn, who teaches the structure as claimed.
Regarding claim 3, Hahn teaches the optoelectronic structure of claim 1, and Hahn teaches that the array of via contacts (Fig. 17B, 1780, ¶ [0144]) is at least partially embedded within a dielectric build-up layer (Fig. 17B, 1760, ¶ [0144]).
Regarding claim 4, Hahn teaches the optoelectronic structure of claim 3, and Hahn teaches that the dielectric build-up layer (Fig. 17B, 1760, ¶ [0144]) is bonded directly to a top dielectric layer (Fig. 17C, 1740, ¶ [1043]) of the backplane (Fig. 17A, 1710, ¶ [0143]).
Regarding claim 5, Hahn teaches the optoelectronic structure of claim 1, and Hahn teaches that the array of micro-sized diodes (Fig. 17B, 1770, ¶ [0144]) is comprised of a plurality of coupons, each coupon including a sub-array of micro-sized diodes (¶ [0131] teaches that Hahn’s micro LEDs can be arranged in two dimensional arrays. A two dimensional array can be subdivided into sub arrays. Therefore, Hahn fulfills this limitation).
Regarding claim 6, Hahn teaches the optoelectronic structure of claim 5, and Hahn teaches that each coupon includes a dielectric fill layer (Fig. 17B, portion of 1760 corresponding to 1770, ¶ [0144]) underneath a corresponding sub-array of micro-sized diodes (¶ [0131]), and the array of via contacts (Fig. 17B, 1780, ¶ [0144]) includes a plurality of sub-arrays of via contacts (Fig. 17B, 1780 corresponding to 1770, ¶ [0144]), and each sub-array of via contacts extends through a corresponding dielectric fill layer (Fig. 17B).
Regarding claim 7, Hahn teaches the optoelectronic structure of claim 6, and Hahn teaches a pitch between the via contacts (Fig. 17B, 1780, ¶ [0144])within each sub-array of via contacts is 5 pm or less (¶ [0075] teaches that Hahn’s LEDs can have a pitch of less than 2 μm. Hahn’s contacts correspond to Hahn’s LED’s and would therefore fulfill this limitation).
Regarding claim 8, Hahn teaches the optoelectronic structure of claim 5, further and Hahn teaches a gap fill layer (Fig. 17B, portion of 1760 inbetween and corresponding to diodes 1770, ¶ [0144]) laterally surrounding each coupon and laterally between adjacent coupons (¶ [0131]. Hahn’s dielectric layer 1760 would be between adjacent sub arrays of Hahn’s two dimensional LED array).
Regarding claim 9, Hahn teaches the optoelectronic structure of claim 8, and Hahn teaches that the array of via contacts (Fig. 17B, 1780, ¶ [0144]) extends through (Fig. 17B) a portion of the gap fill layer (Fig. 17B, portion of 1760 inbetween and corresponding to diodes 1770, ¶ [0144]).
Regarding claim 18, Hahn teaches the optoelectronic structure of claim 5, and Hahn teaches a plurality of dummy vias (Fig. 17C, 1782, ¶ [0144]) adjacent the array of via contacts.
Regarding claim 19, Hahn teaches the optoelectronic structure of claim 18, and Hahn teaches that the plurality of dummy vias (Fig. 17C, 1782, ¶ [0144]) does not vertically overlap with the plurality of coupons (Fig. 17C, contacts 1782 does not vertically overlap with the array of Hahn’s LEDs 1770).
Regarding claim 20, Hahn teaches the optoelectronic structure of claim 1, and Hahn teaches that the micro-sized diodes (Fig. 17B, 1770, ¶ [0144]) of the array of micro-sized diodes are light emitting diodes (LEDs) (¶ [0144]).
Regarding claim 22, Hahn teaches the optoelectronic structure of claim 1, wherein the driving circuitry (Fig. 17A, 1720, ¶ [0143]) includes CMOS driving circuitry (¶ [0135] teaches that Hahn’s driver circuits can be made using CMOS processes).
Regarding claim 23, Hahn teaches the optoelectronic structure of claim 1, and Hahn teaches that the driving circuitry (Fig. 17A, 1720, ¶ [0143]) includes an array of pixel driver chips (¶ [0137]).
Regarding claim 24, Hahn teaches the optoelectronic structure of claim 1, and Hahn teaches that the micro-sized diodes includes a sub-array of regrown micro-size diodes, each regrown micro-sized diode including a p-doped layer (Fig. 15, 1540, ¶ [0131]), an n-doped layer (Fig. 15, 1520, ¶ [0131]), an active layer (Fig. 15, 1530, ¶ [0131]) between the p-doped layer and the n-doped layer, and a regrown layer (Fig. 15, 1560, ¶ [0132]) spanning across sidewalls of the p-doped layer the active layer and the n-doped layer.
Further, the language, term, or phrase "regrown layer", is directed towards the process of making a layer. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “regrown layer" only requires a sidewall layer, which does not distinguish the invention from Hahn, who teaches the structure as claimed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being obvious over HAHN (US Pub. No. 2022/0059740) in view of LEI et al. (US Pub. No. 2023/0335518).
Regarding claim 17, Hahn teaches the optoelectronic structure of claim 5.
However, Hahn does not explicitly teach that a placement distribution of the array of landing pads across the backplane is characterized by a first order standard deviation of displacement values of the array of landing pads to the array of contact pads, and position distribution of the array of via contacts across the backplane is characterized by a first order standard deviation of displacement values of the array of via contacts to the array of contact pads, and the first order standard deviation for the placement distribution of the array of landing pads across the backplane is larger than the first order standard deviation for the position distribution of the array of via contacts across the backplane.
However, Lei is a pertinent art that teaches a placement distribution of the array of landing pads (Fig. 15A, 1570, ¶ [0167]) across the backplane is characterized by a first order standard deviation of displacement values of the array of landing pads to the array of contact pads (Fig. 15A, 1530, ¶ [0167]), and position distribution of the array of via contacts across the backplane is characterized by a first order standard deviation of displacement values of the array of via contacts to the array of contact pads, and the first order standard deviation for the placement distribution of the array of landing pads across the backplane is larger than the first order standard deviation for the position distribution of the array of via contacts across the backplane (Fig. 15A, the placement/position distribution of Lei’s metal layers result in an offset deviation from the center of Lei’s micro LEDs (Fig. 15A, 1550, ¶ [0167]). Therefore, Hahn modified by Lei would fulfill this limitation).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the placement/position of Hahn’s contacting layers according to the teaching of Lei (Fig. 15A) in order to improve thermal performance (Lei ¶¶ [0002] & [0138]).
Claim 21 is rejected under 35 U.S.C. 103 as being obvious over HAHN (US Pub. No. 2022/0059740) in view of INOUE (US Pub. No. 2023/0132555).
Regarding claim 21, Hahn teaches the optoelectronic structure of claim 1, and Hahn teaches that the micro-sized diodes (Fig. 17B, 1770, ¶ [0144]) of the array of micro-sized diodes are photodetectors (PD) (Hahn’s micro LEDs would be capable of functioning as photodetectors because it is known in the art that LEDs can be used as photodetectors depending on the bias voltage. As evidence, see ¶ [0102] of Inoue).
Allowable subject matter
Claims 10-16 are objected to as being dependent upon a rejected base claim (claim 1), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record.
With respect to dependent claim 10, the cited prior art does not anticipate or make obvious, inter alia, the step of: “a coupon of the plurality of coupons includes a p-n diode layer comprising:a corresponding sub-array of micro-sized diodes;a pattern of intermediate p-n diode layer material laterally between the micro-sized diodes of the sub-array of micro-sized diodes;wherein the pattern of intermediate p-n diode layer material is separated from the sub- array of micro-sized diodes by trenches.”.
Claims 11-16 are dependent on claim 10.
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2022/0130890 by Chen et al discloses a micro led device.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2023/0352466 by Breakspear et al discloses micro led device.
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/R.P.S./
Examiner, Art Unit 2813
/STEVEN B GAUTHIER/ Supervisory Patent Examiner, Art Unit 2813