Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03 November 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 16-25 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto (US 20180349146) in view of Suresh (US 20190019267) and further in view of McCrary (US 20210192672).
Regarding claim 1, Iwamoto teaches an apparatus comprising: graphics processor circuitry, that includes:
Tracking slot circuitry that implements entry circuits for multiple tracking slots for the graphics processor circuitry (Paragraph 38, graphics processor includes… clusters… Each cluster further includes hardware resources organized into “slots”);
Queue access circuitry configured to access data that specifies multiple queues, wherein:
Respective queues store control information for multiple sets of graphics work (Paragraph 27, multiple process queues may provide data to a single cluster. For example, process queue A may provide a first portion of process data to cluster A and a second portion of process data A to cluster M; Paragraph 25, Image write buffer 125 may be configured to store processed tiles of an image and may further perform final operations to a rendered image before it is transferred to a frame buffer (e.g., in a system memory via memory interface 130);
Distribution circuitry configured to assign portions of the selected sets of graphics work from the tracking slots to graphics processor circuitry for execution (Paragraph 27, process queue A may provide a first portion of process data to cluster A and a second portion of process data A to cluster M);
While Iwamoto fails to disclose the following, Suresh teaches:
Queue select circuitry configured to select sets of graphics work based on one or more selection parameters and store control information for the selected sets of graphics work in ones of the entry circuits for the tracking slots of the tracking slot circuitry (Paragraph 101, virtual GPU manager may map the graphical processing request to the logical GPU based on one or more processing performance variables including at least processing capacity of the one or more discreet GPUs);
Suresh and Iwamoto are both considered to be analogous to the claimed invention because they are in the same field of logical partitioning of virtualized resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Iwamoto by using Suresh and select a set of graphics work based on one or more selection parameters and storing control information for that work. Doing so would prioritize the graphics work and have it completed more efficiently.
While the combination of Iwamoto and Suresh fails to disclose the following, McCrary teaches:
The data is to be stored in memory circuitry that is accessible to the graphics processor circuitry and also accessible to another processor that is configured to execute instructions to add sets of graphics work to the queues (Paragraph 9, An application executing on a central processing unit (CPU) provides commands to the GPUs and the subsets of the commands are added to queues in the GPUs that are programmed to execute the subsets); and
The sets of graphics work respective include instructions for execution by the graphics processor circuitry (Paragraph 13, Queues 145, 146, 147 (collectively referred to herein as “the queues 145-147”) are associated with the pipelines 141-143 and hold commands or command buffers for the corresponding queues 145-147);
Queue select circuitry configured to select sets of graphics work from the multiple queues (Paragraph 9, A scheduler in the primary GPU monitors the status of the doorbells in the table and causes the dependent commands to be released for execution)
The selection parameters include a dependency parameter encoded by a field of the data (Paragraph 9, a scheduler on the primary GPU determines whether the dependency is resolved by monitoring a corresponding entry in the table);
The field corresponds to a first set of graphics work in a first queue of the multiple queues (Paragraph 9, indicates locations of dependencies associated with commands in the queues of the GPUs);
The dependency parameter indicates a dependency of the first set of graphics work on a second set of graphics work stored in a second queue of the multiple queues (Paragraph 9, A primary GPU in the processing system maintains a data structure (such as a table) that indicates locations of dependencies associated with commands in the queues of the GPUs);
McCrary and the combination of Iwamoto and Suresh are both considered to be analogous to the claimed invention because they are in the same field of logical partitioning of virtualized resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Iwamoto and Suresh by using McCrary and use data in memory accessible to graphics processor circuity and another processor to execute instructions to add sets of graphics work to multiple queues and a dependency parameter corresponding to a first set of graphics work in a first queue that indicates a dependency on a second set of graphics work in a second queue. Doing so would prioritize the graphics work to complete more efficiently by completing dependencies first and spreading dependent work to different queues.
CRM claim 25 and method claim 29 correspond to apparatus claim 1. Therefore, claims 25 and 29 are rejected for the same reasons as used above.
Regarding claim 2, the combination of Iwamoto, Suresh and McCrary teaches the apparatus of claim 1, wherein the selection parameters include a work category parameter for a given set of graphics work, wherein the work category parameter indicates whether a given set of graphics work is compute work, fragment work, or geometry work (Iwamoto, Paragraph 21, use of a processing circuit hardware resource allocation system is disclosed herein where hardware resources (e.g., vertex shaders, fragment shaders, united shader clusters, registers, or computational units) form a plurality of clusters (components or circuits hosting said resources) of a processing system (e.g., a graphics processor) may be distributed between a plurality of processes in an equitable fashion (e.g., based on a target quality of service (QoS) metric)).
Regarding claim 3, the combination of Iwamoto, Suresh, and McCrary teaches the apparatus of claim 1, wherein the selection parameters include a resources available parameter provided by the graphics processor circuitry, wherein the resources available parameter indicates availability of different graphics processor hardware resources (Iwamoto, Paragraph 21, At least one of the clusters may include one or more hardware resource utilization sensors… the hardware resource arbitration circuit may allocate the available hardware resources).
Regarding claim 4, the combination of Iwamoto, Suresh, and McCrary teaches the apparatus of claim 1, wherein the selection parameters include a priority parameter for a given queue, wherein the different queues have different priority parameter values (Iwamoto, Paragraph 21, At least one of the clusters may include… a process priority list. The process priority list may store priorities for at least some of the processes).
Regarding claim 16, the combination of Iwamoto, Suresh, and McCrary teaches the apparatus of claim 1, wherein the graphics processor circuitry includes control circuitry configured to:
Write result data for completed sets of graphics work to completion queue structures in memory (Iwamoto, Paragraph 27, Process queues A-K may store data for a plurality of respective processes).
Regarding claim 17, the combination of Iwamoto, Suresh, and McCrary teaches the apparatus of claim 16, wherein the control circuitry is configured to write result data to multiple different completion queues (Iwamoto, Paragraph 27, Process queues A-K may store data for a plurality of respective processes) with different priorities (Iwamoto, Paragraph 21, At least one of the clusters may include… a process priority list. The process priority list may store priorities for at least some of the processes).
Regarding claim 18, the combination of Iwamoto, Suresh, and McCrary teaches the apparatus of claim 16, wherein the control circuitry is configured to write result data to different completion queues based on whether a given set of graphics work completed normally (Iwamoto, Paragraph 27, Process queues A-K may correspond to different functional aspects of the system). A functional aspect may refer to the result of executing a set of graphics work. Therefore, data may be written to different queues depending on the completion of the work.
Regarding claim 19, the combination of Iwamoto, Suresh, and McCrary teaches the apparatus of claim 16, wherein the control circuitry is further configured to program a set of registers (Iwamoto, Paragraph 28, In response, priority signals A-M may adjust the priorities so the second process is not allocated any of the registers half of the time) indicated by a set of graphics work in response to completion of the set of graphics work (Iwamoto, Paragraph 27, Process queues A-K may correspond to different functional aspects of the system).
Regarding claim 20, the combination of Iwamoto, Suresh, and McCrary teaches the apparatus of claim 1, wherein the graphics processor circuitry is configured to execute firmware to provide one or more of the sets of graphics work for a queue of the multiple queues (Suresh, Paragraph 46, firmware can be stored within a memory element in the physical memory and can be executed by one or more of the physical processors).
Suresh and the combination of Iwamoto and McCrary are both considered to be analogous to the claimed invention because they are in the same field of logical partitioning of virtualized resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Iwamoto and McCrary by using Suresh and execute firmware to provide one or more sets of graphics work. Doing so would allow for utilizing a known resource to divide work between queues.
Regarding claim 21, the combination of Iwamoto, Suresh, and McCrary teaches the apparatus of claim 1, further comprising:
Memory circuitry configured to store the data (Suresh, Paragraph 46, memory element in the physical memory); and
Processor circuitry configured to execute program instructions to add control information to queues of the data (Suresh, Paragraph 46, memory element in the physical memory and can be executed by one or more of the physical processors).
Suresh and the combination of Iwamoto and McCrary are both considered to be analogous to the claimed invention because they are in the same field of logical partitioning of virtualized resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Iwamoto and McCrary by using Suresh and use memory circuity to store the data and add control information to queues of data. Doing so would allow for utilizing known methods of processing data in queues.
Regarding claim 22, the combination of Iwamoto, Suresh, and McCrary teaches the apparatus of claim 1, wherein the graphics processor circuitry includes control circuitry configured to control which sets of graphics work trigger interrupts on completion (Iwamoto, Paragraph 20, the lower priority task may be released to resume execution when, for example, the conditions that triggered the pause are resolved).
Regarding claim 23, the combination of Iwamoto, Suresh, and McCrary teaches the apparatus of claim 1, wherein the graphics processor circuitry includes:
A plurality of single-instruction multiple-data pipelines configured to execute instructions (Iwamoto, Paragraph 24, process data (e.g., graphics data) in parallel using multiple execution pipelines); and
Fixed-function circuitry configured to control the single-instruction multiple-data pipelines to perform operations for at least one of the following types of programs:
Graphics shader programs (Iwamoto, Paragraph 24, programmable shader); and machine learning programs (Iwamoto, Paragraph 24, texture processing unit (TPU)). TPUs can be used to assist in machine learning.
Regarding claim 24, the combination of Iwamoto, Suresh, and McCrary teaches the apparatus of claim 1, wherein the apparatus is a computing device that further comprises:
A display (Suresh, Paragraph 48, a display device);
A central processing unit (Suresh, Paragraph 65, one or more integrated CPU); and
A network interface (Suresh, Paragraph 48, a network interface card).
Suresh and the combination of Iwamoto and McCrary are both considered to be analogous to the claimed invention because they are in the same field of logical partitioning of virtualized resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Iwamoto and McCrary by using Suresh and use a display, central processing unit, and network interface. Doing so would allow for utilizing known methods of processing data in queues.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto in view of Suresh and further in view of McCrary as applied to claims 1-4, 16-25 and 29 and further in view of Oidate (WO 2018235124).
Regarding claim 5, the combination of Iwamoto, Suresh, and McCrary teaches the apparatus of claim 1. While the combination fails to disclose the following, Oidate teaches:
Wherein the selection parameters include a deadline parameter included in the data structure for a given set of graphics work (Page 12, paragraph 7, The deadline is the required time from the start to the end of the operation process, the leading constraint that defines the execution order among the plurality of operation processes).
Oidate and the combination of Suresh, Iwamoto, and McCrary are both considered to be analogous to the claimed invention because they are in the same field of scheduling virtualized resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Iwamoto, Suresh, and McCrary by using Oidate and selecting work based on a deadline parameter. Doing so would prioritize the graphics work and have each unit of work completed by its own deadline.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto in view of Suresh and further in view of McCrary as applied to claims 1-4, 16-25 and 29 and further in view of Ashbaugh (JP 2021099786).
Regarding claim 8, the combination of Iwamoto, Suresh, and McCrary teaches the apparatus of claim 1. While the combination fails to disclose the following, Ashbaugh teaches:
Wherein the queue select circuitry is configured to pause selection from the first queue and select sets of graphics work from the second queue in response to the dependency parameter (Page 16, paragraph 2, while waiting for data from memory or one or the shared functions, the dependent logic in execution units 508A-508N triggers a wait thread to pause activity until the requested data is returned. While the waiting thread is paused, hardware resources may be devoted to processing other threads).
Ashbaugh and the combination of Iwamoto, Suresh, and McCrary are both considered to be analogous to the claimed invention because they are in the same field of managing virtualized resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Iwamoto, Suresh, and McCrary by using Ashbaugh and pausing selection from the first queue and select work from a second queue in response to the dependency parameter. Doing so would prioritize the graphics work to complete more efficiently by completing dependencies first and spreading dependent work to different queues.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto in view of Suresh and further in view of McCrary as applied to claims 1-4, 16-25 and 29 and further in view of Genden (US 20200042321).
Regarding claim 9, the combination of Iwamoto, Suresh, and McCrary teaches the apparatus of claim 1. While the combination fails to disclose the following, Genden teaches:
A dependency parameter for a given set of graphics work includes a set of parent identifiers and a valid parents mask indicating which parent identifiers are valid (Paragraph 19, identifying that a dependent source of a younger instruction is a result of an older instruction includes identifying which dependent source of the available dependent sources of the younger instruction is dependent on the results of execution of the older instruction, and setting a source wakeup selection bit of the plurality of source wakeup selection bits corresponding to the dependent source of the younger instruction); Genden teaches a child (younger) instruction that has a set of parents (available dependent sources) that is able to determine which parent (source/older instruction) it was called by in order to set the specific wake up bit. Therefore, the child work has a set of parents and is able to determine which ones are valid.
The dependency parameter is specified in a manner that is independent of tracking slots to which sets of graphics work are assigned (Paragraph 44, individual instructions are non- fused, non-paired instructions placed independently into the double issue queue).
Genden and the combination of Iwamoto, Suresh, and McCrary are both considered to be analogous to the claimed invention because they are in the same field of managing virtualized resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Iwamoto, Suresh, and McCrary by using Genden and identifying valid parent work independent of the queue of the child work. Doing so would allow child work to notify parent work when it is completed without needing to store extra information like where the parent work is located.
Claims 10-11, 27 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto in view of Suresh and further in view of McCrary as applied to claims 1-4, 16-25 and 29 and further in view of Uhrenholt (US 20220020108).
Regarding claim 10, the combination of Iwamoto, Suresh, and Uhrenholt teaches the apparatus of claim 1. While the combination fails to disclose the following, Uhrenholt teaches:
The selection parameters include an event flag parameter encoded by a second field of the data, wherein the second field corresponds to the first set of graphics work (Paragraph 105, maintaining appropriate dependency counters (slots) that track outstanding register affecting transactions and that can be used to determine when any outstanding register affecting transactions have been completed);
The event flag parameter indicates one or more software-programmable event flags on which the first set of graphics work depends (Uhrenholt, Paragraph 105, the system is operable to track, e.g. by means of appropriate counters, any register affecting transaction dependencies); and
The queue select circuitry is configured to pause selection from the first queue based the first set of graphics work waiting for the one or more software-programmable event flags (Paragraph 26-27, stopping the issuing of shader program instructions for execution by the group of one or more execution threads; waiting for any outstanding transactions for the group of one or more execution threads that affect the content of the registers associated with the threads of the group of one or more execution threads to complete).
Uhrenholt and the combination of Iwamoto, Suresh, and McCrary are both considered to be analogous to the claimed invention because they are in the same field of managing virtualized resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Iwamoto, Suresh, and McCrary by using Uhrenholt and encode a second field of data, have an event flag parameter that indicates a software-programmable event flag on which the first set of graphics work depends, and pause selection from a first queue based on waiting for work. Doing so would allow for implementing a dependency on sets of graphics work.
CRM claim 27 and method claim 30 correspond to apparatus claim 10. Therefore, claims 27 and 30 are rejected for the same reasons as used above.
Regarding claim 11, the combination of Iwamoto, Suresh, McCrary, and Uhrenholt teaches the apparatus of claim 10, wherein at least one of the event flags is encoded as a counter value (Uhrenholt, Paragraph 106, using appropriate dependency counters (slots) to count any outstanding dependencies).
Uhrenholt and the combination of Iwamoto, Suresh, and McCrary are both considered to be analogous to the claimed invention because they are in the same field of managing virtualized resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Iwamoto, Suresh, and McCrary by using Uhrenholt and use a counter. Doing so would allow for implementing multiple dependencies on sets of graphics work.
Claims 12-14 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto in view of Suresh and further in view of McCrary and further in view of Uhrenholt as applied to claims 10-11, 27 and 30 and further in view of Ashok (CN 111767080).
Regarding claim 12, the combination of Iwamoto, Suresh, McCrary, and Uhrenholt teaches the apparatus of claim 10. While the combination fails to disclose the following, Ashok teaches:
A group of sets of graphics work are not dependent on one another (Page 27, paragraph 6, assuming that this particular load in the figure does not specify the dependency), are included in at least two different queues (Page 27, paragraph 5, the dependency token (which may be a single bit) arrives in queues 1018 and 1020), and target a first hardware resource (Page 25, paragraph 2, the embodiment of the invention provides hardware support for multicast in the local network; Page 28, paragraph 1, completion buffer sends the result back to the local network); The graphics work targets a hardware resource because the results are sent back to the local network, and Ashok teaches hardware for the local network.
Control circuitry is configured to, for a launched set of graphics work in the group of sets, set an event flag to acquire the first hardware resource and prevent other sets of graphics work from launching until the event flag is cleared (Page 27, paragraph 5, the memory sequencing circuit… may pause scheduling the new memory operation until the dependency token counter becomes unsaturated).
Ashok and the combination of Iwamoto, Suresh, McCrary, and Uhrenholt are both considered to be analogous to the claimed invention because they are in the same field of managing virtualized resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Iwamoto, Suresh, and McCrary by using Ashok and prioritize graphics work based on dependencies and an event flag. Doing so would allow for the graphics processor to have more control over which queues are executing and increase efficiency overall.
Regarding claim 13, the combination of Iwamoto, Suresh, McCrary, and Uhrenholt teaches the apparatus of claim 10. While the combination fails to disclose the following, Ashok teaches:
Another processor of the apparatus is configured to perform image processing on graphics frame data generated by the graphics processor circuitry (Page 22, paragraph 1, an array of processing elements… the image is configured to perform the same operation according to the data stream); and
The apparatus is configured to execute program instructions to utilize event flag parameters to indicate when subsets of a frame of graphics data have completed processing by the other processor and are ready for the graphics processor circuitry (Page 13, paragraph 2, selected input channel will make its data (e.g., token) is removed (e.g., discarded), for example, to finish the execution of the data stream operation (or a portion of its data stream operation)).
Ashok and the combination of Iwamoto, Suresh, McCrary, and Uhrenholt are both considered to be analogous to the claimed invention because they are in the same field of managing virtualized resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Iwamoto, Suresh, McCrary, and Uhrenholt by using Ashok and prioritize graphics work based on dependencies and an event flag. Doing so would allow for the graphics processor to have more control over which queues are executing and increase efficiency overall.
CRM claim 28 corresponds to apparatus claim 13. Therefore, claim 28 is rejected for the same reasons as used above.
Regarding claim 14, the combination of Iwamoto, Suresh, McCrary, and Uhrenholt teaches the apparatus of claim 10. While the combination fails to disclose the following, Ashok teaches:
Wherein the apparatus is configured to control at least one event based on tasks performed by one or more other circuit components of the apparatus that are external to the graphics processing circuitry (Page 42, paragraph 3, a single face may receive a service command to an external controller… the area controller can coordinate some interlayer network station).
Ashok and the combination of Iwamoto, Suresh, McCrary, and Uhrenholt are both considered to be analogous to the claimed invention because they are in the same field of managing virtualized resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Iwamoto, Suresh, and Uhrenholt by using Ashok and control events for components of the apparatus that are external to the graphics processing circuitry. Doing so would allow for the graphics processor to increase efficiency overall by centralizing control of the larger apparatus.
Claims 15 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Iwamoto in view of Suresh and further in view of McCrary and further in view of Uhrenholt as applied to claims 10-11, 27 and 30 and further in view of Tremblay (US 7664942).
Regarding claim 12, the combination of Iwamoto, Suresh, McCrary, and Uhrenholt teaches the apparatus of claim 10. While the combination fails to disclose the following, Tremblay teaches:
Wherein the graphics process circuitry includes control circuitry configured to control a partial render procedure, including to:
Halt all sets of graphics work that depend on a geometry set of work (Column 2, paragraph 2, halts executing program code);
Schedule a first copy of a fragment set of work that operates on data from the geometry set of work (Column 2, paragraph 2, updates a state of the subordinate strand by copying a present state of the primary strand into the subordinate strand);
Restart the geometry set of work subsequent to execution of the first copy of the fragment set of work (Column 2, paragraph 2, copies a program counter for the branch and other state information from the primary strand to the subordinate strand to enable the subordinate strand to restart the execution);
And configure a second copy of the fragment set of work to resume from a partial render image generated by the first copy of the fragment set of work (Column 6, paragraph 5, processor can include one or more additional copies of some or all of the hardware structures in a given strand (shadow copies), which can be used when copying the architectural state of the strand).
Tremblay and the combination of Iwamoto, Suresh, McCrary, and Uhrenholt are both considered to be analogous to the claimed invention because they are in the same field of managing virtualized resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Iwamoto, Suresh, McCrary, and Uhrenholt by using Tremblay and indicating performing steps to stop, copy, and restart graphics work. Doing so would allow for the graphics processor to have more control over work being executed and make adjustments in real time.
Method claim 31 corresponds to apparatus claim 15. Therefore, claim 31 is rejected for the same reasons as used above.
Response to Arguments
Applicant’s arguments with respect to claim 1 has been considered but are moot because the new ground of rejection does not rely on any rejection applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. McCrary teaches the amended portions of claim 1 regarding that the graphics work includes instructions for execution, that the work is accessible to the graphics processor and to another processor, and describes in detail how dependency is handled via a table. Therefore, the combination of Iwamoto, Suresh, and McCrary teaches the apparatus of claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SNIGDHA SINHA whose telephone number is (571)272-6618. The examiner can normally be reached Mon-Fri. 12pm-8pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jason Chan can be reached at 571-272-3022. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SNIGDHA SINHA/Examiner, Art Unit 2619
/JASON CHAN/Supervisory Patent Examiner, Art Unit 2619