Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office acknowledges receipt of the following items from the Applicant:
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in the
file.
Information Disclosure Statement (IDS) filed on 8/17/23 was considered.
In response to the restriction requirement:
Applicant elected Group II, claims 7-14 for examination.
Group I and III are non-elected group and are withdrawn from
consideration.
Specification
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 7-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Doo et al, Patent Application Publication No. 2017/0117033.
With regard to claim 7, Doo discloses a memory device (fig.1, 110), comprising: a plurality of rows (fig. 1, bank 0-3, with plurality of rows corresponding to WL), (page 3, [0043], line 1-13) each accessible by a row address (page 3, [0044]), a counting control circuit (fig. 1, counter 158) configured to activate, according to an active command (fig. 1, CMD), a row selection signal corresponding to the row address (page 4, [0047]); and
a partial counting circuit (fig.9A, 156) configured to generate a counting signal (fig. 9A, CNT(0)-(6) via 916) and a carry output signal (fig. 9A, Carry_Out signal) by counting, according to the row selection signal (page 4, [0047), a carry input signal (fig. 9A, PCSC)(page 8, [0098]), provided through a carry input pad (fig. 9A, inherent input pad carry input signal), and provide the carry output signal (fig. 9A, 9A, Carry_Out) signal through a carry output pad (fig. 9A, inherent output pad carry output signal).
With regard to claim 8, Doo further discloses a storing circuit (fig. 9A, 810) configured to store the counting signal (fig. 9A, CNT(6:0]) according to the row selection signal; and a data input/output circuit configured to output a signal stored in the storing circuit (fig. 9A, 820) through inherent data pads (page 8, [0101]).
With regard claim 9, Doo discloses the memory device further comprising one or more counting pads configured to output the counting signal (page 8, [0101]).
Allowable Subject Matter
Claim 10-14 are objected as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record does not show the limitation of wherein each of the carry input pad and the carry output pad is a single pad (claim 10),
The prior art of record does not show the limitation of wherein the counting control circuit is further configured to activate, according to a refresh management command, a row reset signal corresponding to the row address, and wherein the partial counting circuit is further configured to initialize the counting signal according to the row reset signal (claim 11).
The prior art of record does not show the limitation of wherein the partial counting circuit includes: a plurality of partial row counters respectively corresponding to the plurality of rows and coupled in common to the carry input pad, wherein each partial row counter is configured to: generate the counting signal by counting the carry input signal according to the row selection signal, and output an overflow signal when the counting signal is fully counted; and an output selection circuit configured to output the carry output signal by selecting, according to the row selection signal, one of the overflow signals from the plurality of partial row counters (claims 12-14).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicants’ disclosure. Kim et al (2023/0185460) disclose a includes a memory cell array, a row hammer management circuit and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The row hammer management circuit counts the number of instances of access of each of the memory cell rows, such as in response to the receipt of an active command, to store the counted values in count cells of each of the memory cell rows as count data and, in response to a first command, initiates an internal read-update-write operation to read the count data, to update the read count data, and to write the updated count data in the count cells. The control logic circuit may performs an internal write operation to write the updated count data in the count cells during a second write time interval that is smaller than a first write time interval associated with a normal write operation.
When responding to the office action, Applicants’ are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
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/CONNIE C YOHA/Primary Examiner, Art Unit 2825