Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 15, 2025 has been entered.
Response to Amendment
Applicant’s amendment submitted on December 15, 2025 necessitated the new ground(s) of rejection presented in this Office action.
Claims 2 and 9 have been cancelled in the amendment.
Claim Objections
Claim 5 is objected to because of the following informalities:
Claim 5, line 2 “configured to read the second target data” should read “configured to read second target data”. The word “the” was removed in a prior amendment, and as the claim is submitted under the label previously presented, the applicant likely did not intend to reintroduce the word “the” to the claim language.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1, 3-8, and 10-15 are rejected under 35 U.S.C. 112(a), as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention
Amended claim 1 recites “when the cold data is read from the map cache, free space in the map cache is obtained by evicting a map unit in the map cache corresponding to a part of the cold data read from the map cache”. The applicant cites the cancelled claims and paragraphs 116-117 and 137-145 of the specification as providing support for the claimed limitation, however, the claim limitation is not supported either in those locations nor elsewhere in the disclosure. Paragraph 145 recites “Since the target data TGT_DATA is cold data, it is unlikely that a part read once from the target data TGT_DATA will be read again in the near future. Accordingly, the free space of the map cache MAP_CACHE may be secured by evicting the map unit corresponding to the part read once from the map cache MAP_CACHE”, however cached map units corresponding to cold target data are not equivalent to the claimed subject matter of the cold data being read from the map cache. There also does not appear to be support in the disclosure for the cold data being stored in the map cache (from where it is claimed to be read). Therefore the amendments to claims 1 introduce new subject matter, failing the written description requirement of 112(a).
Claims 8 and 15 recite similar claim limitations to claim 1 and are rejected under 112(a) following the same rationale.
Claim 15 additionally recites “wherein the access request includes a write command and a read command”. The applicant cites the cancelled claims and paragraphs 116-117 and 137-145 of the specification as providing support for the claimed limitation, however, the claim limitation is not supported either in those locations nor elsewhere in the disclosure. Paragraphs 30-31 of the specification do disclose requests including one of a write command or a read command “The memory 110 may receive a command and an address from the controller 120 and may access an area in the memory cell array that is selected by the address. The memory 110 may perform an operation indicated by the command, on the area selected by the address. The memory 110 may perform a program operation, a read operation or an erase operation”, but a request including both a write command and a read command, as claimed, is not disclosed and amounts to new subject matter. Therefore claim 15 fails to satisfy the requirements of 112(a).
Claims 3-7 and 10-14 depend on claims rejected under 112(a) and therefore also fail to satisfy the requirements of 112(a).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 3-8, and 10-15 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a memory including a plurality of memory blocks; and a controller configured to write target data, which is cold data, to consecutive target memory blocks among the plurality of memory blocks … the target data is the cold data … when the cold data is read from the map cache, free space in the map cache is obtained by evicting a map unit in the map cache corresponding to a part of the cold data read from the map cache”, however, it is unclear how the cold data is read from the map cache if the cold data is stored in the plurality of memory blocks of the memory. Furthermore, as claim 1 recites “during a read of the target data from the consecutive target memory blocks, a plurality of map units are cached into a map cache”, the map units are not present in the map cache until the cold data is read from the memory blocks. Therefore, even if there was cold data in the map cache to be read, the storage device, as claimed, would not be able perform the claimed functionality of evicting a map unit corresponding to a part of the cold data read from the map cache, unless a read of the cold data from the memory blocks had previously occurred. However, a limitation of performing the read from the memory blocks prior to the read from the map cache is not recited in the claim. Thus the scope of the claim is unclear and claim 1 fails to satisfy the requirements of 112(b). For the purposes of examination, claim 1 has been interpreted as if it recited either of “when the cold data is read from the consecutive target memory blocks, free space in the map cache is obtained by evicting a map unit in the map cache corresponding to a part of the cold data read from the consecutive target memory blocks” or “when a map unit in the map cache corresponding to a part of the cold data is read, free space in the map cache is obtained by evicting the map unit corresponding to a part of the cold data”.
Claims 8 and 15 recite similar claim limitations to claim 1 and are rejected under 112(b) following the same rationale.
Claims 3-7 and 10-14 depend on claims rejected under 112(b) and therefore also fail to satisfy the requirements of 112(b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6, 7-8, 11-14, and 15, as best understood and interpreted by the examiner in light of the 112(b) rejection above, are rejected under 35 U.S.C. 103 as being unpatentable over Moon et al. (U.S. patent application publication 20230195386 A1), hereinafter referred to as Moon, in view of Goss et al. (U.S. patent application publication 20110225347 A1), hereinafter referred to as Goss, further in view of Gupta et al. (Aayush Gupta, Youngjae Kim, and Bhuvan Urgaonkar. 2009. DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings. SIGPLAN Not. 44, 3 (March 2009), 229–240. [online], [retrieved on 2026-03-20]. Retrieved from the Internet <URL: https://doi.org/10.1145/1508284.1508271>), hereinafter referred to as Gupta, further in view of Kachare et al. (U.S. patent application publication 20230195351 A1 with an effective filing date of January 24th, 2022), hereinafter known as Kachare.
Regarding claim 1, Moon teaches a storage device (storage device 300) comprising: a memory including a plurality of memory blocks (Fig. 4 and “The memory cell array 510 may be divided into a plurality of memory blocks” [Moon paragraph 89]); and a controller (storage controller 310) configured to write target data, which is cold data, to consecutive target memory blocks among the plurality of memory blocks (“The storage device according to example embodiments may operate based on a nonvolatile memory express (NVMe) protocol” [Moon paragraph 106]. Thus, the NVMe specification is incorporated into the device of Moon. The NVM Express NVM Command Set Specification, Revision 1.0c published on October 3rd, 2022 (NVM Express NVM Command Set Specification, Revision 1.0c. Datasheet [online]. NVM Express, Inc., 2022 [retrieved on 2025-03-03]. Retrieved from the Internet: <URL: https://nvmexpress.org/wp-content/uploads/NVM-Express-NVM-Command-Set-Specification-1.0c-2022.10.03-Ratified-1.pdf>.), hereinafter referred to as the Command Spec, discloses in figure 62: Write – Command Dword 10 and Command Dword 11 Starting LBA “This field indicates the 64-bit address of the first logical block to be written” and figure 63 “Number of Logical Blocks (NLB): This field indicates the number of logical blocks to be written.” These aspects of the write command in the Command Spec describe a sequential write starting at the Starting LBA and continuing for the Number of Logical Blocks. As the device of Moon follows the NVMe protocol, it would be able to perform this sequential write. Additionally, when the cold data flag is present, the target data would be cold data (The Command Spec in Figure 64 “Access Frequency” values “2h - Infrequent writes and infrequent reads to the LBA range indicated.” “3h - Infrequent writes and frequent reads to the LBA range indicated.” “6h - One time write.” These access frequency values would indicate cold data as according to the instant application, “data that is unlikely to be modified after being written once (e.g., write-once-read-only multimedia file) may be classified as cold data” [paragraph 5])), when receiving a write command which requests to write the target data, (Moon abstract “a data write request is received” and the Command Spec 3.2.6 Write command “The Write command writes data and metadata, if applicable, to the I/O controller for the logical blocks indicated.”) wherein the write command includes an identifier for the target data (The Command Spec Figure 60: Write – Data Pointer “Data Pointer (DPTR): This field specifies the location of a data buffer where data is transferred from”. The Command Spec additionally discloses a metadata pointer that can also function as an identifier [Figure 59]. In an alternative embodiment, spatial information can serve as an identifier [Moon paragraphs 7 and 8]), a size of the target data (The Command Spec Figure 63 “Number of Logical Blocks (NLB): This field indicates the number of logical blocks to be written.”), and a flag indicating that the target data is the cold data (The Command Spec in Figure 64 “Access Frequency” values “2h - Infrequent writes and infrequent reads to the LBA range indicated.” “3h - Infrequent writes and frequent reads to the LBA range indicated.” “6h - One time write.” These access frequency values would indicate cold data as according to the instant application, “data that is unlikely to be modified after being written once (e.g., write-once-read-only multimedia file) may be classified as cold data” [paragraph 5]) a read of the target data from the consecutive target memory blocks, (the Command Spec Figs. 47 and 48 teach a read command comprising a “Starting LBA (SLBA): This field indicates the 64-bit address of the first logical block to be read as part of the operation” and “Number of Logical Blocks (NLB): This field indicates the number of logical blocks to be read.” These amount to a teaching of a consecutive read starting with the SLBA and continuing for the following NLB number of logical blocks) a map cache within the controller separate from the consecutive target memory blocks, (Moon Fig. 3 depicts the flash translation layer 430 which comprises the logical to physical mapping table 436 separate from other memories) each map unit indicating a mapping relationship between one logical address and one physical address of the target data, (As disclosed in The NVM Express Base Specification, Revision 2.0c, published on October 4th, 2022 (NVM Express Base Specification, Revision 2.0c, Revision 1.0c. Datasheet [online]. NVM Express, Inc., 2022 [retrieved on 2025-03-03]. Retrieved from the Internet: <URL: https://nvmexpress.org/wp-content/uploads/NVM-Express-Base-Specification-2.0c-2022.10.04-Ratified-1.pdf>.), hereinafter referred to as the Base Spec, section 4.1.1 Physical Region Page Entry and List “A physical region page list (PRP List) is a set of PRP entries in a single page of contiguous memory”. The PRP list would serve as the target map information and the entries in the list would serve as the map units (see also the rejection to claim 4 below)) wherein the identifier, the size of the target data, and the flag are included in a reserved area of the write command corresponding to fields of DWORD #2, DWORD #3 of the write command, wherein the fields of DWORD #2 are allocated to the identifier of the target data and the flag, and the fields of the DWORD#3 are allocated to the size of the target data, (as disclosed in the Base Spec, the identifier can have an area reserved for it [“Metadata Pointer, PRP Entry 1, PRP Entry 2, and Metadata SGL Segment Pointer are not used by all commands” (The PRP Entries can form the data pointer, as in Figure 87 of the Base Spec)], the size of the target data can be in a reserved area [Base Spec Figure 87: Common Command Format Command Dwords 2-3 and 10-15 “This field [these Dwords] is command specific” and Command Spec Figure 63: Figure 63: Write – Command Dword 12 “Number of Logical Blocks”. Dword 12 is a reserved area so the number of logical blocks – the data size – also is], and the flag can also be in a reserved area (it is part of command dword 13 [see Command Spec Figure 64] which is within reserved dwords 10-15. The fields used for the identifier, the size of the target data, and the flag would be a reserved area for those respective fields. As the Base Spec and Command Spec teach having reserved DWORDs 2-3 and the usage of reserved areas in the commands for the identifier, the size of the target data, and the flag, it would have been obvious to a person having ordinary skill in the art to put the identifier, the size of the target data, and the flag in reserved DWORDs 2-3 as any ordering of the fields and DWORDs would be an arbitrary design decision with functional equivalence. The examiner also notes that in the broadest reasonable interpretation of the claim, the numbering assigned to the DWORDs is arbitrary, so it would be patentably equivalent to store the identifier, the size of the target data, and the flag in any reserved DWORD).
Moon does not appear to explicitly disclose wherein, during a read of the target data from the consecutive target memory blocks, a plurality of map units are cached into a map cache and wherein physical addresses for writing the cold data corresponding to the consecutive target memory blocks are consecutive to each other, wherein, when the cold data is read from the map cache, free space in the map cache is obtained by evicting a map unit in the map cache corresponding to a part of the cold data read from the map cache.
However, Gupta teaches wherein, during a read of the target data from the consecutive target memory blocks, a plurality of map units are cached into a map cache (“A request is serviced by reading from or writing to pages in the data blocks while the corresponding mapping updates are performed.” [Gupta page 234]; “Algorithm 1 describes the process of address translation for servicing a request. If the required mapping information for the given read/write request exists in SRAM (in CMT), it is serviced directly by reading/writing the data page on flash using this mapping information. If the information is not present in SRAM then it needs to be fetched into the CMT from flash” [Gupta page 234], wherein CMT stands for cached mapping table and the mapping information is comprised of map units indicating logical to physical address relationships [Gupta page 234]. As Gupta teaches caching mapping information during a read, in combination with Moon’s read of the target data from the consecutive target memory blocks, it would have been obvious to a person having ordinary skill in the art to cache mapping information during a read of the target data from the consecutive target memory blocks)
Moon and Gupta are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Moon and Gupta before him or her, to modify the apparatus of Moon to include the attributes of wherein, during a read of the target data from the consecutive target memory blocks, a plurality of map units are cached into a map cache of Gupta because it will enhance apparatus efficiency.
The motivation for doing so would be the demand-based flash translation layer of Gupta improves storage system performance [Gupta abstract].
Therefore, it would have been obvious to combine Moon and Gupta to obtain the invention as specified in the instant claim.
Gupta also does not appear to explicitly disclose and wherein physical addresses for writing the cold data corresponding to the consecutive target memory blocks are consecutive to each other, wherein, when the cold data is read from the map cache, free space in the map cache is obtained by evicting a map unit in the map cache corresponding to a part of the cold data read from the map cache.
However, Goss teaches and wherein physical addresses for writing the cold data corresponding to the consecutive target memory blocks are consecutive to each other (“in this example there are eleven logical blocks classified as read-cold or write-cold and five of the eleven logical blocks classified as write-cold or read-cold are stored in memory storage block 56. Controller 12 may store the remaining eight logical blocks classified as write-cold or read-cold in another memory storage block. As illustrated in FIG. 4D, memory storage block 60 may store the remaining eight logical blocks classified as write-cold in physical blocks 62A-62C. As described above, in some examples, controller 12 may classify a logical block based on a numerical classification that indicates the frequency of access of that logical block. In the example illustrated in FIGS. 5A-5D, controller 12 may classify logical blocks based on a numerical classification and group logical blocks in common memory storage blocks based on their numerical classification” [Goss paragraphs 98-99]. In Goss Fig. 4D, the cold data is depicted+ having been written in consecutive physical memory blocks/addresses. Similarly in Goss Figs. 5C and 5D, cold data is depicted having been written in consecutive physical memory blocks/addresses).
Moon/Gupta and Goss are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Moon/Gupta and Goss before him or her, to modify the apparatus of Moon/Gupta to include the attributes of wherein physical addresses for writing the cold data corresponding to the consecutive target memory blocks are consecutive to each other of Goss because it will enhance apparatus efficiency.
The motivation for doing so would be that it would reduce write amplification. See Goss paragraph 59 “aspects of this disclosure may mitigate against read disturb, as well as, reduce write amplification. Write amplification may be the number of physical blocks whose data needs to be transferred during garbage collection. Write amplification may create wear on the physical blocks. Accordingly, it may be beneficial to reduce the number of logical blocks that need to be transferred during garbage collection.”
Therefore, it would have been obvious to combine Moon/Gupta and Goss to obtain the invention as specified in the instant claim.
Goss also does not appear to explicitly disclose wherein, when the cold data is read from the map cache, free space in the map cache is obtained by evicting a map unit in the map cache corresponding to a part of the cold data read from the map cache.
However, Kachare teaches wherein, when the cold data is read from the map cache, free space in the map cache is obtained by evicting a map unit in the map cache corresponding to a part of the cold data read from the map cache (“auto-deleting a logical block when the number of read operations performed on the logical block reaches a predefined, host-specified limit or “threshold value”. The host may specify, e.g., with a write command, the expected number of reads for the data being written; once the expected number of reads has been reached, the persistent storage device may immediately invalidate the data” [Kachare par. 47] and “The FTL maintains a logical to physical address mapping table and keeps a record of the physical flash location for all logical blocks of data. The SSD controller stores the expected number of reads parameter received from the host IO write command for each logical block and counts the number of reads performed on that logical block (e.g., by incrementing a read counter in the logical to physical address mapping table, in response to the receiving of each read command). The SSD controller then arranges for the deletion of the logical block, e.g., (i) it deletes the data or (ii) it invalidates the logical block in the logical to physical address mapping table once the read counter reaches a threshold number (e.g., the expected number of reads). Like logical blocks that are invalidated as a result of delete (e.g., Trim) commands or overwrite commands received from the host, logical blocks that are invalidated by the SSD controller as a result of the read counter having reached the expected number of reads may be erased during garbage collection (instead of moving them to a clean physical block)” [Kachare par. 48]. It would have been obvious to a person having ordinary skill in the art to evict data from the map cache in view of Kachare teaching the SSD controller invalidating data in the mapping table (synonymous with map cache) and eventually deleting data associated with the mapping data. For example, the invalidating data and marking data for garbage collection as in Kachare teaches the claimed concept of freeing space after reading data as many times as it is expected to be read. See also Kachare Fig. 2C which shows data with an expected read count of 1, which is functionally equivalent to a flag for cold data).
Moon/Gupta/Goss and Kachare are analogous art because they are both in the field of data storage.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Moon/Gupta/Goss and Kachare before him or her, to modify the device of Moon/Gupta/Goss to include the wherein, when the cold data is read from the map cache, free space in the map cache is obtained by evicting a map unit in the map cache corresponding to a part of the cold data read from the map cache of Kachare because it will improve the efficiency of the storage device when handling cold data.
The motivation for doing so would be “In the case without an auto-delete feature, however, some of the storage space is consumed by obsolete user data 220 (data no longer needed by the host, but not yet deleted or overwritten by the host). The amount of free user space 210 is greater, as illustrated, when an auto-delete feature is used. The use of an auto-delete feature may reduce the background data traffic and reserve more resources and bandwidth for host IO operations” (Kachare paragraph 54).
Therefore, it would have been obvious to combine Moon/Gupta/Goss and Kachare to obtain the invention as specified in the instant claim.
Regarding claim 8, the applicant is directed to the rejection to claim 1 set forth above, as they are rejected based on the same rationale.
Regarding claim 15, the applicant is directed to the rejection to claim 1 set forth above, as they are rejected based on the same rationale, with the additional rationale that wherein the access request includes a write command and a read command for the target data as the cold data would have been obvious to a person having ordinary skill in the art in view of the read and write commands for the target data as the cold data as taught by Moon/Gupta/Goss/Kachare (see above). For example, it would have been obvious to directly combine the cited read and write commands into a single request to achieve the obvious result of a single a single request comprising both commands, for example in order to reduce the number of requests issued.
Regarding claim 4, Moon/Gupta/Goss/Kachare teach the storage device according to claim 1, wherein the controller writes the target data (“The storage controller 310 may control an operation of the storage device 300, e.g., a data write operation” Moon paragraph 59) by: sequentially writing the target data to the target memory blocks; (“The storage device according to example embodiments may operate based on a nonvolatile memory express (NVMe) protocol” [Moon paragraph 106]. The Command Spec, discloses in figure 62: Write – Command Dword 10 and Command Dword 11 Starting LBA “This field indicates the 64-bit address of the first logical block to be written” and figure 63 “Number of Logical Blocks (NLB): This field indicates the number of logical blocks to be written.” These aspects of the write command in the Command Spec describe a sequential write starting at the Starting LBA and continuing for the Number of Logical Blocks. As the device of Moon follows the NVMe protocol, it would be able to perform this sequential write) determining target map information indicating mapping information between a logical address and a physical address for the target data; (“The physical memory locations in memory to use for data transfers are specified using Physical Region Page (PRP) entries or Scatter Gather Lists (SGL).” (Base Spec section 2.1 Memory-Based Transport Model). The starting LBA and NLB indicate the logical addresses that are being used for the target data, and the PRP entries or SGL provide the corresponding physical address mapping information. Additionally note the controller of Moon also contains a logical to physical mapping table (“the storage controller 310 may include a logical storage area management table (LSA_MT) 312 and a spatial information-to-storage location mapping table (S2L_MT) 314, and may further include a logical-to-physical address mapping table (L2P_MT) 316.” Paragraph 66)) and mapping the identifier to the target map information, (Base Spec section 2.1 Memory-Based Transport Model “If more than two PRP entries are necessary to describe the data buffer, then a pointer to a PRP List that describes a list of PRP entries is provided”. In this case the PRP entries serving as the identifier would point/map to the mapping information (the PRP list). When the identifier is spatial information, it can also be mapped to the target map information as explained in claim 5 below) and wherein the target map information includes a plurality of map units each map unit indicating a mapping relationship between one logical address and one physical address (Base spec section 4.1.1 Physical Region Page Entry and List “A physical region page list (PRP List) is a set of PRP entries in a single page of contiguous memory”. The PRP list would serve as the target map information and the entries in the list would serve as the map units as explained above).
Regarding claim 11, the applicant is directed to the rejection to claim 4 set forth above, as they are rejected based on the same rationale.
Regarding claim 5, Moon/Gupta/Goss/Kachare teach the storage device according to claim 4, wherein the controller is further configured to read second target data from the target memory blocks based on the target map information mapped to the identifier, (“Referring to FIGS. 18 and 19, when selecting the target storage area and the physical storage area (operation S1200), the target storage area may be selected from among the plurality of logical storage areas based on the spatial information and a spatial information-to-storage location mapping table (operation S1210). The physical storage area corresponding to the target storage area may be selected based on a logical storage area management table and a logical-to-physical address mapping table” [Moon paragraph 178]. Where the logical-to-physical address mapping table contains the target map information and is mapped to the identifier through correspondence to the spatial information via the storage area management table, when the identifier is spatial information. Additionally the target memory area would be composed of blocks [“The storage device 300 may use a block accessible address space corresponding to an access size of the plurality of nonvolatile memories 320a to 320c to provide the block accessible interface to the host device 200, for allowing the access by units of a memory block with respect to data stored in the plurality of nonvolatile memories” (Moon paragraph 75)]) when receiving a read command which includes the identifier, (“According to example embodiments, in a method of reading data from a storage device, spatial information and a data read request are received from a host device. A target storage area and a physical storage area are selected based on the spatial information and the data read request. Target data to be read and corresponding to the data read request is stored in the target storage area corresponding to the spatial information among a plurality of logical storage areas. The physical storage area in a nonvolatile memory corresponds to the target storage area. A read command is transmitted to the nonvolatile memory such that the target data is retrieved from the physical storage area corresponding to the target storage area” [Moon paragraph 8]. Spatial information identifying which storage area the read command reads would be part of the command.) the size of the target data, (Command Spec Figure 48: Read – Command Dword 12 - Number of Logical Blocks (NLB): This field indicates the number of logical blocks to be read.) and the flag (Command Spec Figure 49: Read – Command Dword 13 - Access Frequency – 2h - Infrequent writes and infrequent reads to the LBA range indicated. – 6h – One time read.).
Regarding claim 12, the applicant is directed to the rejection to claim 5 set forth above, as they are rejected based on the same rationale.
Regarding claim 6, Moon/Gupta/Goss/Kachare teach the storage device (storage device 300) according to claim 5, wherein the controller reads the target data by: (“The storage controller 310 may control an operation of the storage device 300, e.g., a data write operation and/or a data read operation” [Moon paragraph 59]) caching the plurality of map units included in the target map information in a map cache, (“To perform operations according to example embodiments, the storage controller 310 may include a logical storage area management table (LSA_MT) 312 and a spatial information-to-storage location mapping table (S2L_MT) 314, and may further include a logical-to-physical address mapping table (L2P_MT) 316” [Moon paragraph 66]. “The logical-to-physical address mapping table 316 may represent or include a relationship between a logical address, which is received from the host device 200 and corresponds to the logical storage area, and a physical address, which corresponds to a physical storage area in which data is actually stored in the plurality of nonvolatile memories 320a to 320c” [Moon paragraph 70]. Mapping table 316 can serve as the target map information (see the rejection to claim 5 above) and is a cache, so any units included in the target map information are also being cached. See also the rejection to claim 1 above) and reading, based on a map unit corresponding to a target logical address among the cached map units, (“Referring to FIG. 3, a storage controller 400 may include a … flash translation layer (FTL) 430” [Moon paragraph 78]. “The flash translation layer 430 may perform various functions, such as, for example, an address mapping operation, ... The address mapping operation may be an operation of converting a logical address received from the host device into a physical address used to actually store data in a nonvolatile memory … The flash translation layer 430 may manage a logical storage area management table 432, a spatial information-to-storage location mapping table 434 and a logical-to-physical address mapping table 436 that are used to perform the method of writing data and/or the method of reading data according to example embodiments. The logical storage area management table 432, the spatial information-to-storage location mapping table 434 and the logical-to-physical address mapping table 436 may be substantially the same as the logical storage area management table 312, the spatial information-to-storage location mapping table 314 and the logical-to-physical address mapping table 316 in FIG. 2” [Moon paragraphs 81-82]. Wherein the received logical address (see above) would be a target logical address which corresponds to a map unit entry in the flash translation layer, for example in the logical-to-physical address mapping table 436 (which would be caching map unit entries) and this correspondence would be used in the process of reading stored data.) sub-data from the target memory blocks, (“each of the plurality of memory blocks BLK1 to BLKz may be divided into a plurality of pages” [Moon paragraph 89]. “The page buffer circuit 530 may store data DAT to be programmed into the memory cell array 510 or may read data DAT sensed from the memory cell array 510” [Moon paragraph 102].) the sub-data corresponding to the target logical address among the target data (A physical address from the logical to physical address mapping table may correspond to a page, resulting in a sub-data page read. [Moon paragraph 132 “a physical address (e.g., a physical page number (PPN), etc.)”]).
Regarding claim 13, the applicant is directed to the rejection to claim 6 set forth above, as they are rejected based on the same rationale.
Regarding claim 7, Moon/Gupta/Goss/Kachare teaches the storage device according to claim 6, wherein the controller reads the target data further by evicting the map unit corresponding to the target logical address from the map cache when the reading of the sub-data is completed (“The host may specify, e.g., with a write command, the expected number of reads for the data being written; once the limit has been reached, the persistent storage device may immediately invalidate the data” [Kachare paragraph 5]. “A read command handler 315 may read the physical address from the logical to physical address mapping table and update the read counter of the logical blocks. The auto-delete tracker 320 may keep track of the read counter for each row of the logical to physical address mapping table. Once the read counter matches the value of the expected number of reads, the auto-delete tracker 320 logs the logical block number (in a log that the host may query (e.g., using the NVMe Get Log Page command), so that the host may determine which logical blocks have been automatically deleted) and invalidates the entry in the logical to physical address mapping table” [Kachare paragraph 56]. Furthermore, Kachare Fig. 2C shows an example of data expected to be read once, which would result in the invalidation of the data after a read to that data, alongside the corresponding data in the mapping table being invalidated. An indication of one expected read could be representative of cold data, see Kachare paragraph 59 (as the instant application explains in paragraph 145, cold data is unlikely to be read again). As explained in the rejection to claim 6 above, reading the sub-data is taught by Moon (in combination with Gupta/Goss/Kachare), so in the combination of Moon/Gupta/Goss/Kachare it would have been obvious to combine the eviction after reading of Kachare with the reading of sub-data of Moon to achieve the claimed limitation of evicting after reading of sub-data).
Regarding claim 14, the applicant is directed to the rejection to claim 7 set forth above, as they are rejected based on the same rationale.
Claims 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Moon/Gupta/Goss/Kachare, further in view of Wikipedia (Wikipedia article entitled “inode” 1 page, revised March, 26 2023. Retrieved from Internet: <https://en.wikipedia.org/w/index.php?title=Inode&oldid=1146732961>).
Regarding claim 3, Moon/Gupta/Goss/Kachare teaches the storage device according to claim 1.
Moon/Gupta/Goss/Kachare does not appear to explicitly disclose wherein the identifier is an inode number corresponding to the target data.
However, Wikipedia teaches wherein the identifier is an inode number corresponding to the target data (“Each file is associated with an inode, which is identified by an integer, often referred to as an i-number or inode number.” [Wikipedia Details section, first paragraph]).
Moon/Gupta/Goss/Kachare and Wikipedia are analogous art because they are both in the field of data storage.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Moon/Gupta/Goss/Kachare and Wikipedia before him or her, to modify the device of Moon/Gupta/Goss/Kachare to include the inode numbers of Wikipedia as the identifier because it will improve the compatibility or interoperability of the storage device.
The motivation for doing so would be “The inode (index node) is a data structure in a Unix-style file system that describes a file-system object” (Wikipedia paragraph 1). Implementing inodes into the device of Moon/Gupta/Goss/Kachare would improve compatibility with host devices using Unix. Specifically, it would enable Moon/Gupta/Goss/Kachare’s system to have compatibility with additional file systems and applications.
Therefore, it would have been obvious to combine Moon/Gupta/Goss/Kachare and Wikipedia to obtain the invention as specified in the instant claim.
Regarding claim 10, the applicant is directed to the rejection to claim 3 set forth above, as they are rejected based on the same rationale.
Response to Remarks
Examiner thanks the applicant for their remarks of December 15, 2025. The remarks have been accepted and fully considered.
In light of the amendments to the claims, the 112(a) and 112(b) rejections to claims 2 and 9 are withdrawn and moot as the claims have been cancelled.
On pages 12-13 of their remarks, the applicant argues that “there appear to be no teachings in Moon of cold data read from a map cache”. The argument is moot in light of the updated 103 rejection to claim 1 above, as well as the 112(b) rejection to claim 1 above. The examiner additionally notes that cold data read from a map cache is invalid new matter. See the 112(a) rejection to claim 1 above.
Also on page 13 of their remarks, the applicant argues “the only teaching of freeing memory space in Goss is that which occurs during garbage collection”, as opposed to the claimed limitation of freeing space when a read occurs. This argument is moot in light of the updated rejection to claim 1 above.
On pages 13-14 of their remarks, the applicant argues “a combination of Moon and Goss would not disclose or even suggest: [all the new claim limitations added in the amendment to claim 1]”. While the applicant did attempt to distinguish some of the claimed subject matter from the cited references in the arguments cited (and addressed by the examiner) above, the applicant did not attempt to do so for all the newly introduced claim limitations recited on pages 13-14 (for example, no argument is made regarding the claim limitations involving the DWORDs). Therefore applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
On page 14 of their remarks, the applicant argues independent claims 8 and 15 should be allowable based on the alleged allowability of claim 1. This argument is not persuasive in light of the updated rejections to claims 1, 8, and 15 above.
Also on page 14 of the remarks, the applicant argues “the rejection of claims 1-2, 4-6, 8-9, 11-13, and 15 under 35 U.S.C. § 103 … should be withdrawn, and these claims should be passed to allowance”. However, the applicant has cancelled claims 2 and 9, and no argument is supplied for why dependent claims 2, 4-6, 8-9, and 11-13 would be allowable. Regardless, the argument is moot in light of the updated 103 claim rejections above.
On pages 14-15, applicant argues for the allowance of claims 3, 7, 10, and 14 based on their dependence on the allegedly allowable independent claims 1 and 8, additionally alleging that Wikipedia and Kachare do not overcome the alleged deficiencies of Moon. This argument is moot in light of the updated 103 claim rejections above. The examiner additionally notes that the rejections to claims 3, 7, 10, and 14 were based on the combination of Moon/Goss and either Wikipedia or Kachare, and the applicant only argues for patentability against the merits of Moon rather than the combination of Moon and Goss. The examiner further disagrees that the alleged deficiencies in Moon are not overcome by Kachare, as some deficiencies of Moon are overcome by Kachare (see the 103 claim rejections above).
Pertinent Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
In Jung US 20210334218 A1 “Memory system, memory controller, and operation method of memory system”
“According to embodiments of the present disclosure, the memory system, before updating a mapping table which includes mapping information between logical addresses and physical addresses, may assign a portion of a map cache area for caching a plurality of map segments in the mapping table as a map update area for updating the mapping table, and may load a subset of the plurality of map segments to the map update area. Accordingly, it is possible to quickly update a mapping table and to optimize update performance for a mapping table within a limit that guarantees caching performance to a predetermined level or higher.” [abstract]
Kim and Byun US 20200233796 A1 “Storage device, computing system including storage device, and method of operating the same”
Relevant excerpt: “A memory controller may control a memory device for storing logical to physical (L2P) mapping information, the memory controller comprising: a map data storage configured to store a plurality of L2P address segments included in the L2P mapping information; and a map data manager configured to: provide at least one L2P address segment of the plurality of L2P address segments to the host in response to a map data request of the host; and remove a L2P address segment from the map data storage, wherein the L2P address segment is selected, among the plurality of L2P address segments, based on a least recently used (LRU) frequency and whether the L2P address segment is provided to the host.” [abstract]
Conclusion
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857
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/C.J.O./
Examiner, Art Unit 2138
/Kaushikkumar M Patel/Primary Examiner, Art Unit 2138