Prosecution Insights
Last updated: October 02, 2026
Application No. 18/451,206

PHOTOLITHOGRAPHY METHOD USING CASTELLATION SHAPED ASSIST FEATURES TO FORM A LINE-AND-SPACE PATTERN AND PHOTOMASK CONTAINING THE ASSIST FEATURES

Non-Final OA §102§103
Filed
Aug 17, 2023
Examiner
LIN, ARIC
Art Unit
1737
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Western Digital Technologies Inc.
OA Round
1 (Non-Final)
60%
Grant Probability
Moderate
1-2
OA Rounds
0m
Est. Remaining
72%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allowance Rate
315 granted / 527 resolved
-5.2% vs TC avg
Moderate +12% lift
Without
With
+12.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
36 currently pending
Career history
575
Total Applications
across all art units

Statute-Specific Performance

§101
18.7%
-21.3% vs TC avg
§103
45.1%
+5.1% vs TC avg
§102
11.9%
-28.1% vs TC avg
§112
21.0%
-19.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 527 resolved cases

Office Action

§102 §103
DETAILED ACTION This office action is in response to Application No. 18/451,206, filed on 17 August 2023. Claims 1-20 are pending, wherein claims 1-17 are withdrawn from consideration. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 1-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected inventions, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7 July 2026. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tang (“Measurement of non-monotonic Casimir forces between silicon Nanostructures”). Regarding claim 18, Tang discloses a semiconductor device comprising: a substrate; and a patterned material layer located over the substrate (p. 6, first paragraph after figure description; p. 16-17, ¶1), wherein the patterned material layer comprises: a line-and-space pattern structure having a uniform pitch and including a plurality of parallel active line structures that laterally extend along a first horizontal direction (p. 5, Fig. 2); and a peripheral castellation pattern structure, wherein the peripheral castellation pattern structure comprises a combination of an end straight line dummy pattern structure and a plurality of hammerhead pattern structures attached to a lengthwise sidewall of the end straight line dummy pattern structure (p. 3, Fig. 1; p. 5, Fig. 2). Regarding claim 20, Tang discloses that each of the hammerhead pattern structures comprises: a respective oval-shaped material portion that is laterally elongated along the first horizontal direction and comprising a respective laterally-convex sidewall; and a respective bridge material portion connecting the respective oval-shaped material portion to the end straight line dummy pattern structure and comprising a respective pair of laterally-concave sidewalls (p. 3, Fig. 1). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 18 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by Kaneko (US 2016/0005752) or, in the alternative, under 35 U.S.C. 103 as obvious over Kaneko in view of Ito (US 2008/0164614). Regarding claim 18, Kaneko discloses a semiconductor device, comprising: a substrate; and a patterned material layer located over the substrate, wherein the patterned material layer comprises: a line-and-space pattern structure having a uniform pitch and including a plurality of parallel active line structures that laterally extend along a first horizontal direction (Abstract; Fig. 21, MA); and a peripheral castellation pattern structure, wherein the peripheral castellation pattern structure comprises a combination of an end straight line dummy pattern structure and a plurality of hammerhead pattern structures attached to a lengthwise sidewall of the end straight line dummy pattern structure (Abstract; Fig. 21, DA dummy pattern is a series of hammerheads with connected ends). Even if Kaneko is found to be unclear regarding the hammerhead dummy patterns, such dummy patterns are known to be obvious variants of Kaneko’s pattern, as taught by Ito (¶130). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to modify Kaneko’s dummy patterns in the above manner, because doing so would have involved merely the routine substitution of an element for a known equivalent, or the use of a known technique to improve similar devices in the same way, to achieve the predictable results of using various known dummy patterns to improve printing of device features. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Kaneko discloses dummy patterns for improving printing of nearby features. Persons having ordinary skill in the art would recognize that many different types of dummy patterns are used, as taught by Ito. The teachings of Ito are directly applicable to Kaneko in the same way, so that Kaneko would be able to use different known types of dummy patterns for improving printing of device features. Regarding claim 19, Kaneko discloses that the parallel active line structures comprise bit lines of the semiconductor device (¶97). Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaneko in view of Ito, and Mukherjee (US 2005/0055658). Regarding claim 20, Kaneko does not appear to explicitly disclose that each of the hammerhead pattern structures comprises: a respective oval-shaped material portion that is laterally elongated along the first horizontal direction and comprising a respective laterally-convex sidewall; and a respective bridge material portion connecting the respective oval-shaped material portion to the end straight line dummy pattern structure and comprising a respective pair of laterally-concave sidewalls. However, these features are inherent or implied in Kaneko because the dummy pattern DP3 of Kaneko’s Fig. 21 would print in the recited manner, as would be recognized by persons having ordinary skill in the art. Specifically, lithography causes effects such as corner rounding, necking, etc. such that Kaneko’s (or Kaneko’s modified by Ito, as discussed above) T-intersections would round/bulge into ovals and the attached legs would thin, as evidenced by Mukherjee (Fig. 2) (and can also be clearly seen in Tang’s Fig. 1), resulting in the claimed shapes. It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application that the features of Kaneko and Ito would print in the claimed manner using lithography, as taught by Mukherjee, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of patterning a device using lithography. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Kaneko and Ito disclose T-shaped dummy patterns. Such patterns experience rounding and necking when lithographically printed, as shown by Mukherjee. The teachings of Mukherjee are directly applicable to Kaneko and Ito in the same way, such that Kaneko would pattern a device using lithography with similar inherent/implied effects. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIC LIN whose telephone number is (571)270-3090. The examiner can normally be reached M-F 07:30-17:00 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. 5 September 2026 /ARIC LIN/ Examiner, Art Unit 2851
Read full office action

Prosecution Timeline

Aug 17, 2023
Application Filed
Sep 10, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
60%
Grant Probability
72%
With Interview (+12.4%)
3y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 527 resolved cases by this examiner. Grant probability derived from career allowance rate.

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