DETAILED ACTION
This Action is responsive to the Amendments filed on 02/25/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1-2, 5-8, and 12-20 are amended. Claims 3-4 and 9-11 are cancelled. Claims 21-25 are newly presented. Claims 1-2, 5-8, and 12-25 are pending and have been examined.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
No antecedent basis for the claimed term “immediately adjacent” is provided in the Specification. While the Specification uses the term “adjacent” (e.g., ¶0020) when referencing memory rows, no antecedent basis is provided for the term “immediately adjacent” (see Claim 16, lines 15 and 16; Claim 21, lines 17 and 18)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 5-8, 12, 16-19, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Bezbaruah et al. (US 8499129 B1)(hereafter referred to as Bezbaruah) further in view of Hily et al. (US 20230176749 A1)(cited by examiner in previous action)(hereafter referred to as Hily) and Kim et al. (US 20190087100 A1)(cited by examiner in previous action)(hereafter referred to as Kim).
Regarding Claim 1,
Bezbaruah discloses the following limitations:
A system comprising:
…
a memory controller (Node 202, Fig. 2) configured to:
receive a first address (“read generator 228 receives a read request 232 … for N blocks of data 220 … beginning at block 1” [Col. 6, 20-30th lines] // “A block is … a basic unit of addressing data in a data storage device” [Col. 4, 15-20th lines] // Fig. 2) – As shown in Fig. 2, read generator 228 receives a read request 232 from a client which specifies a particular start block (e.g., block 1). As clarified in Col. 4, a block corresponds to the unit by which data is addressed in a data storage device. Accordingly, the specified starting block number of a received read request 232 corresponds to “a first address” which specifies which starting block is targeted by the read request--; and
determine that the first address is within a predefined range (“Upon receiving read request 232, read generator 228 checks the read policy associated with primary storage device 214 and mirror 216 … If the read policy allows for apportioning a read request … two read operations are generated” [Col. 6, 25-35th lines] // “a system administrator of node 202 associates a read policy with primary storage device 214 and mirror 216 by assigning the read policy to virtual disk 238 … The read policy is generally the method by which read generator 228 distributes read operations to primary storage device 214 and mirror 216” [Col. 5, 30-40th lines] // “a new read policy” [Col. 5, 65th line]) – As taught in Bezbaruah, a system administrator establishes a particular “read policy” for each virtual disk 238 which specifies how data stored in the virtual disk might be read (e.g., round robin or “a new read policy”; see Col. 5). After receiving a read request from the client, read generator 228 first checks the read policy associated with the targeted virtual disk to determine whether or not the policy allows for read requests to be apportioned to both a primary storage and a mirror storage (i.e., whether or not “the new read policy” has been assigned by the administrator; see Col. 6). Accordingly, in the context of Fig. 2, read generator 228 checking and confirming that the virtual disk 238 including the starting block targeted by the received read command has been assigned the new read policy corresponds to “determin[ing] that the first address is within a predefined range” (i.e., determining that starting block 1 specified by request 232 is associated with a virtual disk 238 assigned to the new read policy); and
perform, responsive to a single read request specifying the first address (Read Request 232, Fig. 2) and the first address being within the predefined range, a memory transaction (“If the read policy allows … two read operations are generated” [Col. 6, 25-35th lines]),
wherein the memory controller:
partitions requested data of the read request into a first portion and a second portion that does not overlap the first portion (“two read operations are generated, 234 and 236, each for a portion of data. The portion of data 220 for a first read operation 234 begins at block 1 and has a size equal to (N/2) blocks … Similarly, the portion of data 220 for a second read operation 236 begins at block ((N/2) + 1) and has a size equal to ((N/2) + 1) blocks” [Col. 6, 25-55th lines] // Fig. 2) – As shown in Fig. 2 and detailed in Col. 6, read generator 228 creates a first read operation 234 targeting blocks 1 through N/2 (i.e., “a first portion”) and a second read operation 236 targeting blocks N/2+1 through N (i.e., “a second portion that does not overlap” data targeted by read operation 234)--;
issues in parallel (“First and second read operations 234 and 236, respectively, are transmitted, preferably in parallel” [Col. 6, 55-60th lines])
a first read (Read Operation 234, Fig. 2) of the first portion on first data at a mapped second address (block 1, Fig. 2) in a first memory space (Primary Storage Device 214, Fig. 2) – As shown in Fig. 2, read generator 228 issues read operation 234 which targets start block 1 of primary storage device 214 (i.e., targeting “a mapped second address in a first memory space”) …, and
a second read (Read Operation 236, Fig. 2) of the second portion on mirrored first data at a mapped third address (block N/2 + 1, Fig. 2) in a second memory space (Mirror 216, Fig. 2) – As shown in Fig. 2, read generator 228 issues read operation 236 which targets start block N/2 + 1 of mirror storage device 216 (i.e., “a mapped third address in a second memory space”)-- …,
the mapped second address in the first memory space being a different address than the mapped third address in the second memory space (Fig. 2) – As discussed above and shown in Fig. 2, read operations 234 and 236 target different starting blocks in the primary and mirror storage devices--,
… and
combines the first and the second portion from the first and second reads to satisfy the single read request. (“Once received, primary storage device 214 and mirror 216 process the read operations, preferably in parallel, and return the respective portions of data 220. In one embodiment, buffer 230 stores data retrieved from primary storage device 214 and 216. [Col. 6, 55-60th lines] // Fig. 2) – As taught in Col. 6, once primary storage device 214 and mirror 216 have processed read operations 234 and 236, both respective portions of data are returned and are stored in the same buffer 230. Examiner considers the process of retrieving respective data from devices 214 and 216 and storing the retrieved data in a same memory structure (e.g., buffer 230) as “combin[ing]” the data from reads 234 and 236 under the Broadest Reasonable Interpretation (BRI) of the claimed language.
Bezbaruah is silent regarding separate first and second memory channels to primary and mirrored storage devices; and further does not explicitly disclose that data storage devices correspond to RAM devices for data storage. In particular, Bezbaruah does not explicitly disclose the following limitations:
a random access memory configured to store data
a first read … in a first memory space over a first memory channel
a second read … in a second memory space over a second memory channel
the second memory channel being different from the first memory channel
However, Hily discloses the following limitations:
a random access memory (DRAM Chips 110, Fig. 2) configured to store data,
a first read (¶0040) … in a first memory space (DRAM chip 110(1), Fig. 2) over a first memory channel (Channel 0, Fig. 2 // “the primary memory channel” [0040])
a second read (¶0040 … in a second memory space (DRAM chip 110(2), Fig. 2) over a second memory channel (Channel 1, Fig. 2 // “the secondary memory channel” [0040])
the second memory channel being different from the first memory channel (Fig. 2 // “The memory mirror agents … receive and process memory read requests … In response to receiving a read request 200R, the memory mirror agents 120(1)-120(N) are configured to communicate the memory read request 202R to a memory channel … mapped to the memory read address 202R as the primary memory channel, to be read as primary read data 204R … The memory mirror agent 120(1) – 120(N) can also be configured to retrieve the correct read data 204R from its mirrored memory channel … as the second memory channel” [0040]) – As shown in Hily Fig. 1, a Memory Mirror Agent 120(1) reads primary read data from a first DRAM Chip 110(1) and correct (mirrored) read data from a second DRAM Chip 110(2); similar to how Read Generator 228 reads primary data from a primary storage device 214 and mirrored data from a mirror storage device 216. Examiner accordingly considers Computer System 100 depicted in Hily Fig. 1 as analogous to Data Processing System 200 depicted in Bezbaruah Fig. 2. As shown in Hily Fig. 2 and taught in ¶0040, memory mirror agent communicates read requests for primary data using a “primary memory channel” (Channel 0, Fig. 2) and communicates read requests for mirrored data using a “secondary memory channel” (Channel 1, Fig. 2).
Bezbaruah and Hily are considered analogous to the claimed invention because they all relate to the same field of performing memory operations in storage environments which mirror subsets of data between primary and secondary storage devices. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bezbaruah with the teachings of Hily and realize a method of reading primary data over a first memory channel and reading mirrored data over a different second channel. Doing so improves resilience of a data storage system by enabling data recovery when a memory channel incurs a fault, as disclosed in Hily ¶0037: “the first and second memory channels CHANNEL0, CHANNEL1 are configured as memory channel pairs to carry primary and redundant write data 204W when the visibly memory address range of the write request 200W falls within a prescribed memory address range designated for mirroring … In this manner, if one of the memory channels CHANNEL1 or CHANNEL0 incurs a fault, the other non-faulted memory channel CHANNEL0 or CHANNEL1 will have a copy of the data” [0037]
Although Bezbaruah Col. 7, 1-10th lines explicitly discloses that “the block addresses of data 220 may differ on each of the devices”; Bezbaruah is silent regarding an “address mapping” type structure which is used by node 220 to read data from storage devices 214 and 216. In addition, although Hily ¶0030 generally discloses memory mapping for mirrored regions, Hily does not provide specific detail regarding different memory mappings for primary and mirrored data. Specifically, Bezbaruah and Hily do not explicitly disclose the following limitations:
a first read … using a first address mapping between the first address and the mapped second address
a second read … using a second address mapping between the first address and the mapped third address
the first address mapping and the second address mapping being distinct address mappings
However, Kim discloses the following limitations:
a first read (Fig. 3) … using a first address mapping (Map1, Fig. 1) between the first address (Addr1, Fig. 3) and the mapped second address (Addr2, Fig. 3)
a second read (Fig. 3) … using a second address mapping (Map2, Fig. 3) between the first address (Addr1, Fig. 3) and the mapped third address (Addr2, Fig. 3)
the first address mapping and the second address mapping being distinct address mappings (Fig. 3 // “The address assignment map 113 includes a first map 114 and a second map 115 for use in converting a logical address received from a host into a physical address. In the first map 114, the relationship between the physical addresses of the first non-volatile memory 120_1 and the logical addresses may be defined, for example, in the form of a table. Likewise, in the second map 115, the relationship between the physical addresses of the second non-volatile memory 120_2 and the logical addresses may be defined in the form of a table … The address assignment map 113 converts the first address Addr1 into the second address Addr2 using the first map 114 … Similarly, the address assignment map 113 converts the first address Addr1 into the third address Addr3 using the second map 115.” [0043-46] // “It is to be understood that the second non-volatile memory 120_2 mirrors and stores the data stored in the first non-volatile memory 120_1” [0067] // ¶0075) -- As shown in Kim Fig. 3 and described in ¶0067, memory controller 110 mirrors data to both a first memory device non-volatile memory 1 and to a second memory device non-volatile memory 2, similar to how Memory Mirror Agent 120(1) of Hily Fig. 2 mirrors data to both a first DRAM chip 110(1) to a second DRAM chip 110(2). Examiner accordingly considers memory controller 110 of Kim Fig. 3 as analogous to Mirror Memory Agent 120(1) of Hily Fig. 2. As shown in Fig. 3 and described in ¶¶0043-46, memory controller 110 converts a logical address (Addr1) received from a host command (i.e., “the first address”) into a physical address (Addr2) for non-volatile memory 1 (i.e., “the mapped second address”) using a first mapping table 114; and further converts Addr1 into a physical address (Addr3) for non-volatile memory 2 (i.e., “the mapped third address”) using a second (i.e., “distinct”) mapping table 115.
Bezbaruah, Hily, and Kim are all considered analogous to the claimed invention because they all relate to the same field of performing memory operations in storage environments which mirror subsets of data between primary and secondary storage devices. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bezbaruah and Hily with the teachings of Kim and realize a system which uses distinct first and second address mappings in order to perform a memory operation on first data and on mirrored first data. Using separate address mappings for first and second memory spaces improves system performance by reducing the probability of bank collisions during a read request when compared to typical logical address assignment policies across separate memory devices, as disclosed in Kim ¶0068: “Specifically, the second non-volatile memory 120_2 includes the same number of banks as the first non-volatile memory 120_1, and the same number of logical addresses assigned to the banks as the first non-volatile memory 120_1. However, the assignment policy for assigning logical addresses to the same banks is different. For example, when different assignment policies are used for different non-volatile memories, a given read request applied to both non-volatile memories may result in fewer bank collisions in one of the non-volatile memories.” [0068]
Regarding Claim 2,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 2. The combined teachings of Bezbaruah, Hily, and Kim disclose the following limitations:
The system of claim 1, wherein the first address is a system physical address and wherein the mapped second address and the mapped third address addresses are random access memory (Hily, DRAM Chips 110, Fig. 2) physical addresses (Kim, “the controller 110 converts the logical addresses received from the host into actual physical addresses for accessing the first memory cell 130 and the second memory cell 140.” [0041]) – As shown in Hily Fig. 2, write memory addresses are addresses in DRAM. Examiner accordingly considers the addresses in DRAM chips 110 as “random access memory” addresses. As clarified in Kim ¶0041, a memory controller converts a logical address received from a host (i.e., “the first address”) into physical addresses for memory cells 130 and 140. In this case, examiner considers a logical address as “a system physical address” and a physical address as “random access memory physical addresses”, respectively, under the Broadest Reasonable Interpretation (BRI) of the claimed language.
Regarding Claim 5,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 5. The combined teachings of Bezbaruah, Hily, and Kim disclose the following limitations:
The system of claim 1, wherein the first data at the mapped second address (Bezbaruah, Block 1, Fig. 2) is adjacent to first adjacent data (Bezbaruah, Block 2, Fig. 2) in the random access memory (Hily),
wherein the mirrored first data at the mapped third address (Bezbaruah, Block ((N/2) + 1), Fig. 2) is adjacent to second adjacent data (Bezbaruah, Blocks N/2 and ((N/2) + 2), Fig. 2) in the random access memory, wherein the first adjacent data and the second adjacent data are distinct (Bezbaruah, Fig. 2) – As shown in Bezbaruah Fig. 2, data located at the starting block number for read operation 234 sent to primary storage device 214 (i.e., data located at “the mapped second address”; e.g., Block 1) is adjacent (in the primary data storage device) to Block 2 (i.e., “first adjacent data”); whereas data located at the starting block number for read operation 236 sent to mirror storage device 216 (i.e., data located at “the mapped third address”) is adjacent (in the mirror data storage device) to Blocks N/2 and N/2 + 2 (i.e., “second adjacent data” which is “distinct” from Block 1). As previously discussed (see Claim 1 limitation mappings above) and as taught in Hily, both primary and mirrored data are stored in RAM.
Regarding Claim 6,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 6. The combined teachings of Hily and Kim disclose the following limitations:
The system of claim 1 (see Claim 1 limitation mappings above), wherein memory transactions within the predefined range are mirrored on the first memory channel and the second memory channels channel (Hily, Fig. 3, steps 306 + 308; “the write memory address 202W … is within a memory address range stored in any of its mirror address range registers” [0034] // ¶0040) – As previously discussed (see Claim 1 limitation mappings above) and as taught in Hily, read transactions to primary data are sent over the first memory channel, whereas read transactions to mirrored data are sent over the second memory channel-- , and wherein memory transactions outside the predefined range are not mirrored on the first memory channel and the second memory channels channel (Hily, “In this example, if the write address 202W of the write request 200W is not within a memory address range stored in any of its mirror address range registers 210(1), the memory mirror agent 120(1) does not write the write data 204W redundantly (i.e., “mirror” the write data 204W)” [0036]) – As clarified in Hily, non-mirrored transactions are not performed redundantly (i.e., are not performed using both memory channels).
Regarding Claim 7,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 7. The combined teachings of Bezbaruah, Hily, and Kim disclose the following limitations:
The system of claim 1, wherein the predefined range is programmed into the memory controller (Hily, “the memory mirror agent may include a set of address range registers that are configured to be programmed to store one or more memory address ranges for which write data to a write memory address in a stored memory address range is mirrored.” [0005])
Regarding Claim 8,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 8. The combined teachings of Bezbaruah, Hily, and Kim disclose the following limitations:
The system of claim 1, further comprising a processor executing a program (Hily, ¶0052), wherein the program determines (Hily, Fig. 3, step 304) a plurality of data elements, including the first data, to be stored at addresses in the predefined range (Hily, Fig. 3, steps 306 + 308; “the write memory address 202W … is within a memory address range stored in any of its mirror address range registers” [0034]), and the program comprises other data elements, not including the first data, having addresses to be stored outside the predefined range in the random access memory (Hily, “In this example, if the write address 202W of the write request 200W is not within a memory address range stored in any of its mirror address range registers 210(1), the memory mirror agent 120(1) does not write the write data 204W redundantly (i.e., “mirror” the write data 204W)” [0036] // Fig. 3 // ¶¶0034-38) – As shown in Hily Fig. 3 and described in ¶¶0034-38, each write request received during step 302 is compared to the memory address range during step 304, and requests which fall within the mirrored address range are redundantly written during step 308.
Regarding Claim 12,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 12. The combined teachings of Bezbaruah, Hily, and Kim disclose the following limitations:
The system of claim 1, wherein the memory transaction is a read transaction (Hily, “memory read requests” [0040]), and wherein the memory controller is further configured to (Hily, “The memory mirror agents 120(1)-120(N) … are also configured to receive and process memory read requests 200R to read data from a memory read address 202R.” [0040]) – As previously discussed (see Claim 1 limitation mappings above) detailed in Hily ¶0040, memory mirror agents process read requests--:
read at least a first portion of the first data (Hily, “primary read data 204R” [0040]) over the first memory channel (Hily, “communicate the memory read request 202R to a memory channel … mapped to the read address 202R as the primary memory channel, to be read as primary read data 204R from an associated memory chip 110(1)-110(N) coupled to the primary memory channel CHANNEL0, CHANNEL1” [0040]);
detect an uncorrectable error in at least the first portion of the first data (Hily, “determining that the primary read data 204R contains an error … that is not recoverable by an error correction code (ECC) scheme” [0040]); and
read reads at least the first portion of the first data in the mirrored first data (Hily, “the correct read data 204R” [0040]) over the second memory channel (Hily, “The memory mirror agent 120(1)-120(N) can also be configured to retrieve the correct read data 204 from its mirrored memory channel CHANNEL0, CHANNEL1 as the secondary memory channel.” [0040])
Regarding Claim 16,
Bezbaruah discloses the following limitations:
A method, comprising:
receiving, via a memory controller (Node 202, Fig. 2), a first address (“read generator 228 receives a read request 232 … for N blocks of data 220 … beginning at block 1” [Col. 6, 20-30th lines] // “A block is … a basic unit of addressing data in a data storage device” [Col. 4, 15-20th lines] // Fig. 2) – As shown in Fig. 2, read generator 228 receives a read request 232 from a client which specifies a particular start block (e.g., block 1). As clarified in Col. 4, a block corresponds to the unit by which data is addressed in a data storage device. Accordingly, the specified starting block number of a received read request 232 corresponds to “a first address” which specifies which starting block is targeted by the read request--;
determining, using the memory controller, if the first address is within a predefined range (“Upon receiving read request 232, read generator 228 checks the read policy associated with primary storage device 214 and mirror 216 … If the read policy allows for apportioning a read request … two read operations are generated” [Col. 6, 25-35th lines] // “a system administrator of node 202 associates a read policy with primary storage device 214 and mirror 216 by assigning the read policy to virtual disk 238 … The read policy is generally the method by which read generator 228 distributes read operations to primary storage device 214 and mirror 216” [Col. 5, 30-40th lines] // “a new read policy” [Col. 5, 65th line]) – As taught in Bezbaruah, a system administrator establishes a particular “read policy” for each virtual disk 238 which specifies how data stored in the virtual disk might be read (e.g., round robin or “a new read policy”; see Col. 5). After receiving a read request from the client, read generator 228 first checks the read policy associated with the targeted virtual disk to determine whether or not the policy allows for read requests to be apportioned to both a primary storage and a mirror storage (i.e., whether or not “the new read policy” has been assigned by the administrator; see Col. 6). Accordingly, in the context of Fig. 2, read generator 228 checking and confirming that the virtual disk 238 including the starting block targeted by the received read command has been assigned the new read policy corresponds to “determining if the first address is within a predefined range” (i.e., determining that starting block 1 specified by request 232 is associated with a virtual disk 238 assigned to the new read policy); and
when the first address is within the predefined range, performing, using the memory controller, a memory transaction (“If the read policy allows … two read operations are generated” [Col. 6, 25-35th lines]):
on first data at a mapped second address (block 1, Fig. 2) in a first memory space (Primary Storage Device 214, Fig. 2) – As shown in Fig. 2, read generator 228 issues read operation 234 which targets start block 1 of primary storage device 214 (i.e., targeting “a mapped second address in a first memory space”)
…, and
on mirrored first data at a mapped third address (block N/2 + 1, Fig. 2) in a second memory space (Mirror 216, Fig. 2) – As shown in Fig. 2, read generator 228 issues read operation 236 which targets start block N/2 + 1 of mirror storage device 216 (i.e., “a mapped third address in a second memory space”)--
…, the mapped second address in the first memory space being a different address than the mapped third address in the second memory space (Fig. 2), …,
Bezbaruah is silent regarding separate first and second memory channels to primary and mirrored storage devices; and further does not explicitly disclose that data storage devices correspond to RAM devices for data storage. In particular, Bezbaruah does not explicitly disclose the following limitations:
a random access memory …
a memory transaction … in a first memory space … over a first memory channel
a memory transaction … in a second memory space … over a second memory channel
the second memory channel being different from the first memory channel
However, Hily discloses the following limitations:
a random access memory (DRAM Chips 110, Fig. 2) …
a memory transaction (¶0040) … in a first memory space (DRAM chip 110(1), Fig. 2) … over a first memory channel (Channel 0, Fig. 2 // “the primary memory channel” [0040])
a memory transaction (¶0040) … in a second memory space (DRAM chip 119(2), Fig. 2) … over a second memory channel (Channel 1, Fig. 2 // “the secondary memory channel” [0040])
the second memory channel being different from the first memory channel (Fig. 2 // “The memory mirror agents … receive and process memory read requests … In response to receiving a read request 200R, the memory mirror agents 120(1)-120(N) are configured to communicate the memory read request 202R to a memory channel … mapped to the memory read address 202R as the primary memory channel, to be read as primary read data 204R … The memory mirror agent 120(1) – 120(N) can also be configured to retrieve the correct read data 204R from its mirrored memory channel … as the second memory channel” [0040]) – As shown in Hily Fig. 1, a Memory Mirror Agent 120(1) reads primary read data from a first DRAM Chip 110(1) and correct (mirrored) read data from a second DRAM Chip 110(2); similar to how Read Generator 228 reads primary data from a primary storage device 214 and mirrored data from a mirror storage device 216. Examiner accordingly considers Computer System 100 depicted in Hily Fig. 1 as analogous to Data Processing System 200 depicted in Bezbaruah Fig. 2. As shown in Hily Fig. 2 and taught in ¶0040, memory mirror agent communicates read requests for primary data using a “primary memory channel” (Channel 0, Fig. 2) and communicates read requests for mirrored data using a “secondary memory channel” (Channel 1, Fig. 2).
Bezbaruah and Hily are considered analogous to the claimed invention because they all relate to the same field of performing memory operations in storage environments which mirror subsets of data between primary and secondary storage devices. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bezbaruah with the teachings of Hily and realize a method of reading primary data over a first memory channel and reading mirrored data over a different second channel. Doing so improves resilience of a data storage system by enabling data recovery when a memory channel incurs a fault, as disclosed in Hily ¶0037: “the first and second memory channels CHANNEL0, CHANNEL1 are configured as memory channel pairs to carry primary and redundant write data 204W when the visibly memory address range of the write request 200W falls within a prescribed memory address range designated for mirroring … In this manner, if one of the memory channels CHANNEL1 or CHANNEL0 incurs a fault, the other non-faulted memory channel CHANNEL0 or CHANNEL1 will have a copy of the data” [0037]
Although Bezbaruah Col. 7, 1-10th lines explicitly discloses that “the block addresses of data 220 may differ on each of the devices”; Bezbaruah is silent regarding an “address mapping” type structure which is used by node 220 to read data from storage devices 214 and 216. In addition, although Hily ¶0030 generally discloses memory mapping for mirrored regions, Hily does not provide specific detail regarding different memory mappings for primary and mirrored data. Specifically, Bezbaruah and Hily do not explicitly disclose the following limitations:
a memory transaction … using a first address mapping between the first address and the mapped second address
a memory transaction … using a second address mapping between the first address and the mapped third address
the first address mapping and the second address mapping being distinct address mappings
However, Kim discloses the following limitations:
a memory transaction (Fig. 3) … using a first address mapping (Map1, Fig. 1) between the first address (Addr1, Fig. 3) and the mapped second address (Addr2, Fig. 3)
a memory transaction (Fig. 3) … using a second address mapping (Map2, Fig. 3) between the first address (Addr1, Fig. 3) and the mapped third address (Addr2, Fig. 3)
the first address mapping and the second address mapping being distinct address mappings (Fig. 3 // “The address assignment map 113 includes a first map 114 and a second map 115 for use in converting a logical address received from a host into a physical address. In the first map 114, the relationship between the physical addresses of the first non-volatile memory 120_1 and the logical addresses may be defined, for example, in the form of a table. Likewise, in the second map 115, the relationship between the physical addresses of the second non-volatile memory 120_2 and the logical addresses may be defined in the form of a table … The address assignment map 113 converts the first address Addr1 into the second address Addr2 using the first map 114 … Similarly, the address assignment map 113 converts the first address Addr1 into the third address Addr3 using the second map 115.” [0043-46] // “It is to be understood that the second non-volatile memory 120_2 mirrors and stores the data stored in the first non-volatile memory 120_1” [0067] // ¶0075) -- As shown in Kim Fig. 3 and described in ¶0067, memory controller 110 mirrors data to both a first memory device non-volatile memory 1 and to a second memory device non-volatile memory 2, similar to how Memory Mirror Agent 120(1) of Hily Fig. 2 mirrors data to both a first DRAM chip 110(1) to a second DRAM chip 110(2). Examiner accordingly considers memory controller 110 of Kim Fig. 3 as analogous to Mirror Memory Agent 120(1) of Hily Fig. 2. As shown in Fig. 3 and described in ¶¶0043-46, memory controller 110 converts a logical address (Addr1) received from a host command (i.e., “the first address”) into a physical address (Addr2) for non-volatile memory 1 (i.e., “the mapped second address”) using a first mapping table 114; and further converts Addr1 into a physical address (Addr3) for non-volatile memory 2 (i.e., “the mapped third address”) using a second (i.e., “distinct”) mapping table 115.
Bezbaruah, Hily, and Kim are all considered analogous to the claimed invention because they all relate to the same field of performing memory operations in storage environments which mirror subsets of data between primary and secondary storage devices. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bezbaruah and Hily with the teachings of Kim and realize a system which uses distinct first and second address mappings in order to perform a memory operation on first data and on mirrored first data. Using separate address mappings for first and second memory spaces improves system performance by reducing the probability of bank collisions during a read request when compared to typical logical address assignment policies across separate memory devices, as disclosed in Kim ¶0068: “Specifically, the second non-volatile memory 120_2 includes the same number of banks as the first non-volatile memory 120_1, and the same number of logical addresses assigned to the banks as the first non-volatile memory 120_1. However, the assignment policy for assigning logical addresses to the same banks is different. For example, when different assignment policies are used for different non-volatile memories, a given read request applied to both non-volatile memories may result in fewer bank collisions in one of the non-volatile memories.” [0068]
The combined teachings of Bezbaruah, Hily, and Kim further disclose the following limitations:
wherein no row of the random access memory (Hily) that is immediately adjacent to the mapped second address is immediately adjacent to the mapped third address (Bezbaruah, Fig. 2) – As taught in Hily, data is stored in RAM. As shown in Bezbaruah Fig. 2, Block 2 is immediately adjacent to the mapped second address (i.e., Block 1 of primary storage device 214); whereas Blocks (N/2) and (N/2 + 2) are immediately adjacent to the mapped third address (i.e., Block N/2 + 1 in mirror storage device 216)., and
when the first address is outside the predefined range (Hily, Fig. 3, step 306), performing, using the memory controller, the memory transaction on first data at a fourth address (Hily, write memory address 202W, Fig. 4)(Hily, “The memory mirror agent(s) can be configured and reconfigured to identify a subset of memory space (e.g., memory address ranges) of the memory system to be mirrored.” [0023] // “if the write memory address 202W of the write request 200W is not within a memory address range stored in any of its mirror address range registers 210(1), the memory mirror agent 120(1) does not write the write data 204W redundantly” [0036]) – As described in Hily ¶0036, memory mirror agent 120(1) does not redundantly write data falling outside of the mirrored memory address range. One of ordinary skill in the art would accordingly understand that Fig. 3, step 306 would be performed regardless of whether the write memory address 202W falls within the mirrored memory address range or not.--
in one of the first memory space of the random access memory over the first memory channel or the second memory space of the random access memory over the second memory channel (Hily, “The memory mirror agent 120(1) communicates the write request 200W with the write data 204W at the write memory address 202W over a first memory channel (CHANNEL0 or CHANNEL1) to write the write data as primary write data to an associated memory chip 110(1), 110(2) (block 306 in FIG. 3)” [0033]) – As taught in Hily, non-mirrored memory transactions are not performed redundantly and are instead performed using the first memory channel.
Regarding Claim 17,
The same motivation to combine provided in Claim 16 is equally applicable to Claim 17. The combined teachings of Bezbaruah, Hily, and Kim disclose the following limitations:
The method of claim 16, wherein the first address is a system physical address and wherein the mapped second address and the mapped third address addresses are random access memory (Hily, DRAM Chips 110, Fig. 2) physical addresses (Kim, “the controller 110 converts the logical addresses received from the host into actual physical addresses for accessing the first memory cell 130 and the second memory cell 140.” [0041]) – As shown in Hily Fig. 2, write memory addresses are addresses in DRAM. Examiner accordingly considers the addresses in DRAM chips 110 as “random access memory” addresses. As clarified in Kim ¶0041, a memory controller converts a logical address received from a host (i.e., “the first address”) into physical addresses for memory cells 130 and 140. In this case, examiner considers a logical address as “a system physical address” and a physical address as “random access memory physical addresses”, respectively, under the Broadest Reasonable Interpretation (BRI) of the claimed language.
Regarding Claim 18,
The same motivation to combine provided in Claim 16 is equally applicable to Claim 18. The combined teachings of Bezbaruah, Hily, and Kim disclose the following limitations:
The method of claim 16, wherein the memory transaction is a read transaction (Bezbaruah, Fig. 2), and further comprising
reading, using the memory controller, a first portion of the first data (Bezbaruah, Fig. 2) over the first memory channel (Hily) and a second portion of the first data in the mirrored first data (Bezbaruah, Fig. 2) over the second memory channel (Hily) – As previously discussed (see Claim 16 limitation mappings above), primary data is read from a primary storage device using the first memory channel, and mirrored data is read from a mirrored storage device using the second memory channel.
in parallel wherein the first portion and the second portion are distinct portions of the first data. (Bezbaruah, Fig. 2 // “two read operations are generated, 234 and 236, each for a portion of data. The portion of data 220 for a first read operation 234 begins at block 1 and has a size equal to (N/2) blocks … Similarly, the portion of data 220 for a second read operation 236 begins at block ((N/2) + 1) and has a size equal to ((N/2) + 1) blocks … First and second read operations 234 and 236, respectively, are transmitted, preferably in parallel, to primary storage device 214 and mirror 216, respectively” [Col. 6, 25-60th lines]) – As taught in Bezbaruah and shown in Fig. 2, read operations 234 and 236 target different portions of data 220 (i.e., are “distinct portions of the first data”) and are transmit in parallel to respective storage devices.
Regarding Claim 19,
The same motivation to combine provided in Claim 16 is equally applicable to Claim 19. The combined teachings of Bezbaruah, Hily, and Kim disclose the following limitations:
The method of claim 16, wherein the memory transaction is a read transaction (Hily, “memory read requests” [0040]), and further comprising:
reading, using the memory controller, at least a first portion of the first data (Hily, “primary read data 204R” [0040]) over the first memory channel (Hily, “communicate the memory read request 202R to a memory channel … mapped to the read address 202R as the primary memory channel, to be read as primary read data 204R from an associated memory chip 110(1)-110(N) coupled to the primary memory channel CHANNEL0, CHANNEL1” [0040]);
detecting, using the memory controller, an uncorrectable error in at least the first portion of the first data (Hily, “determining that the primary read data 204R contains an error … that is not recoverable by an error correction code (ECC) scheme” [0040]); and
reading, using the memory controller, at least the first portion of the first data in the mirrored first data (Hily, “the correct read data 204R” [0040]) over the second memory channel (Hily, “The memory mirror agent 120(1)-120(N) can also be configured to retrieve the correct read data 204 from its mirrored memory channel CHANNEL0, CHANNEL1 as the secondary memory channel.” [0040])
Regarding Claim 21,
Bezbaruah discloses the following limitations:
A method, comprising:
receiving, via a memory controller (Node 202, Fig. 2), a first address (“read generator 228 receives a read request 232 … for N blocks of data 220 … beginning at block 1” [Col. 6, 20-30th lines] // “A block is … a basic unit of addressing data in a data storage device” [Col. 4, 15-20th lines] // Fig. 2) – As shown in Fig. 2, read generator 228 receives a read request 232 from a client which specifies a particular start block (e.g., block 1). As clarified in Col. 4, a block corresponds to the unit by which data is addressed in a data storage device. Accordingly, the specified starting block number of a received read request 232 corresponds to “a first address” which specifies which starting block is targeted by the read request--;
associated with a single read request (Read request 232, Fig. 2);
determining, using the memory controller, that the first address is within a predefined range (“Upon receiving read request 232, read generator 228 checks the read policy associated with primary storage device 214 and mirror 216 … If the read policy allows for apportioning a read request … two read operations are generated” [Col. 6, 25-35th lines] // “a system administrator of node 202 associates a read policy with primary storage device 214 and mirror 216 by assigning the read policy to virtual disk 238 … The read policy is generally the method by which read generator 228 distributes read operations to primary storage device 214 and mirror 216” [Col. 5, 30-40th lines] // “a new read policy” [Col. 5, 65th line]) – As taught in Bezbaruah, a system administrator establishes a particular “read policy” for each virtual disk 238 which specifies how data stored in the virtual disk might be read (e.g., round robin or “a new read policy”; see Col. 5). After receiving a read request from the client, read generator 228 first checks the read policy associated with the targeted virtual disk to determine whether or not the policy allows for read requests to be apportioned to both a primary storage and a mirror storage (i.e., whether or not “the new read policy” has been assigned by the administrator; see Col. 6). Accordingly, in the context of Fig. 2, read generator 228 checking and confirming that the virtual disk 238 including the starting block targeted by the received read command has been assigned the new read policy corresponds to “determining if the first address is within a predefined range” (i.e., determining that starting block 1 specified by request 232 is associated with a virtual disk 238 assigned to the new read policy);
responsive to the single read request and the first address being within the predefined range (DRAM Chips 110, Fig. 2) ,
partitioning requested data into a first portion and a second portion that does not overlap the first portion (“two read operations are generated, 234 and 236, each for a portion of data. The portion of data 220 for a first read operation 234 begins at block 1 and has a size equal to (N/2) blocks … Similarly, the portion of data 220 for a second read operation 236 begins at block ((N/2) + 1) and has a size equal to ((N/2) + 1) blocks” [Col. 6, 25-55th lines] // Fig. 2) – As shown in Fig. 2 and detailed in Col. 6, read generator 228 creates a first read operation 234 targeting blocks 1 through N/2 (i.e., “a first portion”) and a second read operation 236 targeting blocks N/2+1 through N (i.e., “a second portion that does not overlap” data targeted by read operation 234)--;
issuing in parallel (“First and second read operations 234 and 236, respectively, are transmitted, preferably in parallel” [Col. 6, 55-60th lines])
a first read (Read Operation 234, Fig. 2) of the first portion on first data at a mapped second address (block 1, Fig. 2) in a first memory space (Primary Storage Device 214, Fig. 2) – As shown in Fig. 2, read generator 228 issues read operation 234 which targets start block 1 of primary storage device 214 (i.e., targeting “a mapped second address in a first memory space”) …, and
a second read (Read Operation 236, Fig. 2) of the second portion on mirrored first data at a mapped third address (block N/2 + 1, Fig. 2) in a second memory space (Mirror 216, Fig. 2) – As shown in Fig. 2, read generator 228 issues read operation 236 which targets start block N/2 + 1 of mirror storage device 216 (i.e., “a mapped third address in a second memory space”)-- …,
the mapped second address in the first memory space being a different address than the mapped third address in the second memory space (Fig. 2) – As discussed above and shown in Fig. 2, read operations 234 and 236 target different starting blocks in the primary and mirror storage devices--,
… and
combining the first and the second portion from the first and second reads to satisfy the single read request. (“Once received, primary storage device 214 and mirror 216 process the read operations, preferably in parallel, and return the respective portions of data 220. In one embodiment, buffer 230 stores data retrieved from primary storage device 214 and 216. [Col. 6, 55-60th lines] // Fig. 2) – As taught in Col. 6, once primary storage device 214 and mirror 216 have processed read operations 234 and 236, both respective portions of data are returned and are stored in the same buffer 230. Examiner considers the process of retrieving respective data from devices 214 and 216 and storing the retrieved data in a same memory structure (e.g., buffer 230) as “combin[ing]” the data from reads 234 and 236 under the Broadest Reasonable Interpretation (BRI) of the claimed language.
Bezbaruah is silent regarding separate first and second memory channels to primary and mirrored storage devices; and further does not explicitly disclose that data storage devices correspond to RAM devices for data storage. In particular, Bezbaruah does not explicitly disclose the following limitations:
a random access memory …
a first read … in a first memory space … over a first memory channel
a second read … in a second memory space … over a second memory channel
the second memory channel being different from the first memory channel
However, Hily discloses the following limitations:
a random access memory (DRAM Chips 110, Fig. 2)
a first read (¶0040) … in a first memory space (DRAM chip 110(1), Fig. 2) … over a first memory channel (Channel 0, Fig. 2 // “the primary memory channel” [0040])
a second read (¶0040 … in a second memory space (DRAM chip 110(2), Fig. 2) … over a second memory channel (Channel 1, Fig. 2 // “the secondary memory channel” [0040])
the second memory channel being different from the first memory channel (Fig. 2 // “The memory mirror agents … receive and process memory read requests … In response to receiving a read request 200R, the memory mirror agents 120(1)-120(N) are configured to communicate the memory read request 202R to a memory channel … mapped to the memory read address 202R as the primary memory channel, to be read as primary read data 204R … The memory mirror agent 120(1) – 120(N) can also be configured to retrieve the correct read data 204R from its mirrored memory channel … as the second memory channel” [0040]) – As shown in Hily Fig. 1, a Memory Mirror Agent 120(1) reads primary read data from a first DRAM Chip 110(1) and correct (mirrored) read data from a second DRAM Chip 110(2); similar to how Read Generator 228 reads primary data from a primary storage device 214 and mirrored data from a mirror storage device 216. Examiner accordingly considers Computer System 100 depicted in Hily Fig. 1 as analogous to Data Processing System 200 depicted in Bezbaruah Fig. 2. As shown in Hily Fig. 2 and taught in ¶0040, memory mirror agent communicates read requests for primary data using a “primary memory channel” (Channel 0, Fig. 2) and communicates read requests for mirrored data using a “secondary memory channel” (Channel 1, Fig. 2).
Bezbaruah and Hily are considered analogous to the claimed invention because they all relate to the same field of performing memory operations in storage environments which mirror subsets of data between primary and secondary storage devices. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bezbaruah with the teachings of Hily and realize a method of reading primary data over a first memory channel and reading mirrored data over a different second channel. Doing so improves resilience of a data storage system by enabling data recovery when a memory channel incurs a fault, as disclosed in Hily ¶0037: “the first and second memory channels CHANNEL0, CHANNEL1 are configured as memory channel pairs to carry primary and redundant write data 204W when the visibly memory address range of the write request 200W falls within a prescribed memory address range designated for mirroring … In this manner, if one of the memory channels CHANNEL1 or CHANNEL0 incurs a fault, the other non-faulted memory channel CHANNEL0 or CHANNEL1 will have a copy of the data” [0037]
Although Bezbaruah Col. 7, 1-10th lines explicitly discloses that “the block addresses of data 220 may differ on each of the devices”; Bezbaruah is silent regarding an “address mapping” type structure which is used by node 220 to read data from storage devices 214 and 216. In addition, although Hily ¶0030 generally discloses memory mapping for mirrored regions, Hily does not provide specific detail regarding different memory mappings for primary and mirrored data. Specifically, Bezbaruah and Hily do not explicitly disclose the following limitations:
a first read … using a first address mapping between the first address and the mapped second address
a second read … using a second address mapping between the first address and the mapped third address
the first address mapping and the second address mapping being distinct address mappings
However, Kim discloses the following limitations:
a first read (Fig. 3) … using a first address mapping (Map1, Fig. 1) between the first address (Addr1, Fig. 3) and the mapped second address (Addr2, Fig. 3)
a second read (Fig. 3) … using a second address mapping (Map2, Fig. 3) between the first address (Addr1, Fig. 3) and the mapped third address (Addr2, Fig. 3)
the first address mapping and the second address mapping being distinct address mappings (Fig. 3 // “The address assignment map 113 includes a first map 114 and a second map 115 for use in converting a logical address received from a host into a physical address. In the first map 114, the relationship between the physical addresses of the first non-volatile memory 120_1 and the logical addresses may be defined, for example, in the form of a table. Likewise, in the second map 115, the relationship between the physical addresses of the second non-volatile memory 120_2 and the logical addresses may be defined in the form of a table … The address assignment map 113 converts the first address Addr1 into the second address Addr2 using the first map 114 … Similarly, the address assignment map 113 converts the first address Addr1 into the third address Addr3 using the second map 115.” [0043-46] // “It is to be understood that the second non-volatile memory 120_2 mirrors and stores the data stored in the first non-volatile memory 120_1” [0067] // ¶0075) -- As shown in Kim Fig. 3 and described in ¶0067, memory controller 110 mirrors data to both a first memory device non-volatile memory 1 and to a second memory device non-volatile memory 2, similar to how Memory Mirror Agent 120(1) of Hily Fig. 2 mirrors data to both a first DRAM chip 110(1) to a second DRAM chip 110(2). Examiner accordingly considers memory controller 110 of Kim Fig. 3 as analogous to Mirror Memory Agent 120(1) of Hily Fig. 2. As shown in Fig. 3 and described in ¶¶0043-46, memory controller 110 converts a logical address (Addr1) received from a host command (i.e., “the first address”) into a physical address (Addr2) for non-volatile memory 1 (i.e., “the mapped second address”) using a first mapping table 114; and further converts Addr1 into a physical address (Addr3) for non-volatile memory 2 (i.e., “the mapped third address”) using a second (i.e., “distinct”) mapping table 115.
Bezbaruah, Hily, and Kim are all considered analogous to the claimed invention because they all relate to the same field of performing memory operations in storage environments which mirror subsets of data between primary and secondary storage devices. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bezbaruah and Hily with the teachings of Kim and realize a system which uses distinct first and second address mappings in order to perform a memory operation on first data and on mirrored first data. Using separate address mappings for first and second memory spaces improves system performance by reducing the probability of bank collisions during a read request when compared to typical logical address assignment policies across separate memory devices, as disclosed in Kim ¶0068: “Specifically, the second non-volatile memory 120_2 includes the same number of banks as the first non-volatile memory 120_1, and the same number of logical addresses assigned to the banks as the first non-volatile memory 120_1. However, the assignment policy for assigning logical addresses to the same banks is different. For example, when different assignment policies are used for different non-volatile memories, a given read request applied to both non-volatile memories may result in fewer bank collisions in one of the non-volatile memories.” [0068]
The combined teachings of Bezbaruah, Hily, and Kim additionally disclose the following limitations:
wherein no row of the random access memory (Hily) that is immediately adjacent to the mapped second address is immediately adjacent to the mapped third address (Bezbaruah, Fig. 2) – As taught in Hily, data is stored in RAM. As shown in Bezbaruah Fig. 2, Block 2 is immediately adjacent to the mapped second address (i.e., Block 1 of primary storage device 214); whereas Blocks (N/2) and (N/2 + 2) are immediately adjacent to the mapped third address (i.e., Block N/2 + 1 in mirror storage device 216).
Regarding Claim 22,
The same motivation to combine provided in Claim 21 is equally applicable to Claim 22. The combined teachings of Bezbaruah, Hily, and Kim disclose the following limitations:
The method of claim 21, wherein the predefined range is programmed into the memory controller (Hily, “the memory mirror agent may include a set of address range registers that are configured to be programmed to store one or more memory address ranges for which write data to a write memory address in a stored memory address range is mirrored.” [0005])
Regarding Claim 23,
The same motivation to combine provided in Claim 21 is equally applicable to Claim 23. The combined teachings of Bezbaruah, Hily, and Kim disclose the following limitations:
The method of claim 21, further comprising:
detecting, using the memory controller, an uncorrectable error in at least the first portion returned from the first read (Hily, “determining that the primary read data 204R contains an error … that is not recoverable by an error correction code (ECC) scheme” [0040]); and
reading, using the memory controller, at least the first portion in the mirrored first data (Hily, “the correct read data 204R” [0040]) over the second memory channel (Hily, “The memory mirror agent 120(1)-120(N) can also be configured to retrieve the correct read data 204 from its mirrored memory channel CHANNEL0, CHANNEL1 as the secondary memory channel.” [0040])
Claims 13-14, 20, and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Bezbaruah further in view of Hily, Kim, and Berke et al. (US 20130151767 A1)(cited by examiner in previous action)(hereafter referred to as Berke).
Regarding Claim 13,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 13. The combined teachings of Bezbaruah, Hily, and Kim disclose the following limitations:
The system of claim 1, wherein the memory transaction is a read transaction (Hily, “memory read requests” [0040]), and wherein the memory controller is further configured to:
read the first data (Hily, “primary read data 204R” [0040]) over the first memory channel (Hily, “communicate the memory read request 202R to a memory channel … mapped to the read address 202R as the primary memory channel, to be read as primary read data 204R from an associated memory chip 110(1)-110(N) coupled to the primary memory channel CHANNEL0, CHANNEL1” [0040]);
read the mirrored first data (Hily, “the correct read data 204R” [0040]) over the second memory channel (Hily, “The memory mirror agent 120(1)-120(N) can also be configured to retrieve the correct read data 204 from its mirrored memory channel CHANNEL0, CHANNEL1 as the secondary memory channel.” [0040])
The combined teachings of Bezbaruah, Hily, and Kim are silent regarding the following limitations:
compare the first data read over the first memory channel to the mirrored first data read over the second memory channel.
However, Berke discloses within the context of performing read operations targeting mirrored data that first data and mirrored first data are read from respective locations and are compared to determine any differences. Specifically, Berke discloses the following limitations:
compare (step 430, Fig. 6) the first data read over the first memory channel (Set 1 Data 304, Fig. 5) to the mirrored first data read over the second memory channel (Set 2 Data 306, Fig. 5)(“The method 400 then proceeds to decision block 430 where … the memory buffer 308 may compare the Set1 data to the Set2 data to determine whether any corresponding bits miscompare, and/or perform a variety of other mismatch operations known in the art” [0038]) – As shown in Figs. 5+6 and detailed in ¶0038, primary and mirrored data sets (e.g., Set 1 data and Set 2 data) are read and are compared by Data Compare Logic 310.
Bezbaruah, Hily, Kim, and Berke are all considered analogous to the claimed invention because they all relate to the same field of performing mirrored memory operations on data sets located in separate memory devices. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bezbaruah, Hily, and Kim with the teachings of Berke and realize a system whereby first data and mirrored first data are read and are compared. Comparing primary and mirrored data improves the reliability of data in a storage system by identifying any errors in mirrored data sets, as disclosed in Berke ¶0038: “The memory buffer may compare the Set1 data to the Set2 data to determine whether any corresponding bits miscompare” [0038].
Regarding Claim 14,
The same motivation to combine provided in Claim 13 is equally applicable to Claim 14. The combined teachings of Bezbaruah, Hily, Kim, and Berke disclose the following limitations:
The system of claim 13, wherein the memory controller generates an error flag (Berke, “the lock flag” [0038]) when the first data read over the first memory channel does not match the first data read over the second memory channel (Berke, block 432, Fig. 6 // “If at decision block 430 the memory buffer 308 determines that Set1 data does not match Set2 data, the method 400 proceeds to block 432 where the entry is locked. In an embodiment, the memory buffer sets the lock flag for the scoreboard entry that corresponds to the unmatched Set1 and Set2 data to ‘locked’” [0038])
Regarding Claim 20,
The same motivation to combine provided in Claim 16 is equally applicable to Claim 20. The combined teachings of Bezbaruah, Hily, and Kim disclose the following limitations:
The method of claim 16 (see Claim 16 limitation mappings above), wherein the memory transaction is a read transaction (Hily, “memory read requests” [0040]), and further comprising:
reading, using the memory controller, the first data (Hily, “primary read data 204R” [0040]) over the first memory channel (Hily, “communicate the memory read request 202R to a memory channel … mapped to the read address 202R as the primary memory channel, to be read as primary read data 204R from an associated memory chip 110(1)-110(N) coupled to the primary memory channel CHANNEL0, CHANNEL1” [0040]);
reading, using the memory controller, the mirrored first data (Hily, “the correct read data 204R” [0040]) over the second memory channel (Hily, “The memory mirror agent 120(1)-120(N) can also be configured to retrieve the correct read data 204 from its mirrored memory channel CHANNEL0, CHANNEL1 as the secondary memory channel.” [0040])
The combined teachings of Bezbaruah, Hily, and Kim are silent regarding the following limitations:
comparing, using the memory controller, the first data read over the first memory channel to the mirrored first data read over the second memory channel.
However, Berke discloses within the context of performing read operations targeting mirrored data that first data and mirrored first data are read from respective locations and are compared to determine any differences. Specifically, Berke discloses the following limitations:
comparing (step 430, Fig. 6), using the memory controller, the first data read over the first memory channel (Set 1 Data 304, Fig. 5) to the mirrored first data read over the second memory channel (Set 2 Data 306, Fig. 5)(“The method 400 then proceeds to decision block 430 where … the memory buffer 308 may compare the Set1 data to the Set2 data to determine whether any corresponding bits miscompare, and/or perform a variety of other mismatch operations known in the art” [0038]) – As shown in Figs. 5+6 and detailed in ¶0038, primary and mirrored data sets (e.g., Set 1 data and Set 2 data) are read and are compared by Data Compare Logic 310.
Bezbaruah, Hily, Kim, and Berke are all considered analogous to the claimed invention because they all relate to the same field of performing mirrored memory operations on data sets located in separate memory devices. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bezbaruah, Hily, and Kim with the teachings of Berke and realize a system whereby first data and mirrored first data are read and are compared. Comparing primary and mirrored data improves the reliability of data in a storage system by identifying any errors in mirrored data sets, as disclosed in Berke ¶0038: “The memory buffer may compare the Set1 data to the Set2 data to determine whether any corresponding bits miscompare” [0038].
Regarding Claim 24,
The same motivation to combine provided in Claim 21 is equally applicable to Claim 24. The combined teachings of Bezbaruah, Hily, and Kim disclose the following limitations:
The method of claim 21 (see Claim 21 limitation mappings above),
The combined teachings of Bezbaruah, Hily, and Kim are silent regarding the following limitations:
further comprising: comparing, using the memory controller, the first portion returned from the first read to a corresponding portion of the mirrored first data returned from the second read.
However, Berke discloses within the context of performing read operations targeting mirrored data that first data and mirrored first data are read from respective locations and are compared to determine any differences. Specifically, Berke discloses the following limitations:
comparing (step 430, Fig. 6), using the memory controller, the first portion returned from the first read (Set 1 Data 304, Fig. 5) to a corresponding portion of the mirrored first data returned from the second read (Set 2 Data 306, Fig. 5)(“The method 400 then proceeds to decision block 430 where … the memory buffer 308 may compare the Set1 data to the Set2 data to determine whether any corresponding bits miscompare, and/or perform a variety of other mismatch operations known in the art” [0038]) – As shown in Figs. 5+6 and detailed in ¶0038, primary and mirrored data sets (e.g., Set 1 data and Set 2 data) are read and are compared by Data Compare Logic 310.
Bezbaruah, Hily, Kim, and Berke are all considered analogous to the claimed invention because they all relate to the same field of performing mirrored memory operations on data sets located in separate memory devices. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bezbaruah, Hily, and Kim with the teachings of Berke and realize a system whereby first data and mirrored first data are read and are compared. Comparing primary and mirrored data improves the reliability of data in a storage system by identifying any errors in mirrored data sets, as disclosed in Berke ¶0038: “The memory buffer may compare the Set1 data to the Set2 data to determine whether any corresponding bits miscompare” [0038].
Regarding Claim 25,
The same motivation to combine provided in Claim 24 is equally applicable to Claim 25. The combined teachings of Bezbaruah, Hily, Kim, and Berke disclose the following limitations:
The method of claim 24, further comprising generating an error flag (Berke, “the lock flag” [0038]) when the first portion does not match the corresponding portion of the mirrored first data (Berke, block 432, Fig. 6 // “If at decision block 430 the memory buffer 308 determines that Set1 data does not match Set2 data, the method 400 proceeds to block 432 where the entry is locked. In an embodiment, the memory buffer sets the lock flag for the scoreboard entry that corresponds to the unmatched Set1 and Set2 data to ‘locked’” [0038])
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Bezbaruah further in view of Hily, Kim, and Lee et al. (US 20190066766 A1)(cited by examiner in previous action)(hereafter referred to as Lee).
Regarding Claim 15,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 15. The combined teachings of Bezbaruah, Hily, Kim, and Berke disclose the following limitations:
The system of claim 1 (see Claim 1 limitation mappings above),
The combined teachings of Bezbaruah, Hily, Kim are silent regarding the following limitations:
wherein the random access memory is a synchronous double data rate 5 (DDR5) dual inline memory module
However, Lee discloses within the context of performing memory transactions on memory devices comprising mirroring functionality (see ¶0028) that a “DDR5 SDRAM” device can be used.
Lee discloses the following limitations:
wherein the random access memory is a synchronous double data rate 5 (DDR5) dual inline memory module (“In accordance with one embodiment, the memory device 10 may be a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device” [0019] // ¶0020)
Bezbaruah, Hily, Kim, and Lee are all considered to be analogous to the claimed invention because they all relate to the same field of performing memory transactions on DIMM devices with mirroring functionality. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bezbaruah, Hily, and Kim with the teachings of Lee and realize a DDR5 dual inline memory module with mirroring functionality. Doing so would enable reduced power consumption, increased bandwidth, and increase storage capacity, as disclosed in Lee ¶0019: “Various features of DDR5 SDRAM allow for reduced power consumption, more bandwidth and more storage capacity compared to prior generations of DDR SDRAM.”
Response to Arguments
Applicant’s arguments with respect to claims 1-2, 5-8, and 12-25 have been considered but are moot in view of the newly-identified Bezbaruah reference because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
With respect to applicant’s argument located within the 2nd paragraph of the 3rd page of remarks (numbered as page 10), which recites:
The Examiner has relied on Kim's bank-shift assignment policy, which assigns logical addresses to different banks across non-volatile memories to reduce bank collisions. See Kim, paragraphs [0059]-[0076]. However, Kim does not teach or suggest ensuring that rows immediately adjacent to the primary data address are different from rows immediately adjacent to the mirrored data address in DRAM. Kim's concern is bank collisions in NVM to reduce latency, not row adjacency in DRAM for row hammer protection. Kim's shifted logical-to-bank assignment does not address or teach the concept of diversifying adjacent rows between primary and mirrored data locations to protect against row hammer attacks.
Examiner has fully considered the aforementioned argument but notes that the argument is moot in view of the newly-identified Bezbaruah reference. As detailed in the outstanding prior art rejections (see 35 U.S.C. 103 rejections above), the outstanding rejection no longer relies on Kim for teaching diversifying adjacent rows between primary and mirrored data locations; and instead relies on Kim only for teaching distinct address mappings between primary and mirrored data locations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Dahlen et al. (US 20040090827 A1) – Discloses a method of simultaneously reading distinct portions of a dataset over first and second memory channels (see Fig. 2, ¶0033)
Breakstone et al. (US 20120089854 A1) – Discloses a method of responding to a host read command by “de-parallelizing” portions of read data received from a memory subsystem (see Fig. 5)
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/J.S.M./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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