DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the Amendment filed on 7/28/2026. Claims 1-24 are pending in the case. Claims 1, 7, 13, and 19 are independent claims.
Response to Arguments
Applicant’s prior art arguments have been considered but are moot because the new grounds of rejection presented below do not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the arguments.
Claim Interpretation
The following is a quotation of 35 U.S.C. § 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. § 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. § 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. § 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. § 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. § 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. § 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. § 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. § 112(f) except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. § 112(f) because the claim limitations use a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are: “means for determining … a difference,” “means for selectively activating,” “means for simultaneously transmitting,” “means for power gating,” and “means for processing” in claim 19.
Because these claim limitations are being interpreted under 35 U.S.C. § 112(f) they are being interpreted to cover the corresponding structure described in the specification as performing the claimed functions, and equivalents thereof.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. § 112(f) applicant may: (1) amend the claim limitations to avoid them being interpreted under 35 U.S.C. § 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. § 112(f).
Claim Rejections - 35 U.S.C. § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. §§ 102 and 103 (or as subject to pre-AIA 35 U.S.C. §§ 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 C.F.R. § 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. § 102(b)(2)(C) for any potential 35 U.S.C. § 102(a)(2) prior art against the later invention.
Claims 1-24 are rejected under 35 U.S.C. § 103 as being unpatentable over Li et al. (“Dynamic Dataflow Scheduling and Computation Mapping Techniques for Efficient Depthwise Separable Convolution Acceleration,” August 2021, https://ieeexplore.ieee.org/document/9432828, hereinafter Li) in view of Wellendorf et al. (US 4,199,784 A, hereinafter Wellendorf) and Ramaraju et al. (US 2013/0290753 A1, hereinafter Ramaraju).
As to independent claim 1, Li teaches a method of operating a depth-wise separable convolutional (DSC) network on a DSC accelerator (page 1 title), comprising:
determining, at a first time, a difference between a first throughput associated with a depth-wise convolution (DWC) engine of the DSC accelerator and a second throughput associated with a point-wise convolution (PWC) engine of the DSC accelerator (pages 3286-3287 section III.C scenario 2, particularly equations 10-11);
selectively activating, at a second time for each layer of the DSC network, one or more first processing elements (PEs) in one or more first columns of a first set of columns of first PEs associated with the DWC engine and one or more second PEs in one or more second columns of a second set of columns associated with the PWC engine based on the difference between the first throughput and the second throughput (page 3286 section III.C first paragraph and “scenario 2” paragraph, figure 9, deriving “d” as the solution to page 3287 equation 10); and
processing, at the run time (section IV paragraph 2) for each layer of the DSC network, an input via the DSC accelerator based on selectively activating the one or more first PEs in the one or more first columns and the one or more second PEs in the one or more second columns (pages 3288- 3291 section V).
Li does not appear to expressly teach a method comprising simultaneously transmitting, by a shift-register-based shuffler of the DSC accelerator, data elements, at a run time, based on the one or more first columns and the one or more second columns that are selectively activated.
Wellendorf teaches a method comprising simultaneously transmitting, by a shift-register-based shuffler [], data elements, at a run time, based on the one or more first columns and the one or more second columns [] (“said first group of shift registers are filled and adapted to read out the multiple picture lines read out therefrom in a parallel manner,” column 13 lines 10-13).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the selectively activated columns of Li to comprise the simultaneous transmitting of Wellendorf. (1) The Examiner finds that the prior art included each claim element listed above, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. (2) The Examiner finds that one of ordinary skill in the art could have combined the elements as claimed by known development methods, and that in combination, each element merely performs the same function as it does separately. (3) The Examiner finds that one of ordinary skill in the art would have recognized that the results of the combination were predictable, namely simultaneously transmitting multiple columns (“said first group of shift registers are filled and adapted to read out the multiple picture lines read out therefrom in a parallel manner,” column 13 lines 10-13). Therefore, the rationale to support a conclusion that the claim would have been obvious is that the combining prior art elements according to known methods to yield predictable results to one of ordinary skill in the art. See MPEP § 2143(I)(A).
Li/Wellendorf does not appear to expressly teach a method comprising power gating, at the run time, one or more non-active PWC PE columns of the PWC engine.
Ramaraju teaches a method comprising power gating, at the run time, one or more non-active [] columns of the [chip] (“selective fine grain control of drowsy/power gating of a memory array at an individual column level,” paragraph 0074 lines 20-22).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the selectively activated columns of Li/Wellendorf to comprise the power gating of Ramaraju. (1) The Examiner finds that the prior art included each claim element listed above, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. (2) The Examiner finds that one of ordinary skill in the art could have combined the elements as claimed by known development methods, and that in combination, each element merely performs the same function as it does separately. (3) The Examiner finds that one of ordinary skill in the art would have recognized that the results of the combination were predictable, namely “improved … power management” (Ramaraju paragraph 0074 line 22). Therefore, the rationale to support a conclusion that the claim would have been obvious is that the combining prior art elements according to known methods to yield predictable results to one of ordinary skill in the art. See MPEP § 2143(I)(A).
As to dependent claim 2, the rejection of claim 1 is incorporated. Li/Wellendorf/Ramaraju further teaches a method in which the first time is a compile time (section IV paragraph 2).
As to dependent claim 3, the rejection of claim 1 is incorporated. Li/Wellendorf/Ramaraju further a method in which:
each first PE is a dual functional (DF) PE (“each MA can be configured to support different computing modes, including STC/DWC mode, PWC mode and fully-connected (FC) mode,” page 3286 section III.C lines 6-8); and
each second PE is one of the DF PE or a PWC PE (page 3286 figure 9 showing DWC and PWC modes).
As to dependent claim 4, the rejection of claim 1 is incorporated. Li/Wellendorf/Ramaraju further a method in which:
the DWC engine includes a plurality of window buffers (page 3283 figure 6, page 3284 section III.B fourth paragraph, page 3285 figure 8(b,c)); and
each of the plurality of window buffers reads one or more input feature maps from a respective input channel of a plurality of input channels (page 3283 figure 6, page 3284 section III.B fourth paragraph, page 3285 figure 8(b,c)).
As to dependent claim 5, the rejection of claim 4 is incorporated. Li/Wellendorf/Ramaraju further a method in which:
each window buffer outputs to at least one first PE (page 3286 section III.C, figure 9, page 3283 figure 6, page 3285 figure 8(b,c)); and
each of the at least one first PE is associated with a different column of the first set of columns (page 3286 section III.C, figure 9, page 3283 figure 6, page 3285 figure 8(b,c)).
As to dependent claim 6, the rejection of claim 1 is incorporated. Li/Wellendorf/Ramaraju further a method in which the one or more first PEs and the one or more second PEs are selectively activated based on a kernel size, a number of output channels, a first delay compensation in the DWC engine, and/or a second delay compensation in the PWC engine (page 3286 section III.C, figure 9 deriving “d” as the solution to page 3287 equation 10, which is a first or second delay compensation and also includes a kernel size).
As to independent claim 7, Li teaches an apparatus for operating a depth-wise separable convolutional (DSC) network on a DSC accelerator (page 1 title), comprising:
one or more processors (page 3291 section V.C); and
one or more memories (page 3291 section V.C) coupled with the one or more processors and storing instructions operable, when executed by the one or more processors, to cause the apparatus to:
determine, at a first time, a difference between a first throughput associated with a depth-wise convolution (DWC) engine of the DSC accelerator and a second throughput associated with a point-wise convolution (PWC) engine of the DSC accelerator (pages 3286-3287 section III.C scenario 2, particularly equations 10-11);
selectively activate, at a second time for each layer of the DSC network, one or more first processing elements (PEs) in one or more first columns of a first set of columns of first PEs associated with the DWC engine and one or more second PEs in one or more second columns of a second set of columns associated with the PWC engine based on the difference between the first throughput and the second throughput (page 3286 section III.C first paragraph and “scenario 2” paragraph, figure 9, deriving “d” as the solution to page 3287 equation 10); and
process, at the run time (section IV paragraph 2) for each layer of the DSC network, an input via the DSC accelerator based on selectively activating the one or more first PEs in the one or more first columns and the one or more second PEs in the one or more second columns (pages 3288- 3291 section V).
Li does not appear to expressly teach an apparatus comprising instructions operable to simultaneously transmit, by a shift-register-based shuffler of the DSC accelerator, data elements, at a run time, based on the one or more first columns and the one or more second columns that are selectively activated.
Wellendorf teaches an apparatus comprising instructions operable to simultaneously transmit, by a shift-register-based shuffler [], data elements, at a run time, based on the one or more first columns and the one or more second columns [] (“said first group of shift registers are filled and adapted to read out the multiple picture lines read out therefrom in a parallel manner,” column 13 lines 10-13).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the selectively activated columns of Li to comprise the simultaneous transmitting of Wellendorf. (1) The Examiner finds that the prior art included each claim element listed above, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. (2) The Examiner finds that one of ordinary skill in the art could have combined the elements as claimed by known development methods, and that in combination, each element merely performs the same function as it does separately. (3) The Examiner finds that one of ordinary skill in the art would have recognized that the results of the combination were predictable, namely simultaneously transmitting multiple columns (“said first group of shift registers are filled and adapted to read out the multiple picture lines read out therefrom in a parallel manner,” column 13 lines 10-13). Therefore, the rationale to support a conclusion that the claim would have been obvious is that the combining prior art elements according to known methods to yield predictable results to one of ordinary skill in the art. See MPEP § 2143(I)(A).
Li/Wellendorf does not appear to expressly teach an apparatus comprising instructions operable to power gate, at the run time, one or more non-active PWC PE columns of the PWC engine.
Ramaraju teaches an apparatus comprising instructions operable to power gate, at the run time, one or more non-active [] columns of the [chip] (“selective fine grain control of drowsy/power gating of a memory array at an individual column level,” paragraph 0074 lines 20-22).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the selectively activated columns of Li/Wellendorf to comprise the power gating of Ramaraju. (1) The Examiner finds that the prior art included each claim element listed above, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. (2) The Examiner finds that one of ordinary skill in the art could have combined the elements as claimed by known development methods, and that in combination, each element merely performs the same function as it does separately. (3) The Examiner finds that one of ordinary skill in the art would have recognized that the results of the combination were predictable, namely “improved … power management” (Ramaraju paragraph 0074 line 22). Therefore, the rationale to support a conclusion that the claim would have been obvious is that the combining prior art elements according to known methods to yield predictable results to one of ordinary skill in the art. See MPEP § 2143(I)(A).
As to dependent claim 8, the rejection of claim 7 is incorporated. Li/Wellendorf/Ramaraju further teaches an apparatus in which the first time is a compile time (section IV paragraph 2).
As to dependent claim 9, the rejection of claim 7 is incorporated. Li/Wellendorf/Ramaraju further an apparatus in which:
each first PE is a dual functional (DF) PE (“each MA can be configured to support different computing modes, including STC/DWC mode, PWC mode and fully-connected (FC) mode,” page 3286 section III.C lines 6-8); and
each second PE is one of the DF PE or a PWC PE (page 3286 figure 9 showing DWC and PWC modes).
As to dependent claim 10, the rejection of claim 7 is incorporated. Li/Wellendorf/Ramaraju further an apparatus in which:
the DWC engine includes a plurality of window buffers (page 3283 figure 6, page 3284 section III.B fourth paragraph, page 3285 figure 8(b,c)); and
each of the plurality of window buffers reads one or more input feature maps from a respective input channel of a plurality of input channels (page 3283 figure 6, page 3284 section III.B fourth paragraph, page 3285 figure 8(b,c)).
As to dependent claim 11, the rejection of claim 10 is incorporated. Li/Wellendorf/Ramaraju further an apparatus in which:
each window buffer outputs to at least one first PE (page 3286 section III.C, figure 9, page 3283 figure 6, page 3285 figure 8(b,c)); and
each of the at least one first PE is associated with a different column of the first set of columns (page 3286 section III.C, figure 9, page 3283 figure 6, page 3285 figure 8(b,c)).
As to dependent claim 12, the rejection of claim 7 is incorporated. Li/Wellendorf/Ramaraju further an apparatus in which the one or more first PEs and the one or more second PEs are selectively activated based on a kernel size, a number of output channels, a first delay compensation in the DWC engine, and/or a second delay compensation in the PWC engine (page 3286 section III.C, figure 9 deriving “d” as the solution to page 3287 equation 10, which is a first or second delay compensation and also includes a kernel size).
As to independent claim 13, Li teaches a non-transitory computer-readable medium (page 3291 section V.C) having program code recorded thereon for operating a depth-wise separable convolutional (DSC) network on a DSC accelerator (page 1 title), the program code executed by a processor and comprising:
program code to determine, at a first time, a difference between a first throughput associated with a depth-wise convolution (DWC) engine of the DSC accelerator and a second throughput associated with a point-wise convolution (PWC) engine of the DSC accelerator (pages 3286-3287 section III.C scenario 2, particularly equations 10-11);
program code to selectively activate, at a second time for each layer of the DSC network, one or more first processing elements (PEs) in one or more first columns of a first set of columns of first PEs associated with the DWC engine and one or more second PEs in one or more second columns of a second set of columns associated with the PWC engine based on the difference between the first throughput and the second throughput (page 3286 section III.C first paragraph and “scenario 2” paragraph, figure 9, deriving “d” as the solution to page 3287 equation 10); and
program code to process, at the run time (section IV paragraph 2) for each layer of the DSC network, an input via the DSC accelerator based on selectively activating the one or more first PEs in the one or more first columns and the one or more second PEs in the one or more second columns (pages 3288- 3291 section V).
Li does not appear to expressly teach a medium comprising program code to simultaneously transmit, by a shift-register-based shuffler of the DSC accelerator, data elements, at a run time, based on the one or more first columns and the one or more second columns that are selectively activated.
Wellendorf teaches a medium comprising program code to simultaneously transmit, by a shift-register-based shuffler [], data elements, at a run time, based on the one or more first columns and the one or more second columns [] (“said first group of shift registers are filled and adapted to read out the multiple picture lines read out therefrom in a parallel manner,” column 13 lines 10-13).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the selectively activated columns of Li to comprise the simultaneous transmitting of Wellendorf. (1) The Examiner finds that the prior art included each claim element listed above, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. (2) The Examiner finds that one of ordinary skill in the art could have combined the elements as claimed by known development methods, and that in combination, each element merely performs the same function as it does separately. (3) The Examiner finds that one of ordinary skill in the art would have recognized that the results of the combination were predictable, namely simultaneously transmitting multiple columns (“said first group of shift registers are filled and adapted to read out the multiple picture lines read out therefrom in a parallel manner,” column 13 lines 10-13). Therefore, the rationale to support a conclusion that the claim would have been obvious is that the combining prior art elements according to known methods to yield predictable results to one of ordinary skill in the art. See MPEP § 2143(I)(A).
Li/Wellendorf does not appear to expressly teach a medium comprising program code to power gate, at the run time, one or more non-active PWC PE columns of the PWC engine.
Ramaraju teaches a medium comprising program code to power gate, at the run time, one or more non-active [] columns of the [chip] (“selective fine grain control of drowsy/power gating of a memory array at an individual column level,” paragraph 0074 lines 20-22).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the selectively activated columns of Li/Wellendorf to comprise the power gating of Ramaraju. (1) The Examiner finds that the prior art included each claim element listed above, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. (2) The Examiner finds that one of ordinary skill in the art could have combined the elements as claimed by known development methods, and that in combination, each element merely performs the same function as it does separately. (3) The Examiner finds that one of ordinary skill in the art would have recognized that the results of the combination were predictable, namely “improved … power management” (Ramaraju paragraph 0074 line 22). Therefore, the rationale to support a conclusion that the claim would have been obvious is that the combining prior art elements according to known methods to yield predictable results to one of ordinary skill in the art. See MPEP § 2143(I)(A).
As to dependent claim 14, the rejection of claim 13 is incorporated. Li/Wellendorf/Ramaraju further teaches a medium in which the first time is a compile time (section IV paragraph 2).
As to dependent claim 15, the rejection of claim 13 is incorporated. Li/Wellendorf/Ramaraju further a medium in which:
each first PE is a dual functional (DF) PE (“each MA can be configured to support different computing modes, including STC/DWC mode, PWC mode and fully-connected (FC) mode,” page 3286 section III.C lines 6-8); and
each second PE is one of the DF PE or a PWC PE (page 3286 figure 9 showing DWC and PWC modes).
As to dependent claim 16, the rejection of claim 13 is incorporated. Li/Wellendorf/Ramaraju further a medium in which:
the DWC engine includes a plurality of window buffers (page 3283 figure 6, page 3284 section III.B fourth paragraph, page 3285 figure 8(b,c)); and
each of the plurality of window buffers reads one or more input feature maps from a respective input channel of a plurality of input channels (page 3283 figure 6, page 3284 section III.B fourth paragraph, page 3285 figure 8(b,c)).
As to dependent claim 17, the rejection of claim 16 is incorporated. Li/Wellendorf/Ramaraju further a medium in which:
each window buffer outputs to at least one first PE (page 3286 section III.C, figure 9, page 3283 figure 6, page 3285 figure 8(b,c)); and
each of the at least one first PE is associated with a different column of the first set of columns (page 3286 section III.C, figure 9, page 3283 figure 6, page 3285 figure 8(b,c)).
As to dependent claim 18, the rejection of claim 13 is incorporated. Li/Wellendorf/Ramaraju further a medium in which the one or more first PEs and the one or more second PEs are selectively activated based on a kernel size, a number of output channels, a first delay compensation in the DWC engine, and/or a second delay compensation in the PWC engine (page 3286 section III.C, figure 9 deriving “d” as the solution to page 3287 equation 10, which is a first or second delay compensation and also includes a kernel size).
As to independent claim 19, Li teaches an apparatus for operating a depth-wise separable convolutional (DSC) network on a DSC accelerator (page 1 title), comprising:
means for determining, at a first time, a difference between a first throughput associated with a depth-wise convolution (DWC) engine of the DSC accelerator and a second throughput associated with a point-wise convolution (PWC) engine of the DSC accelerator (pages 3286-3287 section III.C scenario 2, particularly equations 10-11);
means for selectively activating, at a second time for each layer of the DSC network, one or more first processing elements (PEs) in one or more first columns of a first set of columns of first PEs associated with the DWC engine and one or more second PEs in one or more second columns of a second set of columns associated with the PWC engine based on the difference between the first throughput and the second throughput (page 3286 section III.C first paragraph and “scenario 2” paragraph, figure 9, deriving “d” as the solution to page 3287 equation 10); and
means for processing, at the run time (section IV paragraph 2) for each layer of the DSC network, an input via the DSC accelerator based on selectively activating the one or more first PEs in the one or more first columns and the one or more second PEs in the one or more second columns (pages 3288- 3291 section V).
Li does not appear to expressly teach an apparatus comprising means for simultaneously transmitting, by a shift-register-based shuffler of the DSC accelerator, data elements, at a run time, based on the one or more first columns and the one or more second columns that are selectively activated.
Wellendorf teaches an apparatus comprising means for simultaneously transmitting, by a shift-register-based shuffler [], data elements, at a run time, based on the one or more first columns and the one or more second columns [] (“said first group of shift registers are filled and adapted to read out the multiple picture lines read out therefrom in a parallel manner,” column 13 lines 10-13).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the selectively activated columns of Li to comprise the simultaneous transmitting of Wellendorf. (1) The Examiner finds that the prior art included each claim element listed above, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. (2) The Examiner finds that one of ordinary skill in the art could have combined the elements as claimed by known development methods, and that in combination, each element merely performs the same function as it does separately. (3) The Examiner finds that one of ordinary skill in the art would have recognized that the results of the combination were predictable, namely simultaneously transmitting multiple columns (“said first group of shift registers are filled and adapted to read out the multiple picture lines read out therefrom in a parallel manner,” column 13 lines 10-13). Therefore, the rationale to support a conclusion that the claim would have been obvious is that the combining prior art elements according to known methods to yield predictable results to one of ordinary skill in the art. See MPEP § 2143(I)(A).
Li/Wellendorf does not appear to expressly teach an apparatus comprising means for power gating, at the run time, one or more non-active PWC PE columns of the PWC engine.
Ramaraju teaches an apparatus comprising means for power gating, at the run time, one or more non-active [] columns of the [chip] (“selective fine grain control of drowsy/power gating of a memory array at an individual column level,” paragraph 0074 lines 20-22).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the selectively activated columns of Li/Wellendorf to comprise the power gating of Ramaraju. (1) The Examiner finds that the prior art included each claim element listed above, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. (2) The Examiner finds that one of ordinary skill in the art could have combined the elements as claimed by known development methods, and that in combination, each element merely performs the same function as it does separately. (3) The Examiner finds that one of ordinary skill in the art would have recognized that the results of the combination were predictable, namely “improved … power management” (Ramaraju paragraph 0074 line 22). Therefore, the rationale to support a conclusion that the claim would have been obvious is that the combining prior art elements according to known methods to yield predictable results to one of ordinary skill in the art. See MPEP § 2143(I)(A).
As to dependent claim 20, the rejection of claim 19 is incorporated. Li/Wellendorf/Ramaraju further teaches an apparatus in which the first time is a compile time (section IV paragraph 2).
As to dependent claim 21, the rejection of claim 19 is incorporated. Li/Wellendorf/Ramaraju further an apparatus in which:
each first PE is a dual functional (DF) PE (“each MA can be configured to support different computing modes, including STC/DWC mode, PWC mode and fully-connected (FC) mode,” page 3286 section III.C lines 6-8); and
each second PE is one of the DF PE or a PWC PE (page 3286 figure 9 showing DWC and PWC modes).
As to dependent claim 22, the rejection of claim 19 is incorporated. Li/Wellendorf/Ramaraju further an apparatus in which:
the DWC engine includes a plurality of window buffers (page 3283 figure 6, page 3284 section III.B fourth paragraph, page 3285 figure 8(b,c)); and
each of the plurality of window buffers reads one or more input feature maps from a respective input channel of a plurality of input channels (page 3283 figure 6, page 3284 section III.B fourth paragraph, page 3285 figure 8(b,c)).
As to dependent claim 23, the rejection of claim 22 is incorporated. Li/Wellendorf/Ramaraju further an apparatus in which:
each window buffer outputs to at least one first PE (page 3286 section III.C, figure 9, page 3283 figure 6, page 3285 figure 8(b,c)); and
each of the at least one first PE is associated with a different column of the first set of columns (page 3286 section III.C, figure 9, page 3283 figure 6, page 3285 figure 8(b,c)).
As to dependent claim 24, the rejection of claim 19 is incorporated. Li/Wellendorf/Ramaraju further an apparatus in which the one or more first PEs and the one or more second PEs are selectively activated based on a kernel size, a number of output channels, a first delay compensation in the DWC engine, and/or a second delay compensation in the PWC engine (page 3286 section III.C, figure 9 deriving “d” as the solution to page 3287 equation 10, which is a first or second delay compensation and also includes a kernel size).
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure:
US 2019/0139477 A1 disclosing simultaneously transmitting, by a shift-register-based shuffler, data elements, at a run time, based on the one or more first columns and the one or more second columns that are activated
Applicant is required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action.
Applicant’s amendments necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 C.F.R. § 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 C.F.R. § 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
In the interests of compact prosecution, Applicant is invited to contact the examiner via electronic media pursuant to USPTO policy outlined MPEP § 502.03. All electronic communication must be authorized in writing. Applicant may wish to file an Internet Communications Authorization Form PTO/SB/439. Applicant may wish to request an interview using the Interview Practice website: http://www.uspto.gov/patent/laws-and-regulations/interview-practice.
Applicant is reminded Internet e-mail may not be used for communication for matters under 35 U.S.C. § 132 or which otherwise require a signature. A reply to an Office action may NOT be communicated by Applicant to the USPTO via Internet e-mail. If such a reply is submitted by Applicant via Internet e-mail, a paper copy will be placed in the appropriate patent application file with an indication that the reply is NOT ENTERED. See MPEP § 502.03(II).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ryan Barrett whose telephone number is 571 270 3311. The examiner can normally be reached 9:00am to 5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Michelle Bechtold can be reached at 571 431 0762. The fax phone number for the organization where this application or proceeding is assigned is 571 273 8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Ryan Barrett/
Primary Examiner, Art Unit 2148
