Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 28, 2025 has been entered.
Response to Amendment
This Office action is in response to applicant’s amendment filed December 28, 2025. Claims 3 and 13 have been cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-12, and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Crawford et al. (U.S. patent number 10359831 B2), hereinafter referred to as Crawford, in view of Donald et al. (U.S. patent application publication 20070204106 A1), hereinafter referred to as Donald, further in view of Corulli et al. (U.S. patent application publication 20070177417 A1), hereinafter referred to as Corulli.
Regarding claim 1, Crawford teaches a method of a computing system (Fig. 1 data processing system 10) for partial cache deactivation, comprising: deactivating a region of a cache based on cache hit counts; (“a determination is made if at least one bank of the cache is currently powered (N>1) and if the cache hit bandwidth (HBW) is less than the memory bandwidth equivalent, i.e. (N−Td)*L/ED. If this is true then at step 78 a bank is powered down and the flow proceeds to step 74” [Crawford Column 10 lines 7-12] wherein the cache hit bandwidth is based on cache hit counts [Crawford Fig. 1 and 2 cache performance monitoring unit 40]) estimating a first change in leakage power of the cache (“calculating a cache hit bandwidth equivalent for an increment increase in cache leakage power” [Crawford col. 10 lines 32-34]. Wherein an increment increase is a change and this calculation would involve an estimation/calculation of the increment increase of cache leakage power) when the region of the cache is deactivated (Crawford Fig. 4 shows a cyclical algorithm for monitoring the cache, performing calculations, and then changing the amount of cache that is activated correspondingly. As the logic repeats after deactivating a cache bank, the above calculation involving the change in leakage power would be performed alongside powering down a portion of the cache. See for example Fig. 4 steps 78, 74, 60, 62, 64, and 70. Also note that in Crawford’s mathematical expression (N-Td) * L/ED, N*L would represent changes in leakage and accounts for changes in the number of regions of the cache that are activated (see Crawford Col. 7 lines 51-59)) monitoring a bandwidth of a memory hierarchy device, (As Crawford monitors a change in bandwidth of a memory hierarchy device, it would have been obvious to a person having ordinary skill in the art to monitor the bandwidth of a memory hierarchy device (for example, to find the change in bandwidth, it would be obvious to first monitor the bandwidth, see “a determination of the miss count change 52 between a previous miss count 58 and the current miss count over the time period 54 gives the miss bandwidth” [Crawford col. 9 lines 13-16]). Wherein a person having ordinary skill in the art would recognize that the accesses to a higher level memory hierarchy device comes from misses in lower levels of the memory hierarchy, so it would be obvious to monitor bandwidth to a higher level memory hierarchy device in view of monitoring a miss bandwidth at a lower level memory as the values would be approximately equivalent. It would also be obvious in view of the concepts taught by Crawford such as “calculating a memory bandwidth equivalent of expending the current active cache leakage power on memory access” [Crawford abstract]. The examiner notes that the broadest reasonable interpretation of “monitoring a bandwidth of a memory hierarchy device” only requires the bandwidth of the memory hierarchy device to be monitored and does not require the memory hierarchy device itself to be monitored. See also Crawford Fig. 4 step 62 “Monitoring period elapsed?” and claim 9 “calculating a cache miss bandwidth from monitoring performance of the cache”) wherein the memory hierarchy device has a larger capacity than the cache is at a next level downstream from the cache in a memory hierarchy of the computing system (Crawford further explains “expending the current active cache leakage power on memory access” as “meaning here going beyond the cache to access the required data items, e.g. to external memory such as DRAM” [Crawford col. 2 lines 42-44]. A person having ordinary skill in the art would recognize that DRAM is a memory hierarchy device that has a larger capacity than cache. See also Crawford Fig. 1) estimating a second change in dynamic power when the region of the cache is deactivated, wherein the dynamic power is converted from the monitored bandwidth (“it is recognised here that the equivalent memory cost, i.e. the power required to return the same bandwidth from memory (meaning here going beyond the cache to access the required data items, e.g. to external memory such as DRAM), should be evaluated” [Crawford column 2 lines 40-46]. Therefore it would have been obvious to a person having ordinary skill in the art to convert the dynamic power from the monitored bandwidth. As the algorithm of Crawford is cyclical (see Crawford Fig. 4), it also would have been obvious to perform the claimed estimation following a cache region deactivation) and adjusting a size of the deactivated region based on a combined change that includes the first change and the second change (“a decision to reduce the proportion of the cache which is currently powered is made based on calculating a memory bandwidth equivalent of expending the current active cache leakage power on memory access. The cache hit bandwidth is compared against this memory bandwidth equivalent and when the cache hit bandwidth is less than the memory bandwidth equivalent, the proportion of the cache which is currently powered is reduced. A analogous decision may also be made and based on calculating a cache hit bandwidth equivalent for an increment increase in cache leakage power, and when the cache miss bandwidth exceeds the cache hit bandwidth equivalent, the proportion of the cache which is currently powered is increased.” [Crawford col. 10 lines 22-36] Where the bandwidth equivalent is the dynamic power, and calculating the leakage and dynamic power based on an increment increase and comparing them is functionally equivalent to calculating the combined change. The objective of this calculation in Crawford is to compare the current (pre-deactivation) state of the cache with a possible future (post cache bank deactivation) state of the cache, and then use that information to determine whether the amount of deactivated cache should be changed to save total power. Therefore the claimed limitation would have been obvious).
Crawford does not appear to explicitly disclose estimating a first change in leakage power of the cache based on operating conditions of the cache including voltage and temperature.
However, Donald teaches estimating leakage power of a cache based on operating conditions of the cache including temperature (“In one embodiment, one or more sensors 210 (such as temperature or power consumption sensors) may be utilized to measure or determine the leakage power of the shared cache 108” [Donald paragraph 17]. Therefore it would have been obvious to incorporate temperature into the estimate of a first change in leakage power).
Crawford and Donald are analogous art because they are from the same field of endeavor of optimizing memory device power consumption.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Crawford and Donald before him or her, to modify the method of Crawford to include the sensors and sensor detections in the estimation of leakage power of Donald because it will improve the ability of the invention to reduce power leakage/waste.
The motivation for doing so would be that a better leakage power estimation from incorporating temperature would improve the ability of the method to reduce power leakage and also that a temperature sensor would be valuable for protecting the hardware from overheating by detecting its temperature.
Corulli teaches estimating leakage power of a cache based on operating conditions of the cache including voltage (voltage sensors 54 and 55; “In certain embodiments, monitoring can be performed by a computer system configured to control measurement of voltages, record data, and calculate capacitor parameters including leakage current” [Corulli paragraph 22]. It would have been obvious for one of ordinary skill in the art to use the voltage measurements and leakage current parameters to estimate leakage power as power is a simple function of voltage and current).
Corulli is analogous art as it is in the same field of endeavor of dynamically measuring the operating conditions of electronic components.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Crawford/Donald and Corulli before him or her, to modify the device of Crawford/Donald to include the sensors and sensor detections in the estimation of leakage power of Corulli because it will improve the system performance by reducing overall power consumption and heat generation with voltage detections incorporated into the leakage power estimation.
The motivation for doing so would be that the having voltage sensors would be further useful for protecting the hardware from sudden surges in voltage.
Therefore, it would have been obvious to combine Crawford, Donald, and Corulli to obtain the invention as specified in the instant claim.
Regarding claims 2 and 4-10, the applicant is directed to the rejections of claims 12 and 14-20 (respectively) set forth below, as they are rejected based on the same rationale.
Regarding claim 11, Crawford teaches a computing system (Fig. 1 data processing system 10) operative to perform partial cache deactivation, comprising: one or more processors; (Fig. 1 processor core 12) a cache; (Fig. 1 cache 14) and a memory hierarchy device, which has a larger capacity than the cache and is at a next level downstream from the cache in a memory hierarchy of the computing system, (Fig. 1 memory (DRAM) 16) wherein the computing system is operative to: deactivate a region of a based on cache hit counts; (“a determination is made if at least one bank of the cache is currently powered (N>1) and if the cache hit bandwidth (HBW) is less than the memory bandwidth equivalent, i.e. (N−Td)*L/ED. If this is true then at step 78 a bank is powered down and the flow proceeds to step 74” [Column 10 lines 7-12] wherein the cache hit bandwidth is based on cache hit counts [Fig. 1 and 2 cache performance monitoring unit 40]) estimate a first change in leakage power of the cache (“calculating a cache hit bandwidth equivalent for an increment increase in cache leakage power” [Crawford col. 10 lines 32-34]. Wherein an increment increase is a change and this calculation would involve an estimation/calculation of the increment increase of cache leakage power) when the region of the cache is deactivated; (Crawford Fig. 4 shows a cyclical algorithm for monitoring the cache, performing calculations, and then changing the amount of cache that is activated correspondingly. As the logic repeats after deactivating a cache bank, the above calculation involving the change in leakage power would be performed alongside powering down a portion of the cache. See for example Fig. 4 steps 78, 74, 60, 62, 64, and 70. Also note that in Crawford’s mathematical expression (N-Td) * L/ED, N*L would represent changes in leakage and accounts for changes in the number of regions of the cache that are activated (see Crawford Col. 7 lines 51-59)) monitor a bandwidth of the memory hierarchy device; (As Crawford monitors a change in bandwidth of a memory hierarchy device, it would have been obvious to a person having ordinary skill in the art to monitor the bandwidth of a memory hierarchy device (for example, to find the change in bandwidth, it would be obvious to first monitor the bandwidth, see “a determination of the miss count change 52 between a previous miss count 58 and the current miss count over the time period 54 gives the miss bandwidth” [Crawford col. 9 lines 13-16]). Wherein a person having ordinary skill in the art would recognize that the accesses to a higher level memory hierarchy device comes from misses in lower levels of the memory hierarchy, so it would be obvious to monitor bandwidth to a higher level memory hierarchy device in view of monitoring a miss bandwidth at a lower level memory as the values would be approximately equivalent. It would also be obvious in view of the concepts taught by Crawford such as “calculating a memory bandwidth equivalent of expending the current active cache leakage power on memory access” [Crawford abstract]. The examiner notes that the broadest reasonable interpretation of “monitoring a bandwidth of a memory hierarchy device” only requires the bandwidth of the memory hierarchy device to be monitored and does not require the memory hierarchy device itself to be monitored. See also Crawford Fig. 4 step 62 “Monitoring period elapsed?” and claim 9 “calculating a cache miss bandwidth from monitoring performance of the cache”) estimate a second change in dynamic power when the region of the cache is deactivated, wherein the dynamic power is converted from the monitored bandwidth (“it is recognised here that the equivalent memory cost, i.e. the power required to return the same bandwidth from memory (meaning here going beyond the cache to access the required data items, e.g. to external memory such as DRAM), should be evaluated” [Crawford column 2 lines 40-46]. Therefore it would have been obvious to a person having ordinary skill in the art to convert the dynamic power from the monitored bandwidth. As the algorithm of Crawford is cyclical (see Crawford Fig. 4), it also would have been obvious to perform the claimed estimation following a cache region deactivation) and adjust a size of the deactivated region based on a combined change that includes the first change and the second change (“a decision to reduce the proportion of the cache which is currently powered is made based on calculating a memory bandwidth equivalent of expending the current active cache leakage power on memory access. The cache hit bandwidth is compared against this memory bandwidth equivalent and when the cache hit bandwidth is less than the memory bandwidth equivalent, the proportion of the cache which is currently powered is reduced. A analogous decision may also be made and based on calculating a cache hit bandwidth equivalent for an increment increase in cache leakage power, and when the cache miss bandwidth exceeds the cache hit bandwidth equivalent, the proportion of the cache which is currently powered is increased.” [Crawford col. 10 lines 22-36] Where the bandwidth equivalent is the dynamic power, and calculating the leakage and dynamic power based on an increment increase and comparing them is functionally equivalent to calculating the combined change. The objective of this calculation in Crawford is to compare the current (pre-deactivation) state of the cache with a possible future (post cache bank deactivation) state of the cache, and then use that information to determine whether the amount of deactivated cache should be changed to save total power. Therefore the claimed limitation would have been obvious).
Crawford does not appear to explicitly disclose temperature sensors; voltage sensors; and estimating leakage power of the cache based on operating conditions of the cache including voltage and temperature.
Donald also does not appear to explicitly disclose voltage sensors and estimating leakage power of the cache based on operating conditions of the cache including voltage.
However, Donald does teach temperature sensors and estimating leakage power of the cache based on operating conditions of the cache including temperature (“In one embodiment, one or more sensors 210 (such as temperature or power consumption sensors) may be utilized to measure or determine the leakage power of the shared cache 108” [Donald paragraph 17]. Therefore it would have been obvious to incorporate temperature into the estimate of a first change in leakage power).
Crawford and Donald are analogous art because they are from the same field of endeavor of optimizing memory device power consumption.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Crawford and Donald before him or her, to modify the device of Crawford to include the sensors and sensor detections in the estimation of leakage power of Donald because it will improve the ability of the invention to reduce power leakage/waste.
The motivation for doing so would be that a better leakage power estimation from incorporating temperature would improve the ability of the device to reduce power leakage and also that a temperature sensor would be valuable for protecting the hardware from overheating by detecting its temperature.
Corulli teaches voltage sensors and estimating leakage power of the cache based on operating conditions of the cache based on voltage (voltage sensors 54 and 55; “In certain embodiments, monitoring can be performed by a computer system configured to control measurement of voltages, record data, and calculate capacitor parameters including leakage current” [Corulli paragraph 22]. It would have been obvious for one of ordinary skill in the art to use the voltage measurements and leakage current parameters to estimate leakage power as power is a simple function of voltage and current).
Corulli is analogous art as it is in the same field of endeavor of dynamically measuring the operating conditions of electronic components.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Crawford/Donald and Corulli before him or her, to modify the device of Crawford/Donald to include the sensors and sensor detections in the estimation of leakage power of Corulli because it will improve the system performance by reducing overall power consumption and heat generation, leading to better efficiency, with voltage detections incorporated into the leakage power estimation.
The motivation for doing so would be that the having voltage sensors would be further useful for protecting the hardware from sudden surges in voltage.
Therefore, it would have been obvious to combine Crawford, Donald, and Corulli to obtain the invention as specified in the instant claim.
Regarding claim 12, the combination of Crawford/Donald/Corulli teaches, as best understood by the examiner in light of the 112(b) rejection above, The computing system of claim 11, wherein the first change occurs, at least in part, when at least one of the voltage and the temperature changes (The change calculated by Crawford is based on changes that would occur when a cache bank is powered down (see Crawford Col. 10 lines 7-12 as cited above), which a person having ordinary skill in the art would recognize would also simultaneously cause voltage and temperature changes in the cache. Additionally, Corulli and Donald teach voltage and temperature impacting leakage power (see the rejections to claims 1 and 11 above), so it would have been obvious to include voltage and temperature as factors in the first change (see the rejections to claims 1 and 11 above)).
Regarding claim 14, Crawford teaches the computing system of claim 11, wherein the computing system is further operative to: re-activate at least a portion of the deactivated region if the combined change indicates a power increase that exceeds a threshold (“The effect of this choice of value is to set how aggressively the decision making with regard to powering up the increment proportion of the cache is made, ranging from using the first power down threshold factor value which will more readily power up this increment proportion (essentially as soon as there is any expected cache hit bandwidth benefit of powering up this increment proportion), through a value very close to the second power-down threshold factor value (i.e. just above zero), which will result in this increment proportion of the cache only being powered up when a “whole bank's worth” of cache hit bandwidth is expected to be gained from it being powered.” [Crawford col. 5 lines 7-18 and Fig. 3B Tu]).
Regarding claim 15, Crawford teaches the computing system of claim 11, wherein the computing system when adjusting the size of the deactivated region is further operative to: estimate dynamic power from the bandwidth of the memory hierarchy device; (“it is recognised here that the equivalent memory cost, i.e. the power required to return the same bandwidth from memory (meaning here going beyond the cache to access the required data items, e.g. to external memory such as DRAM), should be evaluated” [Crawford column 2 lines 40-46]) and minimize power increase caused by the partial cache deactivation based on estimations of the leakage power and the dynamic power (“In turn this causes the memory bandwidth equivalent to be calculated corresponding to all of the currently powered proportion of the cache, through to a memory bandwidth equivalent corresponding to if that increment proportion were switched off. The effect of this choice of value is to set how aggressively the decision making with regard to powering down the increment proportion of the cache is made, ranging from using the first power down threshold factor value which will more readily power down this increment proportion (essentially as soon as the hit bandwidth benefit of powering this increment proportion is less than optimal), through to the second power-down threshold factor value, which will result in this increment proportion of the cache only being powered down when there is essentially perceived to be no hit bandwidth benefit at all to be gained from it being powered” [Crawford col. 3 lines 47-62]).
Regarding claim 16, the combination of Crawford/Donald/Corulli teaches the computing system of claim 13, wherein the computing system is further operative to: periodically detecting the voltage and the temperature of the cache; (“Capacitors can be disconnected from the charging current and their voltage monitored according to a programmed sequence. Monitoring can be periodic in nature” Corulli paragraph 10. Crawford also teaches a monitoring period [Fig. 4 step 62]. Considering this, it would have been obvious to incorporate the measurements by the temperature sensors of Donald with the periodic monitoring (detecting) of Crawford/Corulli to achieve the claimed limitation) and adjusting an estimation of the leakage power based on the detected voltage and the detected temperature ([Donald paragraph 17] and [Corulli paragraph 22]).
Regarding claim 17, the combination of Crawford/Donald/Corulli teaches the computing system of claim 11, wherein the leakage power is estimated using a leakage power model built specifically for a die that is used as the cache (“The monitoring may be performed at a “global” level for the entire cache, or may be performed on a per-bank basis. Accordingly, in some embodiments monitoring performance of the cache comprises monitoring a global cache performance” [Crawford col. 6 lines 11-15]. In the case of global performance monitoring, the leakage power model used in Crawford (such as in claim 1, “calculating an active cache leakage power”, the method of calculation would be a model) would be estimating the leakage power for a cache die).
Regarding claim 18, the combination of Crawford/Donald/Corulli teaches the computing system of claim 11, wherein the bandwidth indicates a data access rate from processors of the computing system to the memory hierarchy device (Crawford columns 6 lines 56-59 “As will be familiar to one of ordinary skill in the art, the processor core 12 performs data processing operations on data items which are retrieved from the memory 16” and abstract “calculating a memory bandwidth equivalent of expending the current active cache leakage power on memory access”. Furthermore, hit and miss bandwidths are found by the number of accesses counted over a monitoring period, making them a rate of data accesses [Crawford Fig. 2]).
Regarding claim 19, the combination of Crawford/Donald/Corulli teaches the computing system of claim 11, wherein the memory hierarchy device has a lower speed than the cache (A person having ordinary skill in the art would recognize that the DRAM of Crawford (such as DRAM 16 of Crawford Fig. 1) is a memory hierarchy device with a lower speed than the cache. Alternatively, Donald paragraphs 12-13 “For example, the shared cache 108 may locally cache data stored in a memory 114 for faster access by components of the processor 102. As shown in FIG. 1, the memory 114 may be in communication with the processors 102 via the interconnection 104. In an embodiment, the cache 108 (that may be shared) may include a mid-level cache (such as a level 2 (L2), a level 3 (L3), a level 4 (L4), or other levels of cache), a last level cache (LLC), and/or combinations thereof. In some embodiments, one or more of the cores 106 may include a level 1 (L1) cache (116-1) (generally referred to herein as "L1 cache 116"). Various components of the processor 102-1 may communicate with the shared cache 108 directly, through a bus (e.g., the bus 112), and/or a memory controller or hub.” One of ordinary skill in the art would recognize that L2, L3, and L4 cache would have a larger capacity and lower speed than the L1 cache and are also memory hierarchy devices).
Regarding claim 20, Crawford teaches the computing system of claim 11, wherein the memory hierarchy device is a main memory of the computing system (Crawford memory (DRAM) 16).
Response to Remarks
Examiner thanks the applicant for their remarks of December 28, 2025. The remarks have been accepted and fully considered.
In light of the amendments to the claims, the 112(b) rejections to claims 3 and 13 indicated in the previous Office action are withdrawn.
The applicant’s remarks regarding the 103 rejections to claims 1-2, 4-12, and 14-20 are not persuasive. See the updated 103 rejections above.
Pertinent Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Monferrer et al. (US 20080244278 A1)
Relevant excerpts: “However, leakage power may vary during run-time, for example, due to changes in temperature, supply voltage, or threshold voltage. Accordingly, power management techniques may be less accurate without knowledge of leakage power.” [paragraph 3]
“in various embodiments, the power management logic 112 may adjust power consumption of one or more components of a corresponding domain. For example, the logic 112 may utilize information such as the leakage power estimation value (e.g., provided by the corresponding logic 106), dynamic power estimation, and/or some other information (e.g., committed instructions per cycle, cache misses, etc.) to adjust supply voltage and/or threshold voltage of one or more components of the corresponding domain. Also, the logic 112 may adjust the frequency of a clock signal (e.g., a clock signal that is used within at least a portion of the corresponding domain). In an embodiment, the logic 112 may turn off one or more components such: one or more processor cores or portions of the processor cores (e.g., different pipelines, etc.) and/or data caches (e.g., including various levels of caches such as level 1 (L1), level 2 (L2), or other levels) or portions of data caches (e.g., different banks of caches).” [paragraph 12]
Cooper et al. (US 9851771 B2)
Relevant excerpt: “If there is an exception asserted, 404 YES branch, the power management can sample bandwidth, voltage, and/or current values as measured by a sensor” (Col. 8 lines 47-49)
Garg et al. (US 20220100247 A1) “HIERARCHICAL POWER MANAGEMENT APPARATUS AND METHOD”
Dwarkadas et al. (US 20040184340 A1) “Memory Hierarchy Reconfiguration For Energy And Performance In General-purpose Processor Architectures”
Palaniappan et al. (US 8713340 B2) “Method And Apparatus For Power Management Control Of An Embedded Memory Having Sleep And Shutdown Features”
Wang et al. (US 20140173207 A1) “Power Gating A Portion Of A Cache Memory”
Ismail (US 20080120514 A1) “THERMAL MANAGEMENT OF ON-CHIP CACHES THROUGH POWER DENSITY MINIMIZATION”
Cai et al. (Non-patent literature) "Power Reduction of Multiple Disks Using Dynamic Cache Resizing and Speed Control"
Chen et al. (US 20240095168 A1) is a related patent application.
Conclusion
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/C.J.O./
Examiner, Art Unit 2138
/Kaushikkumar M Patel/Primary Examiner, Art Unit 2138
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