DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement submitted on 17 Nov 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant's election with traverse of the restriction requirement in the reply filed on 3 Feb 2026 is acknowledged. The traversal is on the ground(s) that there is no serious search burden on the examiner to examine all of the claims. This is not found persuasive because there is always a serious burden on an examiner to search for two independent and distinct inventions in two different and distinct search areas. Therefore, the requirement is still deemed proper and is therefore made FINAL.
The requirement is still deemed proper and is therefore made FINAL.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 2 & 8 are objected to because of the following informalities:
Claim 2: "a halt period" should be replaced with "the halt period".
Claim 8: "algorism" should be replaced with "algorithm".
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The term “substantially” in claim 5 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is not clear how much or to what degree the total sum of halt periods of each of the plurality of single-phase power converting cells can vary from each other and still be interpreted as zero. For the purposes of examination, Examiner has interpreted this limitation as a total sum of halt periods of each of the plurality of single-phase power converting cells in the unit time is equal.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 & 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mori (JP 2005033891 A).
Regarding Claim 1, Mori teaches a power converting apparatus (2, 16, Fig 1) comprising: one or more series multiplex power converter (62-63, Fig 1) each including a plurality of single-phase power converting cells (52-57, Fig 1), outputs of the plurality of single-phase power converting cells being connected to each other in series (52-57 are connected to each other in series, Fig 1); control circuitry (16, Fig 1) configured to output a drive signal (152-157, Fig 1); each of the plurality of single-phase power converting cells having a plurality of switching elements (314-315, 321-322, Fig 5) and configured to output an output voltage (30, Fig 5) by switching the plurality of switching elements in accordance with the drive signal (21, Fig 5); and the control circuitry being configured to output the drive signal respectively to the plurality of single-phase power converting cells (16 sends drive signals 152-157 to cells 52-57, Fig 1) such that, during a halt period in which the plurality of switching elements of at least one of the plurality of single-phase power converting cells do not perform switching at a short time interval (during T4-T5 of 570 52 of group 62 and 56-57 of group 63 are held at 0V while 53 of group 62 and 55 of group 63 are switching, Fig 14) which is shorter than a predetermined time interval to output the output voltages (the period that 52 is held at 0V is shorter than T4-T5, Fig 14), the plurality of switching elements of a remainder of the plurality of single-phase power converting cells performs switching at the short time interval to output the output voltages (53-55 are switching during T4-T5 of 570 while 52 of group 62 and 56-57 of group 63 are held at 0V, Fig 14).
Regarding Claim 2, Mori teaches all of the limitations of Claim 1 above, and further teaches wherein the one or more series multiplex power converter comprises a plurality of series multiplex power converters (62-63, Fig 1), and wherein the control circuitry is configured to output the drive signal respectively to the plurality of single-phase power converting cells (16 sends drive signals 152-157 to 52-57, Fig 1) such that, during a-the halt period in which the plurality of switching elements of each of a-the plurality of single-phase power converting cells that constitute at least one of the plurality of series multiplex power converters do not perform switching at the short time interval to output the output voltages (during T4-T5 of 570 52 of group 62 and 56-57 of group 63 are held at 0V while 53 of group 62 and 55 of group 63 are switching, Fig 14) , the plurality of switching elements of a remainder of the plurality of series multiplex power converters performs switching at the short time interval to output the output voltages (53-55 are switching during T4-T5 of 570 while 52 of group 62 and 56-57 of group 63 are held at 0V, Fig 14).
Regarding claim 16, it is rejected for the same reasons as stated above for Claim 1.
Regarding claim 17, it is rejected for the same reasons as stated above for Claim 2.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Mori (JP 2005033891 A), in view of Inomata (US 20160056706 A1).
Regarding Claim 9, Mori discloses all of the limitations of Claim 2 above.
Mori does not disclose wherein the power converting apparatus is a matrix converter, and wherein, in the halt period, the matrix converter outputs a voltage ranked as a specific magnitude order among a plurality of input voltages.
Inomata teaches a conventional matrix converter (see Fig 1) including wherein the power converting apparatus is a matrix converter (1, Fig 1), and wherein, in the halt period ("in the time period during which the magnitude relationship between the input phase voltages Er, Es and Et remains unchanged", [0136]), the matrix converter outputs a voltage ranked as a specific magnitude order among a plurality of input voltages ("the magnitude relationship between the input phase voltages Er, Es and Et will be often referred to as an input voltage rank.", [0136-9]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the matrix converter in Mori, as taught by Inomata, as it provides the advantage of reducing conduction and/or switching losses ([0149-67] of Inomata).
Claims 12 & 19 are rejected under 35 U.S.C. 103 as being unpatentable over Mori (JP 2005033891 A), in view of Katayama (US 9906168 B2).
Regarding Claim 12, Mori discloses all of the limitations of Claim 1 above.
Mori does not disclose wherein the predetermined time interval is one cycle of a carrier signal that is compared with a voltage command to generate the drive signal.
Katayama teaches a conventional power converting apparatus (see Fig 1C & 2) including wherein the predetermined time interval (2*Ts, Fig 1C) is one cycle of a carrier signal (carrier signal completes a whole cycle after 2*Ts, Fig 1C) that is compared with a voltage command ("The comparator 34 compares the carrier signals Vc1′ and Vc2′ with the voltage command V* and generates PWM signals L1, L2, R1, and R2 based on a result of the comparison. The comparator 34 outputs the PWM signals L1, L2, R1, and R2 to the gate drive circuit 11.", Fig 2, Col 7 [12-16]) to generate the drive signal (L1, L2, R1, R2, Fig 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the power converting apparatus in Mori, as taught by Katayama, as it provides the advantage of reducing switching losses ([27-8] of Katayama).
Regarding Claim 19, it is rejected for the same reasons as stated above for Claim 12.
Allowable Subject Matter
Claims 3-4, 6-7, & 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 5 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 8 would be allowable if rewritten to overcome the objection(s) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 3, Mori teaches all of the limitations of Claim 2 above.
Mori does not teach wherein each of the at least one of the plurality of series multiplex power converters outputs a phase voltage, wherein (a number of a plurality of single-phase power converting cells in one series multiplex power converter) × (a number of levels of the plurality of single-phase power converting cells - 1) × 2 is N, and wherein the control circuitry sets a voltage range by dividing a range between a maximum output voltage and a minimum output voltage in one cycle of the phase voltage by a divisor of N, determines the halt period by a time during which the phase voltage continuously exists in one voltage range or a plurality of continuous voltage ranges for each cycle, and outputs the drive signal respectively to the plurality of single-phase power converting cells.
Prior art Hatano (JP 2006174663 A), Katayama (US 9906168 B2), and Inomata (US 20160056706 A1) are considered to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “wherein each of the at least one of the plurality of series multiplex power converters outputs a phase voltage, wherein (a number of a plurality of single-phase power converting cells in one series multiplex power converter) × (a number of levels of the plurality of single-phase power converting cells - 1) × 2 is N, and wherein the control circuitry sets a voltage range by dividing a range between a maximum output voltage and a minimum output voltage in one cycle of the phase voltage by a divisor of N, determines the halt period by a time during which the phase voltage continuously exists in one voltage range or a plurality of continuous voltage ranges for each cycle, and outputs the drive signal respectively to the plurality of single-phase power converting cells.”
Claims 4-7 are indicated as allowable, as they depend on Claim 3.
Regarding Claim 8, Mori discloses all of the limitations of Claim 2, and further discloses wherein the one or more series multiplex power converter comprises three series multiplex power converters (210, 220, 230, Fig 1), wherein the three series multiplex power converters output a first phase voltage (410, Fig 1), a second phase voltage (420, Fig 1), and a third phase voltage (430, Fig 1), respectively.
Mori does not disclose wherein the halt period is determined, based on an algorism->algorithm of discontinuous PWM, as a period during which one of the first phase voltage, the second phase voltage, and the third phase voltage becomes a maximum level or a minimum level.
Prior art Hatano (JP 2006174663 A), Katayama (US 9906168 B2), and Inomata (US 20160056706 A1) are considered to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “wherein the halt period is determined, based on an algorithm of discontinuous PWM, as a period during which one of the first phase voltage, the second phase voltage, and the third phase voltage becomes a maximum level or a minimum level.”
Regarding Claim 10, the combination of Mori and Inomata discloses all of the limitations of Claim 9, and further discloses wherein the matrix converter receives a plurality of phase AC voltages as inputs (input phase voltages Er, Es and Et, [0136] of Inomata), outputs a voltage of a phase ranked as any magnitude order among the plurality of phase AC voltages in the halt period ("in the time period during which the magnitude relationship between the magnitude relationship between the input phase voltages Er, Es and Et will be often referred to as an input voltage rank.", [0136-9] of Inomata).
Mori does not disclose performs switching at a time interval longer than the predetermined time interval in order for the voltage ranked as the specific magnitude order to be output when the magnitude order changes during the halt period.
Prior art Hatano (JP 2006174663 A) and Katayama (US 9906168 B2) are considered to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “performs switching at a time interval longer than the predetermined time interval in order for the voltage ranked as the specific magnitude order to be output when the magnitude order changes during the halt period.”
Claim 11 is indicated as allowable, as it depends on Claim 10.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Hatano (JP 2006174663 A) discloses a multiplexed inverter device comprised of three single-phase full-bridge inverters with temperature measuring means for measuring the heat generated by the switch loss in the switch circuits.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER C CAULK whose telephone number is (571)270-0623. The examiner can normally be reached M-F 8:30-5:30, every other Fri off.
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/J.C.C./Examiner, Art Unit 2838
/GARY L LAXTON/Primary Examiner, Art Unit 2838 3/19/2026