DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 1/7/2025 and 4/16/2024 are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Liang (US 2016/0351468 A1 hereinafter Liang) in view of Cola et al (US 8919428 B2 hereinafter Cola).
Regarding Claim 1, Liang discloses in Fig 13: A power semiconductor module, comprising:
at least one heat sink (50);
at least one power semiconductor package (power package); and both the power semiconductor package (power package) and the heat sink (50) are to form the power semiconductor module (54) [0034, 0045-0047].
Liang does not disclose: a thermal conductive layer, wherein the thermal conductive layer is located between the heat sink and the power semiconductor package, and the thermal conductive layer is a thermal conductive material having metal bonding wires on a surface or a solid-state thermal conductive layer formed by curable silicone grease; and both the power semiconductor package and the heat sink are combined with the thermal conductive layer to form the power semiconductor module.
However, Cola in a similar device teaches in Fig 11: a thermal conductive layer (30), wherein the thermal conductive layer is located between the heat sink (HEAT SINK) and the semiconductor package (CPU), and the thermal conductive layer is a thermal conductive material having metal bonding wires (MWCNT) on a surface (See Fig 11) or a solid-state thermal conductive layer formed by curable silicone grease; and both the power semiconductor package and the heat sink are combined with the thermal conductive layer to form the power semiconductor module (taught by the combined device of Liang and Cola).
References Liang and Cola are analogous art because they both are directed to thermal management of semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Liang with the specified features of Cola because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Liang and Cola so that the thermal conductive layer is located between the heat sink and the power semiconductor package, and the thermal conductive layer is a thermal conductive material having metal bonding wires on a surface or a solid-state thermal conductive layer formed by curable silicone grease; and both the power semiconductor package and the heat sink are combined with the thermal conductive layer to form the power semiconductor module as taught by Cola in Liang’s device since this provides a solution to the reliability and functionality issues faced at electrical interfaces.
Regarding Claim 2, Liang and Cola disclose: The power semiconductor module according to claim 1.
Liang does not disclose: wherein the thermal conductive layer comprises: a metal thermal conductive sheet and the metal bonding wires disposed on a surface of the metal thermal conductive sheet.
However, Cola in a similar device teaches in Fig 11: wherein the thermal conductive layer comprises: a metal thermal conductive sheet (30) and the metal bonding wires disposed on a surface of the metal thermal conductive sheet (Col 1 lines 40-65).
References Liang and Cola are analogous art because they both are directed to thermal management of semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Liang with the specified features of Cola because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Liang and Cola so that the thermal conductive layer comprises: a metal thermal conductive sheet and the metal bonding wires disposed on a surface of the metal thermal conductive sheet as taught by Cola in Liang’s device since this provides a solution to the reliability and functionality issues faced at electrical interfaces.
Regarding Claim 3, Liang and Cola disclose: The power semiconductor module according to claim 1.
Liang does not disclose: wherein the metal thermal conductive sheet is a copper foil, an aluminum foil, a silver foil, or a gold leaf, and the metal bonding wire is a nano copper wire, a nano aluminum wire, a nano silver wire, or a nano gold wire.
However, Cola in a similar device teaches in Fig 11: wherein the metal thermal conductive sheet (30) is a copper foil, an aluminum foil, a silver foil, or a gold leaf, and the metal bonding wire is a nano copper wire, a nano aluminum wire, a nano silver wire, or a nano gold wire (Col 1 lines 40-65).
References Liang and Cola are analogous art because they both are directed to thermal management of semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Liang with the specified features of Cola because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Liang and Cola so that the metal thermal conductive sheet is a copper foil, an aluminum foil, a silver foil, or a gold leaf, and the metal bonding wire is a nano copper wire, a nano aluminum wire, a nano silver wire, or a nano gold wire as taught by Cola in Liang’s device since this provides a solution to the reliability and functionality issues faced at electrical interfaces.
Regarding Claim 4, Liang and Cola disclose: The power semiconductor module according to claim 1.
Liang does not disclose: wherein the thermal conductive layer further comprises:
thermal conductive adhesive, and the thermal conductive adhesive is distributed in a gap between adjacent metal bonding wires.
However, Cola in a similar device teaches in Fig 11: wherein the thermal conductive layer further comprises: thermal conductive adhesive, and the thermal conductive adhesive is distributed in a gap between adjacent metal bonding wires (Col 18 lines 42-65).
References Liang and Cola are analogous art because they both are directed to thermal management of semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Liang with the specified features of Cola because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Liang and Cola so that the thermal conductive layer further comprises: thermal conductive adhesive, and the thermal conductive adhesive is distributed in a gap between adjacent metal bonding wires as taught by Cola in Liang’s device since this provides a solution to the reliability and functionality issues faced at electrical interfaces.
Regarding Claim 5, Liang and Cola disclose: The power semiconductor module according to claim 1, Liang further discloses in Fig 13: wherein there are two heat sinks, the two heat sinks (50) are respectively a first heat sink and a second heat sink that are opposite to each other, the power semiconductor package is disposed between the first heat sink and the second heat sink (See Fig 13).
Liang does not disclose: and the thermal conductive layer is disposed between the power semiconductor package and the first heat sink and between the power semiconductor package and the second heat sink.
However, Cola in a similar device teaches in Fig 11: a thermal conductive layer (30), wherein the thermal conductive layer is located between the heat sink (HEAT SINK) and the semiconductor package (CPU).
References Liang and Cola are analogous art because they both are directed to thermal management of semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Liang with the specified features of Cola because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Liang and Cola so that the thermal conductive layer is disposed between the power semiconductor package and the first heat sink and between the power semiconductor package and the second heat sink as taught by Cola in Liang’s device since this provides a solution to the reliability and functionality issues faced at electrical interfaces.
Regarding Claim 6, Liang and Cola disclose: The power semiconductor module according to claim 5, Liang further discloses in Fig 13: wherein one end of the first heat sink and one end of the second heat sink are connected by using a connecting plate, and the other end of the first heat sink and the other end of the second heat sink are connected by using a fastener; or two ends of the first heat sink and the second heat sink are connected by using a connecting pipe (Coolant manifold), and two ends of the first heat sink and the second heat sink are connected by using a connecting pipe (Coolant manifold) [0045].
Regarding Claim 7, Liang and Cola disclose: The power semiconductor module according to claim 6, wherein a heat dissipation water channel (62: path through the water channel) is disposed inside the first heat sink and a heat dissipation water channel is disposed inside the second heat sink, the heat dissipation water channel in the first heat sink and the heat dissipation water channel in the second heat sink are connected in series by using the connecting plate, and a water inlet and a water outlet that communicate with the heat dissipation water channels are respectively disposed at the other end of the first heat sink and the other end of the second heat sink; or
a heat dissipation water channel is disposed inside the first heat sink and a heat
dissipation water channel is disposed inside the second heat sink, the heat dissipation water channel in the first heat sink and the heat dissipation water channel in the second heat sink are connected in parallel by using the connecting pipes, and a water inlet is disposed at one end of the first heat sink, and a water outlet (76) is disposed at one end that is of the second heat sink and that is away from the water inlet (70). See Fig 13 [0045-0048].
Regarding Claim 8, Liang and Cola disclose: The power semiconductor module according to claim 1, Liang further discloses in Fig 7 and 13: wherein each power semiconductor package at least comprises a first substrate (46), a second substrate, (48) and at least one chip (22/24), and the chip is fastened between the first substrate and the second substrate; the at least one chip is electrically connected to the first substrate and the second substrate (See Fig 7 and 1) [0030, 0035]
Liang does not disclose: and the thermal conductive layer is disposed between the heat sink and the first substrate and/or between the heat sink and the second substrate.
However, Cola in a similar device teaches in Fig 11: a thermal conductive layer (30), wherein the thermal conductive layer is located between the heat sink (HEAT SINK) and the semiconductor package (CPU).
References Liang and Cola are analogous art because they both are directed to thermal management of semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Liang with the specified features of Cola because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Liang and Cola so that the thermal conductive layer is disposed between the heat sink and the first substrate and/or between the heat sink and the second substrate as taught by Cola in Liang’s device since this provides a solution to the reliability and functionality issues faced at electrical interfaces.
Regarding Claim 9, Liang and Cola disclose: The power semiconductor module according to claim 8, Liang further discloses in Fig 1, 7 and 13: wherein the chip comprises an insulated gate bipolar transistor chip and a diode chip; or the chip comprises a silicon metal-oxide-semiconductor field-effect transistor or a silicon carbide metal-oxide-semiconductor field-effect transistor [0005].
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hirata et al (US 20200212819 A1 hereinafter Hirata) in view of Liang (US 2016/0351468 A1 hereinafter Liang) and further in view of Cola et al (US 8919428 B2 hereinafter Cola).
Regarding Claim 17, Hirata discloses in Fig 3: A motor driver, comprising a capacitor and a power semiconductor module, wherein an electrode terminal of the power semiconductor module is electrically connected to the capacitor [0033].
Hirata does not disclose: wherein the power semiconductor module comprises at least one heat sink and at least one power semiconductor package, and a thermal conductive layer, wherein: the thermal conductive layer is located between the heat sink and the power semiconductor package, and the thermal conductive layer is a thermal conductive material having metal bonding wires on a surface or a solid-state thermal conductive layer formed by curable silicone grease; and both the power semiconductor package and the heat sink are combined with the thermal conductive layer to form the power semiconductor module.
However, Liang in a similar device teaches in Fig 13: the power semiconductor module, comprising: at least one heat sink (50);
at least one power semiconductor package (power package); and both the power semiconductor package (power package) and the heat sink (50) are to form the power semiconductor module (54) [0034, 0045-0047].
References Hirata, Liang are analogous art because they both are directed to thermal management of semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Hirata with the specified features of Liang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Hirata, Liang so that wherein the power semiconductor module comprises at least one heat sink and at least one power semiconductor package as taught by Liang in Hirata’s device since this provides enhancements in performance parameters, leading to huge improvements in cost reduction, power density increase, reliability enhancement and cost-effective manufacturability, compared to conventional packaging.
Hirata and Liang do not disclose: a thermal conductive layer, wherein the thermal conductive layer is located between the heat sink and the power semiconductor package, and the thermal conductive layer is a thermal conductive material having metal bonding wires on a surface or a solid-state thermal conductive layer formed by curable silicone grease; and both the power semiconductor package and the heat sink are combined with the thermal conductive layer to form the power semiconductor module.
However, Cola in a similar device teaches in Fig 11: a thermal conductive layer (30), wherein the thermal conductive layer is located between the heat sink (HEAT SINK) and the semiconductor package (CPU), and the thermal conductive layer is a thermal conductive material having metal bonding wires (MWCNT) on a surface (See Fig 11) or a solid-state thermal conductive layer formed by curable silicone grease; and both the power semiconductor package and the heat sink are combined with the thermal conductive layer to form the power semiconductor module (taught by the combined device of Liang and Cola).
References Hirata, Liang and Cola are analogous art because they both are directed to thermal management of semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Liang and Hirata with the specified features of Cola because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Hirata, Liang and Cola so that the thermal conductive layer is located between the heat sink and the power semiconductor package, and the thermal conductive layer is a thermal conductive material having metal bonding wires on a surface or a solid-state thermal conductive layer formed by curable silicone grease; and both the power semiconductor package and the heat sink are combined with the thermal conductive layer to form the power semiconductor module as taught by Cola in Liang’s and Hirata’s device since this provides a solution to the reliability and functionality issues faced at electrical interfaces.
Allowable Subject Matter
Claims 10-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 10, the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “wherein the power semiconductor package further comprises: at least one conductive pad, and the conductive pad is located between the chip and the first substrate; and two ends of the conductive pad are respectively connected to the chip and the first substrate by using conductive connecting layers” as recited in claim 10 in combination with the remaining features.
Dependent claims 11-16 are indicated as containing allowable subject matter based on virtue of their dependencies
The most relevant prior art references, (US 2016/0351468 A1 to Liang, Zhenxian in Figs 13 and US 2011/0316143 A1 to Noritake et al. in Fig 1 substantially teach the limitations of the claim 10, with the exception of the limitations described in the preceding paragraph.
Claims 18-20 are allowed.
The following is an examiner’s statement of reasons for allowance: With respect to claim 18, the primary reason for allowance is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “separately disposing an interface material on a top surface and/or a bottom surface of the power semiconductor package, wherein the interface material is a thermal conductive material having metal bonding wires on a surface, or the interface material is curable silicone grease; and press-fitting, for preset time at a preset temperature and preset pressure, the power semiconductor package on which the interface material is disposed with the heat sink, to form the power semiconductor module.” as recited in claim 18 in combination with the remaining features.
Dependent claims 19-20 are allowed based on virtue of their dependencies
The most relevant prior art references, (US 2016/0351468 A1 to Liang, Zhenxian in Figs 13 and US 2011/0316143 A1 to Noritake et al. in Fig 1 substantially teach the limitations of the claim 18, with the exception of the limitations described in the preceding paragraph.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/NISHATH YASMEEN/Primary Examiner, Art Unit 2811