DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species C in the reply filed on 23 December 2025 is acknowledged. The traversal is on the ground(s) that claims 1-30 are each generic among the Species or directed to the subject matter of Species C. Applicant’s arguments on pp. 8-9 have been fully considered and are persuasive. The restriction requirement has been withdrawn.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 10-18, 20-24 and 26-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. US 2021/0098421 in view of Lin et al. US 7,858,441.
Regarding claim 1, Wu et al. in Fig. 11B discloses a stacked integrated circuit (IC) device 80 comprising:
a first die 200A” having a first face, a first active region adjacent to the first face, first circuitry disposed in the first active region, and first die-interconnect contacts 208a disposed on the first face and electrically connected to the first circuitry [0097]-[0105];
a second die 330A having a second face, a second active region adjacent to the second face, second circuitry disposed in the second active region, and second die-interconnect contacts 134 disposed on the second face and electrically connected to the second circuitry, wherein the first face is oriented toward the second face, and wherein the first die-interconnect contacts 208a are electrically connected to the second die-interconnect contacts 134 [0097]-[0105];
a set of redistribution layers 150 electrically connected to redistribution contacts on the first face 208b, the second face, or both and
interconnect conductors 120 external to the second die 330A and electrically connected to the redistribution layers 150 [0097]-[0105].
Wu et al. does not expressly disclose interconnect conductors 120 external to the first die and electrically connected to the redistribution layers 150 to provide signal paths from the first die 200A”, second die or both, to a set of external contacts 300.
However, Lin et al. in Fig. 7 teaches a semiconductor package 500 including metal posts 530 and 550 electrically connected to a redistribution layer col. 14, lines 50-55 to provide in-package interconnection and next-level interconnection.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lin et al. in the device of Wu et al. for the purpose of providing in-package interconnection and next-level interconnection as taught in col. 14, lines 50-55.
Wu et al. in view of Lin et al. does not expressly teach “to provide signal paths from the first die, the second die or both, to a set of external contacts”.
However, the claim limitation “to provide signal paths from the first die, the second die or both, to a set of external contacts”, is drawn to a method of use or a device under test. The intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art.
If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey,152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). In this case the structure is capable of performing this use.
Regarding claim 2, Wu et al. in view of Lin et al. teaches the stacked IC device of claim 1. Wu et al. in Fig. 11B teaches the stacked IC device of claim 1, further comprising a substrate 110, wherein a back of the second die 330A is coupled to a first side of the substrate 110 and the external contacts 300 are coupled to a second side of the substrate 110, and wherein the back of the second die is opposite the second face [0097]-[0105].
Regarding claim 3, Wu et al. in view of Lin et al. teaches the stacked IC device of claim 1. Wu et al. in Fig. 11B teaches wherein the first die 200A” and the second die 330A are devoid of through-silicon vias.
Regarding claim 4, Wu et al. in view of Lin et al. teaches the stacked IC device of claim 1. Wu et al. in Fig. 11B teaches wherein the first die 200A” further comprises a first back and a first inactive region adjacent to the first back, and wherein the first back is devoid of electrical contacts.
Regarding claim 5, Wu et al. in view of Lin et al. teaches the stacked IC device of claim 1. Wu et al. in Fig. 11B teaches wherein the second die further comprises a second back and a second inactive region adjacent to the second back, and wherein the second back is devoid of electrical contacts.
Regarding claim 6, Wu et al. in view of Lin et al. teaches the stacked IC device of claim 1. Wu et al. in [0096]-[0103] teaches wherein the first circuitry includes one or more first transistors and the second circuitry includes one or more second transistors, and wherein the one or more first transistors are electrically connected to the one or more second transistors through the first die-interconnect contacts and the second die-interconnect contacts.
Regarding claim 10, Wu et al. in view of Lin et al. teaches the stacked IC device of claim 1. Wu et al. in Fig. 11B teaches the stacked IC device of claim 1, further comprising mold compound 140, 210 at least partially encapsulating the first die 200A”, the second die 330A, the redistribution layers 150, and the interconnect conductors 120.
Regarding claim 11, Wu et al. in view of Lin et al. teaches the stacked IC device of claim 1. Wu et al. in Fig. 11B teaches wherein at least one of the interconnect conductors 120 includes a through-mold 140 via Fig. 1C.
Regarding claim 12, Wu et al. in view of Lin et al. teaches the stacked IC device of claim 1. Wu et al. in Fig. 11B teaches further comprising at least one additional device 200B, 200C” disposed adjacent to the first die 200A” and electrically connected to the first circuitry, the second circuitry, or both, through the redistribution layers 150.
Regarding claim 13, Wu et al. in view of Lin et al. teaches the stacked IC device of claim 1. Wu et al. in Fig. 11B teaches the stacked IC device of claim 1 further comprising at least one additional device 330A disposed adjacent to the second die 330A and electrically connected to the first circuitry, the second circuitry, or both, through the interconnect conductors 120 and the redistribution layer 150.
Regarding claim 14, Wu et al. in view of Lin et al. teaches the stacked IC device of claim 1. Lin et al. in Fig. 7 teaches the stacked IC device of claim 1 further comprising at least one additional device 564 and second interconnect conductors 530, 550, wherein the first die is disposed between the at least one additional device and the redistribution layers, and wherein additional circuitry of the at least one additional device is electrically connected to the first circuitry, the second circuitry, or both, through the second interconnect conductors and the redistribution layers.
Regarding claim 15, Wu et al. in view of Lin et al. teaches the stacked IC device of claim 1. Wu et al. in view of Lin et al. does not expressly teach “wherein the first die is a first chiplet and the second die is a second chiplet designed to operate in conjunction with the first chiplet.”
However, the claim limitation “wherein the first die is a first chiplet and the second die is a second chiplet designed to operate in conjunction with the first chiplet”, is drawn to a method of use or a device under test. The intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art.
If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey,152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). In this case the structure is capable of performing this use.
Regarding claim 16, Wu et al. in view of Lin et al. teaches the stacked IC device of claim 15. Wu et al. in [0030] teaches that semiconductor die 130(330) includes passive devices, transistors, resistors, capacitors, inductors, etc.. and [0051] teaches that 130(330) includes decoupling capacitors for filtering the noise on power supply lines. Wu et al. further teaches in [0098] devices 200A”, 200B and 200C” that include a single function such as, a logic die, memory die, or multiple functions such as a system-on-chip. Semiconductor die 330 provides shorter electrical connection paths among 200A”, 200B and 200C”.
Therefore one of ordinary skill in the art before the effective filing date of the claimed invention would recognize that the first circuitry includes one or more first functional circuit blocks and the second circuitry includes one or more second functional circuit blocks, and wherein the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent upon one another.
Regarding claim 17, Wu et al. in Fig. 11B discloses a method comprising:
electrically connecting a first die 200A” face-to-face with a second die 330A using first die-interconnect contacts 208a disposed on a first face of the first die 200A” and second die-interconnect contacts 134 disposed on a second face of the second die 330A, wherein a face of a die corresponds to a surface of the die bounding an active region of the die, and wherein the active region includes circuitry;
forming a set of redistribution layers 150 electrically connected to redistribution contacts on the first face 208b, the second face, or both and
forming interconnect conductors 120 external to the second die 330A and electrically connected to the redistribution layers 150.
Wu et al. does not expressly disclose interconnect conductors 120 external to the first die and electrically connected to the redistribution layers 150 to provide signal paths from the first die 200A”, second die or both, to a set of external contacts 300.
However, Lin et al. in Fig. 7 teaches a method of forming a semiconductor package 500 including metal posts 530 and 550 electrically connected to a redistribution layer col. 14, lines 50-55 to provide in-package interconnection and next-level interconnection.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lin et al. in the device of Wu et al. for the purpose of providing in-package interconnection and next-level interconnection.
Wu et al. in view of Lin et al. does not expressly teach “to provide signal paths from the first die, the second die or both, to a set of external contacts”.
However, the claim limitation “to provide signal paths from the first die, the second die or both, to a set of external contacts”, is drawn to a method of use or a device under test. The intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art.
If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey,152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). In this case the structure is capable of performing this use.
Regarding claim 18, Wu et al. in view of Lin et al. teaches the method of claim 17. Wu et al. in Fig. 11B teaches the method of claim 17, further comprising coupling a back of the second die 330A to a first side of a substrate 110, wherein the external contacts 300 are coupled to a second side of the substrate 110, and wherein the back of the second die 330A is opposite the second face.
Regarding claim 20, Wu et al. in view of Lin et al. teaches the method of claim 17. Wu et al. in Fig. 11B teaches the method of claim 17 further comprising at least partially encapsulating the first die, the second die, the redistribution layers, and the interconnect conductors in a mold compound 210, 140.
Regarding claim 21, Wu et al. in view of Lin et al. teaches the method of claim 20. Wu et al. in Fig. 11B teaches the method of claim 17 further comprising forming one or more through-mold vias 120, wherein at least one of the interconnect conductors 120 includes a through-mold via Fig. 1C.
Regarding claim 22, Wu et al. in view of Lin et al. teaches the method of claim 20. Wu et al. in Fig. 11B teaches the method of claim 17 further comprising electrically connecting at least one additional device 200B, 200C, 330A to first circuitry of the first die, second circuitry of the second die, or both, through the redistribution layers 150.
Regarding claim 23, Wu et al. in Fig. 11B discloses a device comprising:
a substrate 110 having a set of external contacts 300 on a second side; and
a stacked integrated circuit (IC) device 80 on a first side of the substrate 110, the stacked IC device comprising:
a first die 200A” having a first face, a first active region adjacent to the first face, first circuitry disposed in the first active region, and first die-interconnect contacts 208a disposed on the first face and electrically connected to the first circuitry;
a second die 330A having a second face, a second active region adjacent to the second face, second circuitry disposed in the second active region, and second die-interconnect contacts 134 disposed on the second face and electrically connected to the second circuitry, wherein the first face is oriented toward the second face, and wherein the first die-interconnect contacts 208a are electrically connected to the second die-interconnect contacts 134;
a set of redistribution layers 150 electrically connected to redistribution contacts on the first face 208b, the second face, or both and
interconnect conductors 120 external to the second die 330A and electrically connected to the redistribution layers 150.
Wu et al. does not expressly disclose interconnect conductors 120 external to the first die and electrically connected to the redistribution layers 150 to provide signal paths from the first die 200A”, second die or both, to a set of external contacts 300.
However, Lin et al. in Fig. 7 teaches a semiconductor package 500 including metal posts 530 and 550 electrically connected to a redistribution layer col. 14, lines 50-55 to provide in-package interconnection and next-level interconnection.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lin et al. in the device of Wu et al. for the purpose of providing in-package interconnection and next-level interconnection.
Wu et al. in view of Lin et al. does not expressly teach “to provide signal paths from the first die, the second die or both, to a set of external contacts”.
However, the claim limitation “to provide signal paths from the first die, the second die or both, to a set of external contacts”, is drawn to a method of use or a device under test. The intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art.
If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey,152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). In this case the structure is capable of performing this use.
Regarding claim 24, Wu et al. in view of Lin et al. teaches the device of claim 23. Wu et al. in Fig. 11B teaches wherein a back of the second die 330A is coupled to the first side of the substrate 110, and wherein the back of the second die 330A is opposite the second face.
Regarding claim 26, Wu et al. in view of Lin et al. teaches the device of claim 23. Wu et al. in Fig. 11B teaches wherein the stacked IC device further comprises mold compound 140, 210 at least partially encapsulating the first die, the second die, the redistribution layers, and the interconnect conductors.
Regarding claim 27, Wu et al. in view of Lin et al. teaches the device of claim 26. Wu et al. in Fig. 11B teaches wherein at least one of the interconnect conductors 120 includes a through-mold via Fig. 1C.
Regarding claim 28, Wu et al. in view of Lin et al. teaches the device of claim 23. Wu et al. in Fig. 11B teaches wherein the stacked IC device further comprises at least one additional device 200B, 200C” disposed adjacent to the first die 200A” and electrically connected to the first circuitry, the second circuitry, or both, through the redistribution layers 150.
Regarding claim 29, Wu et al. in view of Lin et al. teaches the device of claim 23. Wu et al. in Fig. 11B teaches wherein the stacked IC device further comprises at least one additional device 330A disposed adjacent to the second die 330A and electrically connected to the first circuitry, the second circuitry, or both, through the interconnect conductors 120 and the redistribution layer 150.
Regarding claim 30, Wu et al. in view of Lin et al. teaches the device of claim 23. Lin et al. in Fig. 7 teaches the stacked IC device further comprising at least one additional device 564 and second interconnect conductors 530, 550, wherein the first die is disposed between the at least one additional device and the redistribution layers, and wherein additional circuitry of the at least one additional device is electrically connected to the first circuitry, the second circuitry, or both, through the second interconnect conductors and the redistribution layers.
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. and Lin et al. as applied to claim 1 above, and further in view of Ong et al. US 2022/0278084.
Regarding claim 7, Wu et al. in view of Lin et al. teaches the stacked IC device of claim 1. Wu et al. in view of Lin et al. does not expressly disclose the stacked IC device of claim 1 further comprising at least one first integrated capacitor device (ICD) disposed between the first face and the set of external contacts and electrically connected to a power distribution network (PDN) of the first die.
Wu et al. in [0030] teaches that semiconductor die 130(330) includes passive devices, transistors, resistors, capacitors, inductors, etc.. and [0051] teaches that 130(330) includes decoupling capacitors for filtering the noise on power supply lines. Wu et al. further teaches in [0098] devices 200A”, 200B and 200C” that include a single function such as, a logic die, memory die, or multiple functions such as a system-on-chip. Semiconductor die 330 provides shorter electrical connection paths among 200A”, 200B and 200C”.
Ong et al. in Fig. 1A and [0016]-[0018] teaches an IC package substrate with reduced package inductance looping. The power integrity of the electrical performance is achieved by including decoupling capacitors embedded in molded interconnects bridges in the die side of the substrate directly coupled to the power delivery networks.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Ong et al. in the device of Wu et al. and Lin et al. for the purpose of enhancing the device performance.
Regarding claim 8, Wu et al. in view of Lin et al. teaches the stacked IC device of claim 1. Wu et al. in view of Lin et al. does not expressly disclose the stacked IC device of claim 1 further comprising at least one second ICD disposed adjacent to the first die and electrically connected to a PDN of the second die.
Wu et al. in [0030] teaches that semiconductor die 130(330) includes passive devices, transistors, resistors, capacitors, inductors, etc.. and [0051] teaches that 130(330) includes decoupling capacitors for filtering the noise on power supply lines. Wu et al. further teaches in [0098] devices 200A”, 200B and 200C” that include a single function such as, a logic die, memory die, or multiple functions such as a system-on-chip. Semiconductor die 330 provides shorter electrical connection paths among 200A”, 200B and 200C”.
Ong et al. in Fig. 1A and [0016]-[0018] teaches an IC package substrate with reduced package inductance looping. The power integrity of the electrical performance is achieved by including decoupling capacitors embedded in molded interconnects bridges in the die side of the substrate directly coupled to the power delivery networks.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Ong et al. in the device of Wu et al. and Lin et al. for the purpose of enhancing the device performance.
Claim(s) 9, 19 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. and Lin et al. as applied to claims 1, 17 and 23 above, and further in view of Kim et al. US 2020/0043853.
Regarding claim 9, Wu et al. in view of Lin et al. teaches the stacked IC device of claim 1 but does not expressly teach the stacked IC device of claim 1 further comprising an interposer device comprising a plurality of conductive vias electrically connected to the redistribution layers and to a plurality of the external contacts.
Kim et al. teaches a highly integrated semiconductor package 1 including an interposer device 230 comprising a plurality of conductive vias 236 for interconnecting a plurality of semiconductor chips to each other, Fig. 1A at a lower manufacturing cost.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kim et al. in the device of Wu et al. and Lin et al. for the purpose of interconnecting a plurality of chips at a lower manufacturing cost.
Regarding claim 19, Wu et al. in view of Lin et al. teaches the method of claim 17, but does not expressly teach the method of claim 17 further comprising electrically connecting an interposer device to the redistribution layers and to a plurality of the external contacts, wherein the interposer device comprises a plurality of conductive vias. Kim et al. teaches a highly integrated semiconductor package 1 and method of making such device including an interposer device 230 comprising a plurality of conductive vias 236 for interconnecting a plurality of semiconductor chips to each other, Fig. 1A at a lower manufacturing cost.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kim et al. in the method and device of Wu et al. and Lin et al. for the purpose of interconnecting a plurality of chips at a lower manufacturing cost.
Regarding claim 25, Wu et al. in view of Lin et al. teaches the device of claim 23 but does not expressly teach the stacked IC device of claim 23 further comprising an interposer device comprising a plurality of conductive vias electrically connected to the redistribution layers and to a plurality of the external contacts.
Kim et al. teaches a highly integrated semiconductor package 1 including an interposer device 230 comprising a plurality of conductive vias 236 for interconnecting a plurality of semiconductor chips to each other, Fig. 1A at a lower manufacturing cost.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kim et al. in the device of Wu et al. and Lin et al. for the purpose of interconnecting a plurality of chips at a lower manufacturing cost.
Conclusion
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/Sonya McCall-Shepard/ Primary Examiner, Art Unit 2898