DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1, 3-12, and 14-23 are pending. Claims 1, 12, and 18 have been amended as per Applicants' request. Claims 21-23 have been added as per Applicants' request.
Papers Submitted
It is hereby acknowledged that the following papers have been received and placed of record in the file:
Amended Claims as filed on March 04, 2026
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 17, 2026 is/are in compliance with the provisional of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 4-12, and 15-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6, 9 and 10 of U.S. Patent No. 11,733,873 in view of KIM et al. (US 2018/0285197) and Kankani et al. (US 2016/0342344). See chart below.
Current Application
US 11,733,873
1. A device, comprising:
a set of non-volatile memory units of different types,
a controller configured to:
access the memory units using an address map that maps logical addresses to physical addresses of the memory units;
track degrees of wear of the memory units based on a normalized degree of wear for each of the memory units of different types having different program erase budgets based on the different memory types; and
adjust the address map based at least in part on the normalized degree of wear for at least one of the memory units.
wherein the non-volatile memory units of different types comprises at least three different memory types each having different program erase budgets corresponding to the different types respectively;
that the different types of memory used for normalization is “at least three different memory types”
wherein the address map further comprises, associated with each of the physical addresses, a memory type and a program/erase cycle count;
1. A solid state drive, comprising:
a set of non-volatile memory units of different types that have different program erase budgets corresponding to the different types respectively; and
a controller;
generate an address map mapping logical addresses to physical addresses of the memory units of the different types;
(Claim 3) the controller to: receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit;
track degrees of wear of the memory units, wherein the degrees of wear are normalized to account for differences in the program erase budgets corresponding to the different types, wherein the degrees of wear are normalized using a largest one of the program erase budgets; and
adjust the address map based at least in part on the program erase budgets to level wear across the memory units of the different types;
wherein the degrees of wear are normalized to account for differences in the program erase budgets corresponding to the different types, wherein the degrees of wear are normalized using a largest one of the program erase budgets;
(claim 1) a set of non-volatile memory units of different types that have different program erase budgets corresponding to the different types respectively; and
(KIM et al.) “Memory cells included in the respective memory blocks 0 to N-1 may be one or more of a single level cell (SLC) storing 1-bit data, a multi-level cell (MLC) storing 2-bit data, an MLC storing 3-bit data also referred to as a triple level cell (TLC), an MLC storing 4-bit data also referred to as a quadruple level cell (QLC), or an MLC storing 5-bit or more bit data” (Kim [0051])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the use of multiple types of memory cells in Kim with the memory system in US 11,733,873. The motivation for doing so would be to balancing performance, endurance and cost of the memory.
“In some embodiments, each mapping record in the reverse mapping table stores the following information and data structures, or a subset or superset thereof: mapping information (e.g., mapping information 304-a(1)) that identifies one or more logical addresses in a logical address space (e.g., an LBA) that is mapped to one or more physical addresses associated with the mapping record; encoding format (e.g., encoding format 304-a(2)) information about a currently-configured encoding format (e.g., SLC, MLC, or TLC) for one or more non-volatile memory portions corresponding to the one or more physical addresses associated with the mapping record; a current endurance metric (e.g., current endurance metric 304-a(3)) that reflects estimated endurance (e.g., estimated number of P/E cycles remaining, or estimated number of write operations remaining) at the currently-configured encoding format for the one or more non-volatile memory portions corresponding to the one or more physical addresses associated with the mapping record” (Kankani [0093-0096])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the information of memory type and program/erase cycle count disclosed in Kankani with the mapping information in the combination of Sutardja and Kim. The motivation for doing so would be improve the efficiency and reliability of the flash memory.
4. The device of claim 1, wherein the normalized degree of wear accounts for differences in the program erase budgets corresponding to the different types.
(Claim 1) wherein the degrees of wear are normalized to account for differences in the program erase budgets corresponding to the different types
5. The device of claim 1, wherein the degrees of wear are normalized using a largest one of the program erase budgets corresponding to the different types.
(Claim 1) wherein the degrees of wear are normalized using a largest one of the program erase budgets;
6. The device of claim 1, wherein the controller is further configured to track the degrees of wear by tracking numbers of normalized program erase cycles of the memory units, wherein the numbers of normalized program erase cycles of the memory units are proportional to a number of actual program erase cycles of the memory units and inversely proportional to program erase budgets of the memory units.
(Claim 1) track numbers of normalized program erase cycles of the memory units, wherein the numbers of normalized program erase cycles of the memory units are proportional to number of actual program erase cycles of the memory units and inversely proportional to program erase budgets of the memory units.
7. The device of claim 1, wherein the non-volatile memory units of different types comprise at least two of:
single level cell flash memory;
multi level cell flash memory;
triple level cell flash memory; and
quad level cell flash memory.
2. The solid state drive of claim 1, wherein the types of the memory units include at least two of:
single level cell flash memory;
multi level cell flash memory;
triple level cell flash memory; and
quad level cell flash memory.
8. The device of claim 1, wherein the controller is further configured to:
receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit; and
identify, based on the normalized degree of wear for at least two of the memory units, a second memory unit having less wear than the first memory unit.
3. The solid state drive of claim 1, wherein the instructions are further configured to instruct the controller to:
receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit;
identify a second memory unit having less wear than the first memory unit;
9. The device of claim 8, wherein the controller is further configured to:
change the address map to map the logical address to the second memory unit; and
write the data in the second memory unit.
(Claim 3)
change the address map to map the logical address to the second memory unit; and
write the data in the second memory unit.
10. The device of claim 9, wherein the first memory unit and the second memory unit are of different types.
4. The solid state drive of claim 3, wherein the first memory unit and the second memory unit are of different types.
11. The device of claim 9, wherein the first memory unit and the second memory unit have different program erase budgets.
5. The solid state drive of claim 3, wherein the first memory unit and the second memory unit have different program erase budgets.
12. A non-transitory computer storage medium storing instructions thereon which, upon execution by a controller of a memory device, cause the memory device to:
access memory units using an address map that maps logical addresses to physical addresses of the memory units,
wherein the memory units comprise a set of memory units of different types;
track degrees of wear of the memory units based on a normalized degree of wear for each of the memory units of different types having different program erase budgets based on the different memory types;
adjust the address map based at least in part on the normalized degree of wear for at least one of the memory units.
wherein the memory units of different types comprises at least three different memory types each having different program erase budgets corresponding to the different types respectively; and
that the different types of memory used for normalization is “at least three different memory types”
wherein the address map further comprises, associated with each of the physical addresses, a memory type and a program/erase cycle count;
1. A solid state drive, comprising:
generate an address map mapping logical addresses to physical addresses of the memory units of the different types;
(Claim 3) the controller to: receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit;
a set of non-volatile memory units of different types that have different program erase budgets corresponding to the different types respectively; and
track degrees of wear of the memory units, wherein the degrees of wear are normalized to account for differences in the program erase budgets corresponding to the different types, wherein the degrees of wear are normalized using a largest one of the program erase budgets; and
adjust the address map based at least in part on the program erase budgets to level wear across the memory units of the different types;
wherein the degrees of wear are normalized according to the program erase budgets corresponding to the different types, wherein the degrees of wear are normalized using a largest one of the program erase budgets;
(claim 1) a set of non-volatile memory units of different types that have different program erase budgets corresponding to the different types respectively; and
(KIM et al.) “Memory cells included in the respective memory blocks 0 to N-1 may be one or more of a single level cell (SLC) storing 1-bit data, a multi-level cell (MLC) storing 2-bit data, an MLC storing 3-bit data also referred to as a triple level cell (TLC), an MLC storing 4-bit data also referred to as a quadruple level cell (QLC), or an MLC storing 5-bit or more bit data” (Kim [0051])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the use of multiple types of memory cells in Kim with the memory system in US 11,733,873. The motivation for doing so would be to balancing performance, endurance and cost of the memory.
“In some embodiments, each mapping record in the reverse mapping table stores the following information and data structures, or a subset or superset thereof: mapping information (e.g., mapping information 304-a(1)) that identifies one or more logical addresses in a logical address space (e.g., an LBA) that is mapped to one or more physical addresses associated with the mapping record; encoding format (e.g., encoding format 304-a(2)) information about a currently-configured encoding format (e.g., SLC, MLC, or TLC) for one or more non-volatile memory portions corresponding to the one or more physical addresses associated with the mapping record; a current endurance metric (e.g., current endurance metric 304-a(3)) that reflects estimated endurance (e.g., estimated number of P/E cycles remaining, or estimated number of write operations remaining) at the currently-configured encoding format for the one or more non-volatile memory portions corresponding to the one or more physical addresses associated with the mapping record” (Kankani [0093-0096])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the information of memory type and program/erase cycle count disclosed in Kankani with the mapping information in the combination of Sutardja and Kim. The motivation for doing so would be improve the efficiency and reliability of the flash memory.
15. The non-transitory computer storage medium of claim 12, wherein the instructions further cause the memory device to:
receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit;
identify, based on the normalized degree of wear for at least two of the memory units, a second memory unit having less wear than the first memory unit;
receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit; and
identify, based on the normalized degree of wear for at least two of the memory units, a second memory unit having less wear than the first memory unit.
3. The solid state drive of claim 1, wherein the instructions are further configured to instruct the controller to:
receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit;
identify a second memory unit having less wear than the first memory unit;
receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit;
identify a second memory unit having less wear than the first memory unit;
16. The non-transitory computer storage medium of claim 12, wherein the degrees of wear are normalized using a largest one of the program erase budgets corresponding to the different types.
(Claim 1) wherein the degrees of wear are normalized using a largest one of the program erase budgets;
17. The non-transitory computer storage medium of claim 12, wherein the memory units of different types comprise at least two of:
single level cell non-volatile flash memory;
multi level cell non-volatile flash memory;
triple level cell non-volatile flash memory; and
quad level cell non-volatile flash memory.
2. The solid state drive of claim 1, wherein the types of the memory units include at least two of:
single level cell flash memory;
multi level cell flash memory;
triple level cell flash memory; and
quad level cell flash memory.
18. A method comprising:
accessing, by a controller of a memory device, memory units using an address map that maps logical addresses to physical addresses of the memory units,
wherein the memory units comprise a set of memory units;
tracking, by the controller, degrees of wear of the memory units based on a normalized degree of wear for each of the memory units having different program erase budgets based on the different types respectively; and
adjusting, by the controller, the address map based at least in part on the normalized degree of wear for at least one of the memory units.
wherein the set of memory units comprises at least three different memory types each having different program erase budgets corresponding to the different types respectively; and
that the different types of memory used for normalization is “at least three different memory types”
wherein the address map further comprises, associated with each of the physical addresses, a memory type and a program/erase cycle count;
6. A method implemented in a solid state drive, the method comprising:
generating an address map mapping logical addresses to physical addresses of the memory units of the different types;
(Claim 8) receiving a request to write data in a logical address that is currently mapped by the address map to a first memory unit
providing a set of non-volatile memory units of different types that have different program erase budgets corresponding to the different types respectively;
tracking data indicating degrees of wear of the memory units, wherein the degrees of wear are normalized according to the program erase budgets corresponding to the different types, wherein the degrees of wear are normalized using a largest one of the program erase budgets; and
adjusting the address map based at least in part on the program erase budgets to level wear across the memory units of the different types;
wherein the degrees of wear are normalized according to the program erase budgets corresponding to the different types, wherein the degrees of wear are normalized using a largest one of the program erase budgets;
(claim 1) providing a set of non-volatile memory units of different types that have different program erase budgets corresponding to the different types respectively;
(KIM et al.) “Memory cells included in the respective memory blocks 0 to N-1 may be one or more of a single level cell (SLC) storing 1-bit data, a multi-level cell (MLC) storing 2-bit data, an MLC storing 3-bit data also referred to as a triple level cell (TLC), an MLC storing 4-bit data also referred to as a quadruple level cell (QLC), or an MLC storing 5-bit or more bit data” (Kim [0051])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the use of multiple types of memory cells in Kim with the memory system in US 11,733,873. The motivation for doing so would be to balancing performance, endurance and cost of the memory.
“In some embodiments, each mapping record in the reverse mapping table stores the following information and data structures, or a subset or superset thereof: mapping information (e.g., mapping information 304-a(1)) that identifies one or more logical addresses in a logical address space (e.g., an LBA) that is mapped to one or more physical addresses associated with the mapping record; encoding format (e.g., encoding format 304-a(2)) information about a currently-configured encoding format (e.g., SLC, MLC, or TLC) for one or more non-volatile memory portions corresponding to the one or more physical addresses associated with the mapping record; a current endurance metric (e.g., current endurance metric 304-a(3)) that reflects estimated endurance (e.g., estimated number of P/E cycles remaining, or estimated number of write operations remaining) at the currently-configured encoding format for the one or more non-volatile memory portions corresponding to the one or more physical addresses associated with the mapping record” (Kankani [0093-0096])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the information of memory type and program/erase cycle count disclosed in Kankani with the mapping information in the combination of Sutardja and Kim. The motivation for doing so would be improve the efficiency and reliability of the flash memory.
19. The method of claim 18, wherein the degrees of wear are normalized using a largest one of the program erase budgets of the memory units.
(Claim 6) wherein the degrees of wear are normalized using a largest one of the program erase budgets; and
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-12, and 14-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sutardja (US 2008/0140918) (hereinafter Sutardja) (published June 12, 2008) in view of KIM et al. (US 2018/0285197) (hereinafter Kim) (filed November 15, 2017) and Kankani et al. (US 2016/0342344) (hereinafter Kankani) (published November 24, 2015).
Regarding Claims 1, 12, and 18, taking claim 1 as exemplary, Sutardja discloses a device, comprising: a set of non-volatile memory units of different types,
“The first solid-state nonvolatile memory 204 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory. The second solid-state nonvolatile memory 206 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory” (Sutardja [0108])
a controller configured to:
“A solid-state disk 450 may include a controller 460, a first solid-state nonvolatile memory 462, and a second solid-state nonvolatile memory 464” (Sutardja [0141])
access the memory units using an address map that maps logical addresses to physical addresses of the memory units,
“The controller 460 may include the wear leveling module 260 and a mapping module 465. The wear leveling module 260 may also implement the mapping module. The mapping module 465 may map the logical addresses to the physical addresses of one of the first and second solid-state nonvolatile memory 462, 464 based on access times and/or storage capacities of the first and second solid-state nonvolatile memory 462, 464” (Sutardja [0142])
track degrees of wear of the memory units based on a normalized degree of wear for each of the memory units of different types having different program erase budgets based on the different memory types; and
“The first solid-state nonvolatile memory 204 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory. The second solid-state nonvolatile memory 206 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory” (Sutardja [0108])
“The wear leveling module 260 may use a normalized version of the write and/or erase cycle counts. For example, the number of write cycles performed on a block in the first solid-state nonvolatile memory 204 may be divided by the total number of write cycles that a block in the first solid-state nonvolatile memory 204 can endure” (Sutardja [0122])
“For example only, the first memory have a write cycle lifetime of 10,000, while the second memory has a write cycle lifetime of 100,000” (Sutardja [0161] SLC would have more write cycle lifetime than MLC)
adjust the address map based at least in part on the normalized degree of wear for at least one of the memory units.
“The wear leveling module 260 may use a normalized version of the write and/or erase cycle counts” (Sutardja [0122])
“At various times, such as periodically, the wear leveling module may analyze the wear levels of the blocks, and remap relatively frequently rewritten logical addresses to blocks with low wear levels. In addition, the wear leveling module may remap relatively infrequently rewritten logical addresses to blocks with high wear levels, which is known as static data shifting” (Sutardja [0167])
But does not explicitly state wherein the non-volatile memory units of different types comprises at least three different memory types each having different program erase budgets corresponding to the different types respectively; and that the different types of memory used for normalization is “at least three different memory types”, and wherein the address map further comprises, associated with each of the physical addresses, a memory type and a program/erase cycle count.
Kim and Sutardja discloses wherein the non-volatile memory units of different types comprises at least three different memory types each having different program erase budgets corresponding to the different types respectively; and that the different types of memory used for normalization is “at least three different memory types”.
“Memory cells included in the respective memory blocks 0 to N-1 may be one or more of a single level cell (SLC) storing 1-bit data, a multi-level cell (MLC) storing 2-bit data, an MLC storing 3-bit data also referred to as a triple level cell (TLC), an MLC storing 4-bit data also referred to as a quadruple level cell (QLC), or an MLC storing 5-bit or more bit data” (Kim [0051] SLC, MLC, TLC, and QLC each would have different program erase budgets)
“For example only, the first memory have a write cycle lifetime of 10,000, while the second memory has a write cycle lifetime of 100,000” (Sutardja [0161] SLC would have more write cycle lifetime than MLC)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the use of multiple types of memory cells in Kim with the memory system in Sutardja. The motivation for doing so would be to balancing performance, endurance and cost of the memory.
Kankani discloses wherein the address map further comprises, associated with each of the physical addresses, a memory type and a program/erase cycle count.
“In some embodiments, each mapping record in the reverse mapping table stores the following information and data structures, or a subset or superset thereof: mapping information (e.g., mapping information 304-a(1)) that identifies one or more logical addresses in a logical address space (e.g., an LBA) that is mapped to one or more physical addresses associated with the mapping record; encoding format (e.g., encoding format 304-a(2)) information about a currently-configured encoding format (e.g., SLC, MLC, or TLC) for one or more non-volatile memory portions corresponding to the one or more physical addresses associated with the mapping record; a current endurance metric (e.g., current endurance metric 304-a(3)) that reflects estimated endurance (e.g., estimated number of P/E cycles remaining, or estimated number of write operations remaining) at the currently-configured encoding format for the one or more non-volatile memory portions corresponding to the one or more physical addresses associated with the mapping record” (Kankani [0093-0096])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the information of memory type and program/erase cycle count disclosed in Kankani with the mapping information in the combination of Sutardja and Kim. The motivation for doing so would be improve the efficiency and reliability of the flash memory as described by Kankani. “Since flash memory can only be programmed and erased a limited number of times, the efficiency of the algorithm used to pick the next block(s) to re-write and erase has a significant impact on the lifetime and reliability of flash-based storage systems” (Kankani [0056])
Regarding Claims 3 and 14, Sutardja further discloses wherein the controller is further configured to generate the address map prior to the access of the memory units using the address map.
“When a write request for a logical address arrives at the wear leveling module, the wear leveling module may determine if the logical address is already mapped to a physical address. If so, the wear leveling module may direct the write to that physical address” (Sutardja [0164] the address map is already generated before the request and is used to direct the access to the correct address)
Regarding Claim 4, Sutardja further discloses wherein the normalized degree of wear accounts for differences in the program erase budgets corresponding to the different types.
“The number of erases performed on a block may therefore not be an appropriate comparison between a block from the first memory and a block of the second memory. To achieve appropriate comparisons, the erase counts can be normalized. One way of normalizing is to divide the erase count by the total number of erase counts a block in that memory is expected to be able to withstand. For example only, the first memory have a write cycle lifetime of 10,000, while the second memory has a write cycle lifetime of 100,000” (Sutardja [0161])
Regarding Claims 5, 16, and 19, Sutardja further discloses wherein the degrees of wear are normalized using a largest one of the program erase budgets corresponding to the different types.
“Another way of normalizing, which avoids fractional numbers, is to multiply the erase counts of blocks in the first memory (having the lower write cycle lifetime) by the ratio of write cycle lifetimes. In the current example, the ratio is 10 (100,000/10,000). A block in the first memory that has been erased 1,000 times would then have a normalized wear level of 10,000, while a block in the second memory that has been erased 1,000 times would then have a normalized wear level of 1,000” (Sutardja [0163] the erase budget/write cycle lifetimes of the smaller one is normalized to the higher erase budget write cycle lifetimes)
Regarding Claim 6, Sutardja further discloses wherein the controller is further configured to track the degrees of wear by tracking numbers of normalized program erase cycles of the memory units,
“The wear leveling module 260 may use a normalized version of the write and/or erase cycle counts” (Sutardja [0122])
wherein the numbers of normalized program erase cycles of the memory units are proportional to a number of actual program erase cycles of the memory units and inversely proportional to program erase budgets of the memory units.
“Another way of normalizing, which avoids fractional numbers, is to multiply the erase counts of blocks in the first memory (having the lower write cycle lifetime) by the ratio of write cycle lifetimes. In the current example, the ratio is 10 (100,000/10,000). A block in the first memory that has been erased 1,000 times would then have a normalized wear level of 10,000, while a block in the second memory that has been erased 1,000 times would then have a normalized wear level of 1,000” (Sutardja [0163] it is inherent that the normalized erase cycles are proportional to the number of actual program erase cycle and inversely proportional to program erase budgets of the memory units)
Regarding Claims 7 and 17, Sutardja further discloses wherein the non-volatile memory units of different types comprise at least two of: single level cell flash memory; multi level cell flash memory; triple level cell flash memory; and quad level cell flash memory.
“The first solid-state nonvolatile memory 204 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory. The second solid-state nonvolatile memory 206 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory” (Sutardja [0108])
Regarding Claims 8 and 15, Sutardja further discloses wherein the controller is further configured to: receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit; and
“When a write request for a logical address arrives at the wear leveling module, the wear leveling module may determine if the logical address is already mapped to a physical address. If so, the wear leveling module may direct the write to that physical address” (Sutardja [0164])
identify, based on the normalized degree of wear for at least two of the memory units, a second memory unit having less wear than the first memory unit.
“When the wear leveling module has good data for estimating access frequencies, the wear leveling module may move data from a used block to free that block for an incoming write. In this way, an incoming write to a block that is relatively frequently accessed can be written to a block with a low wear level. Also, an incoming write to a block that is relatively infrequently accessed can be written to a block with a high wear level” (Sutardja [0166])
Regarding Claim 9, Sutardja further discloses wherein the controller is further configured to: change the address map to map the logical address to the second memory unit; and write the data in the second memory unit.
“Control writes data to the first and/or second NVS memories in step 510 according to the mapping generated in steps 506 and 508” (Sutardja [0147])
“When a write request for a logical address arrives at the wear leveling module, the wear leveling module may determine if the logical address is already mapped to a physical address. If so, the wear leveling module may direct the write to that physical address” (Sutardja [0164])
“When the wear leveling module has good data for estimating access frequencies, the wear leveling module may move data from a used block to free that block for an incoming write. In this way, an incoming write to a block that is relatively frequently accessed can be written to a block with a low wear level. Also, an incoming write to a block that is relatively infrequently accessed can be written to a block with a high wear level” (Sutardja [0166] mapping is changed to another physical address that has a lower wear level)
Regarding Claim 10, Sutardja further discloses wherein the first memory unit and the second memory unit are of different types.
“The first solid-state nonvolatile memory 204 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory. The second solid-state nonvolatile memory 206 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory” (Sutardja [0108])
Regarding Claim 11, Sutardja further discloses wherein the first memory unit and the second memory unit have different program erase budgets.
“The first solid-state nonvolatile memory 204 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory. The second solid-state nonvolatile memory 206 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory” (Sutardja [0108])
“For example only, the first memory have a write cycle lifetime of 10,000, while the second memory has a write cycle lifetime of 100,000” (Sutardja [0161] SLC would have more write cycle lifetime than MLC)
Regarding Claim 20, Sutardja further discloses wherein the memory units comprise at least two units of different types, wherein the different types of memory units have different program eras budgets.
“The first solid-state nonvolatile memory 204 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory. The second solid-state nonvolatile memory 206 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory” (Sutardja [0108])
“For example only, the first memory have a write cycle lifetime of 10,000, while the second memory has a write cycle lifetime of 100,000” (Sutardja [0161] SLC would have more write cycle lifetime than MLC)
Regarding Claim 22, Sutardja further discloses wherein the program/erase cycle count is incremented per program/erase cycle of an associated physical address of the physical address of the memory units, and
“With various nonvolatile memories, writing data to a block may require erasing or writing to the entire block. In such a block-centric memory, the wear leveling module may track the number of times that each block has been erased or written” (Sutardja [0111])
further wherein the normalized degree of wear is determined by multiplying the program/erase cycle count by a normalized program erase increment.
“The wear leveling module 260 may use a normalized version of the write and/or erase cycle counts. For example, the number of write cycles performed on a block in the first solid-state nonvolatile memory 204 may be divided by the total number of write cycles that a block in the first solid-state nonvolatile memory 204 can endure” (Sutardja [0122] the increment being multiplied by is 1/total number of write cycles that can be endured, which is the same as dividing by the total number of write cycles that can be endured)
Regarding Claim 23, Sutardja further discloses wherein the program/erase cycle count of an associated physical address of the physical addresses of the memory units is incremented by a normalized program/erase increment per program/erase cycle.
“The wear leveling module 260 may use a normalized version of the write and/or erase cycle counts. For example, the number of write cycles performed on a block in the first solid-state nonvolatile memory 204 may be divided by the total number of write cycles that a block in the first solid-state nonvolatile memory 204 can endure” (Sutardja [0122] the increment being multiplied by is 1/total number of write cycles that can be endured, which is the same as dividing by the total number of write cycles that can be endured)
“With various nonvolatile memories, writing data to a block may require erasing or writing to the entire block. In such a block-centric memory, the wear leveling module may track the number of times that each block has been erased or written” (Sutardja [0111] the tracking can displayed by the normalized value via the mathematical calculations described in paragraph [0122])
Claims 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sutardja (published June 12, 2008), Kim (filed November 15, 2017) and Kankani (published November 24, 2015) as applied to claims 1, above, and further in view of Fai et al. (US 2012/0216079) (hereinafter Fai) (published August 23, 2012).
Regarding Claim 21, the combination of Sutardja, Kim, and Kankani disclosed the device of claim 1, but does not explicitly state further comprising a host interface configured to communicate with a host device through a communication channel connecting the host interface and the host device.
Fai discloses further comprising a host interface configured to communicate with a host device through a communication channel connecting the host interface and the host device.
“In another implementation, a memory device includes non-volatile memory, a host interface that communicatively connects the memory device to a host, and a memory controller that is configured to perform memory operations on the non-volatile memory and that communicates with the host through the host interface” (Fai [0007])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to modify the combination of Sutardja, Kim, and Kankani to use a separate host interface as shown in Fai. The functions of communicating with the host is the same with the host interface as a separate component or integrated into the controller and the motivation for the modification would be design choice of making separable and rearrangement of parts as disclosed in MPEP 2144.04.
Response to Arguments
Applicant’s arguments, see page 1 of remarks, filed March 04, 2026, with respect to the rejection(s) of claim(s) 1, 4-12, and 15-19 under the ground of nonstatutory double patenting have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of U.S. Patent No. 11,733,873, KIM et al. (US 2018/0285197), and Kankani et al. (US 2016/0342344).
Applicant’s arguments, see pages 1-3 of remarks, filed March 04, 2026, with respect to the rejection(s) of claim(s) 1, 3-12, and 14-20 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Sutardja (US 2008/0140918), KIM et al. (US 2018/0285197) and Kankani et al. (US 2016/0342344). Kankani discloses the newly added limitations to the claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.L./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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