DETAILED ACTION
Claims 1-18 are presented for examination. Applicant has amended claims 1-7 and 13.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 6-8, 12-14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over IM et al. (US 2011/0161965 A1) in view of Xu et al. (US 9,588,808 B2).
As to claim 1, IM teaches a multi-core processor (the multi-core processor; paragraph [0040]), comprising multiple processing cores (The job processors include a first core, a second core, a third core; paragraph [0043]), wherein the multi-core processor executes programming instructions to:
store multiple job chains and dependency relationships between the multiple job chains (The host processor 100 may control and manage stage allocation and stage execution of each device processors. Accordingly, the device processors may perform pipeline processing of an application in parallel and in time-sliced fashion by dividing the application into two or more stages; paragraph [0040] and The work list management module 110 may manage correlation information between two or more stages of the application. The correlation information may include information that indicates the relationship between two or more stages; paragraph [0048]), wherein the dependency relationship comprises dependency and non-dependency (processing of an application in parallel (non-dependency) and in time-sliced fashion (dependency) by dividing the application into two or more stages; paragraph [0040], [0052], [0063]);
determine a first job chain and a second job chain in the multiple job chains based on the dependency relationships between the multiple job chains, wherein a dependency relationship between the first job chain and the second job chain is non-dependency, the first job chain comprises one or more first tasks, and the second job chain comprises one or more second tasks (The work list management module may manage correlation information (i.e., relationship) between two or more stages of the application; paragraph [0048] and subordinate relationship between stages in a work list; paragraphs [0064]-[0066]);
schedule a part or all of the multiple processing cores to execute the one or more first tasks (The work scheduler that operates on the host processor may allocate stages to the host processors that are capable of pipeline processing an application; paragraph [0052] and [0057]-[0059]); and
schedule at least one second task in the second job chain to at least one first processing core for execution (a first processor may process stage A and C; paragraph [0057] and stages A, B and C may be executed in the first processors; paragraph [0060]).
IM does not teach while executing the one or more first tasks on the part or all of the multiple processing cores, schedule at least one second task in the second job chain to at least one first processing core for execution when the at least one first processing core in the multiple processing cores is in an idle state.
However, IM teaches the core capacity is in considered when assign stage to processor (The work scheduler may determine how many stages will be allocated to each job processor based on the stage correlation information managed by the work list management module and the core capability with respect to each stage which is managed by the core capability management module 120; paragraph [0049], [0052]).
Xu, in the same field of endeavor, teaches while executing the one or more first tasks on the part or all of the multiple processing cores, schedule at least one second task in the second job chain to at least one first processing core for execution when the at least one first processing core in the multiple processing cores is in an idle state (Task manager 16 assigns tasks to cores 18, 20, 22, and 24. Cores 18, 20, 22, and 24 begin running the assigned tasks which may include a first task assigned to core 18 and other tasks assigned to cores 20, 22, and 24. The first task may include a job that is a software operation that core 18 may perform on its own. The first task may also include a job that requires an accelerator such as accelerator 28. In such case, core 18 requests use of an accelerator from task manger 16 and stores context information for that stage of the task in a context storage buffer in core 18. Task manager 16 passes that job to an accelerator that can perform the job. If accelerator 28 can perform the job, task manager 16 may assign the job to accelerator 28. After task manager 16 assigns the job to accelerator 28, core 18 is then available for task manger 16 to assign it a second task. While accelerator 28 is executing the job it has been assigned, core 18 may begin the second task or it may be inhibited as it waits for the accelerator 28 to complete the job. When accelerator 28 finishes its assigned job, accelerator 28 provides an output pointer and completion status information to task manager 16. Core 18 may still be performing the second task if it was not inhibited. Another core, such as core 20, may be available for performing tasks at this point. In such case task manager fetches the context information from core 18 and assigns the first task to core 20 while also providing the context information to core 20. With core 20 now having the context information, core 20 can continue with the first task. When a context is switched to a different core, task status info 26 is updated indicating that core 20 is now assigned to the first task; col. 2, lines 25-58).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of Xu to the system of IM because Xu teaches a method that allows available/idle core to execute another job, thus improve the performance of the system reduce/eliminate the resources assigned to the idle/available cores.
As to claim 2, IM as modified by Xu teaches determining that the dependency relationship between the first job chain and the second job chain is non-dependency (see Xu: task manager 16 assigns tasks to cores 18, 20, 22, and 24. Cores 18, 20, 22, and 24 begin running the assigned tasks which may include a first task assigned to core 18 and other tasks assigned to cores 20, 22, and 24; col. 2, lines 18-31). Clearly, the tasks are executed in parallel, i.e., no dependency between tasks.
As to claim 6, IM as modified by Xu teaches:
obtain a command stream (see IM: the multi-core processor receives a task execution request from a specific application; paragraph [0071]) and dependency relationships between a part or all of the multiple job chains (see IM: the multi-core processor divides the task into stages and generates correlation information between the stages; paragraph [0072]);
generate the part or all of the multiple job chains based on the command stream (see IM: The stages refer to smaller task units that allow the requested task to be divided up and processed in a pipeline manner; paragraph [0072]).
As to claim 7, IM teaches a method (a method; abstract), applied to a multi- core processor (the multi-core processor; paragraph [0040]), wherein the multi-core processor comprises a job manager (host processor; Fig. 2 and paragraph [0040]) and multiple processing cores coupled to the job manager (a first device processor, a second device processor, and third device processor; Fig. 2 and paragraph [0040] and The job processors include a first core, a second core, a third core; paragraph [0043]), and the method comprises:
storing multiple job chains and dependency relationships between the multiple job chains by using the job manager, wherein the dependency relationship comprises dependency and non-dependency (The host processor 100 may control and manage stage allocation and stage execution of each device processors. Accordingly, the device processors may perform pipeline processing of an application in parallel and in time-sliced fashion by dividing the application into two or more stages; paragraph [0040] and The work list management module 110 may manage correlation information between two or more stages of the application. The correlation information may include information that indicates the relationship between two or more stages; paragraph [0048]), wherein the dependency relationship comprises dependency and non-dependency (processing of an application in parallel (non-dependency) and in time-sliced fashion (dependency) by dividing the application into two or more stages; paragraph [0040], [0052], [0063]);
determining a first job chain and a second job chain in the multiple job chains based on the dependency relationships between the multiple job chains by using the job manager, wherein a dependency relationship between the first job chain and the second job chain is non-dependency, the first job chain comprises one or more first tasks, and the second job chain comprises one or more second tasks (The work list management module may manage correlation information (i.e., relationship) between two or more stages of the application; paragraph [0048] and subordinate relationship between stages in a work list; paragraphs [0064]-[0066]);
scheduling, by using the job manager, a part or all of the multiple processing cores to execute the one or more first tasks (The work scheduler that operates on the host processor may allocate stages to the host processors that are capable of pipeline processing an application; paragraph [0052] and [0057]-[0059]); and
scheduling, by using the job manager, at least one second task in the second job chain to at least one first processing core for execution (a first processor may process stage A and C; paragraph [0057] and stages A, B and C may be executed in the first processors; paragraph [0060]).
IM does not teach while executing the one or more first tasks on the part or all of the multiple processing cores, schedule at least one second task in the second job chain to at least one first processing core for execution when the at least one first processing core in the multiple processing cores is in an idle state.
However, IM teaches the core capacity is in considered when assign stage to processor (The work scheduler may determine how many stages will be allocated to each job processor based on the stage correlation information managed by the work list management module and the core capability with respect to each stage which is managed by the core capability management module 120; paragraph [0049], [0052]).
Xu, in the same field of endeavor, teaches while executing the one or more first tasks on the part or all of the multiple processing cores, schedule at least one second task in the second job chain to at least one first processing core for execution when the at least one first processing core in the multiple processing cores is in an idle state (Task manager 16 assigns tasks to cores 18, 20, 22, and 24. Cores 18, 20, 22, and 24 begin running the assigned tasks which may include a first task assigned to core 18 and other tasks assigned to cores 20, 22, and 24. The first task may include a job that is a software operation that core 18 may perform on its own. The first task may also include a job that requires an accelerator such as accelerator 28. In such case, core 18 requests use of an accelerator from task manger 16 and stores context information for that stage of the task in a context storage buffer in core 18. Task manager 16 passes that job to an accelerator that can perform the job. If accelerator 28 can perform the job, task manager 16 may assign the job to accelerator 28. After task manager 16 assigns the job to accelerator 28, core 18 is then available for task manger 16 to assign it a second task. While accelerator 28 is executing the job it has been assigned, core 18 may begin the second task or it may be inhibited as it waits for the accelerator 28 to complete the job. When accelerator 28 finishes its assigned job, accelerator 28 provides an output pointer and completion status information to task manager 16. Core 18 may still be performing the second task if it was not inhibited. Another core, such as core 20, may be available for performing tasks at this point. In such case task manager fetches the context information from core 18 and assigns the first task to core 20 while also providing the context information to core 20. With core 20 now having the context information, core 20 can continue with the first task. When a context is switched to a different core, task status info 26 is updated indicating that core 20 is now assigned to the first task; col. 2, lines 25-58).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of Xu to the system of IM because Xu teaches a method that allows available/idle core to execute another job, thus improve the performance of the system reduce/eliminate the resources assigned to the idle/available cores.
As to claim 8, IM as modified by Xu teaches the method according to claim 7, wherein the job manager comprises a dependency manager and a task queue (see IM: The work list management module 110 may manage correlation information between two or more stages of the application; paragraph [0048]) and a task queue (see IM: inherent from “a host processor is configured to divide an application to be processed into a plurality of stages”; paragraph [0022], thus, the host must include a queue to store the stages of application); wherein storing the dependency relationships between the multiple job chains by using the job manager comprises:
storing the dependency relationships between the multiple job chains by using the dependency manager in the job manager (see IM: The work list management module 110 may manage correlation information between two or more stages of the application. The correlation information may include information that indicates the relationship between two or more stages.; paragraph [0048]).
IM as modified by Xu does not teach sending a first instruction to the task queue by using the dependency manager in the job manager if determining, by using the dependency manager in the job manager, that the dependency relationship between the first job chain and the second job chain is non-dependency, wherein the first instruction indicates that the dependency relationship between the first job chain and the second job chain is non-dependency.
However, IM teaches different stages of the application executed in parallel on different job processors (processing of an application in parallel (non-dependency) and in time-sliced fashion (dependency) by dividing the application into two or more stages; paragraph [0040], [0052], [0063]), the work scheduler may determine how many stages will be allocated to each job processor based on the stage correlation information managed by the work list management module and the core capability with respect to each stage which is managed by the core capability management module 120 (paragraph [0049], [0052]).
Given the teaching of IM above, the host processor aware which stages have non-dependency relationship in order to assign stages to which job processor, and the instruction must be sent to the task queue to inform stage relationship information.
As to claim 12, IM as modified by Xu teaches the method according to claim 8, wherein the job manager further comprises a task assembling manager, and the method further comprises:
obtaining a command stream (see IM: the multi-core processor receives a task execution request from a specific application; paragraph [0071]) and dependency relationships between a part or all of the multiple job chains by using the task assembling manager in the job manager (see IM: the multi-core processor divides the task into stages and generates correlation information between the stages; paragraph [0072]), and generating the part or all of the multiple job chains based on the command stream (see IM: The stages refer to smaller task units that allow the requested task to be divided up and processed in a pipeline manner; paragraph [0072]); and
sending the part or all of the multiple job chains to the task queue by using the task assembling manager in the job manager (see IM: inherent from “a host processor is configured to divide an application to be processed into a plurality of stages”; paragraph [0022], thus, the host must include a queue to store the stages of application), and sending the dependency relationships between the part or all of the multiple job chains to the dependency manager (see IM: The work list management module 110 may manage correlation information between two or more stages of the application. The correlation information may include information that indicates the relationship between two or more stages; paragraph [0048]).
As to claim 13, IM teaches a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores a computer program (The methods described above may be recorded, stored, or fixed in one or more computer-readable storage media; paragraph [0081]) which, when executed by a multi-core processor (the multi-core processor; paragraph [0040]) comprising a job manager (host processor; Fig. 2 and paragraph [0040]) and multiple processing cores coupled to the job manager (a first device processor, a second device processor, and third device processor; Fig. 2 and paragraph [0040] and The job processors include a first core, a second core, a third core; paragraph [0043]), causes the multi-core processor to perform operations comprising:
storing multiple job chains and dependency relationships between the multiple job chains, wherein the dependency relationship comprises dependency and non-dependency (The host processor 100 may control and manage stage allocation and stage execution of each device processors. Accordingly, the device processors may perform pipeline processing of an application in parallel and in time-sliced fashion by dividing the application into two or more stages; paragraph [0040] and The work list management module 110 may manage correlation information between two or more stages of the application. The correlation information may include information that indicates the relationship between two or more stages; paragraph [0048]), wherein the dependency relationship comprises dependency and non-dependency (processing of an application in parallel (non-dependency) and in time-sliced fashion (dependency) by dividing the application into two or more stages; paragraph [0040], [0052], [0063]);
determining a first job chain and a second job chain in the multiple job chains based on the dependency relationships between the multiple job chains, wherein a dependency relationship between the first job chain and the second job chain is non-dependency, the first job chain comprises one or more first tasks, and the second job chain comprises one or more second tasks (The work list management module may manage correlation information (i.e., relationship) between two or more stages of the application; paragraph [0048] and subordinate relationship between stages in a work list; paragraphs [0064]-[0066]);
scheduling a part or all of the multiple processing cores to execute the one or more first tasks (The work scheduler that operates on the host processor may allocate stages to the host processors that are capable of pipeline processing an application; paragraph [0052] and [0057]-[0059]); and
schedule at least one second task in the second job chain to at least one first processing core for execution (a first processor may process stage A and C; paragraph [0057] and stages A, B and C may be executed in the first processors; paragraph [0060]).
IM does not teach while executing the one or more first tasks on the part or all of the multiple processing cores, schedule at least one second task in the second job chain to at least one first processing core for execution when the at least one first processing core in the multiple processing cores is in an idle state.
However, IM teaches the core capacity is in considered when assign stage to processor (The work scheduler may determine how many stages will be allocated to each job processor based on the stage correlation information managed by the work list management module and the core capability with respect to each stage which is managed by the core capability management module 120; paragraph [0049], [0052]).
Xu, in the same field of endeavor, teaches while executing the one or more first tasks on the part or all of the multiple processing cores, schedule at least one second task in the second job chain to at least one first processing core for execution when the at least one first processing core in the multiple processing cores is in an idle state (Task manager 16 assigns tasks to cores 18, 20, 22, and 24. Cores 18, 20, 22, and 24 begin running the assigned tasks which may include a first task assigned to core 18 and other tasks assigned to cores 20, 22, and 24. The first task may include a job that is a software operation that core 18 may perform on its own. The first task may also include a job that requires an accelerator such as accelerator 28. In such case, core 18 requests use of an accelerator from task manger 16 and stores context information for that stage of the task in a context storage buffer in core 18. Task manager 16 passes that job to an accelerator that can perform the job. If accelerator 28 can perform the job, task manager 16 may assign the job to accelerator 28. After task manager 16 assigns the job to accelerator 28, core 18 is then available for task manger 16 to assign it a second task. While accelerator 28 is executing the job it has been assigned, core 18 may begin the second task or it may be inhibited as it waits for the accelerator 28 to complete the job. When accelerator 28 finishes its assigned job, accelerator 28 provides an output pointer and completion status information to task manager 16. Core 18 may still be performing the second task if it was not inhibited. Another core, such as core 20, may be available for performing tasks at this point. In such case task manager fetches the context information from core 18 and assigns the first task to core 20 while also providing the context information to core 20. With core 20 now having the context information, core 20 can continue with the first task. When a context is switched to a different core, task status info 26 is updated indicating that core 20 is now assigned to the first task; col. 2, lines 25-58).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of Xu to the system of IM because Xu teaches a method that allows available/idle core to execute another job, thus improve the performance of the system reduce/eliminate the resources assigned to the idle/available cores.
As to claims 14 and 18, see rejections of claims 8 and 12 above, respectively.
Claims 3-5, 9-11 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over IM et al. (US 2011/0161965 A1) in view of Xu et al. (US 9,588,808 B2) further in view of VRIND et al. (US 2019/0087224 A1).
As to claim 3, IM as modified by Xu does not teach preempt a processing core for the first job chain and the second job chain.
However, VRIND, in the same field of endeavor, teaches a pre-emptive task scheduling is adopted where highest-priority tasks are executed on any available processor core (paragraphs [0032] and [0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of VRIND to the system of IM as modified by Xu, because VRIND teaches a method that tasks in a system can be executed based on priority-driven scheduling (paragraph [0032]).
As to claim 4, IM as modified by Xu teaches split the first job chain into the one or more first tasks (see IM: stages A0, A1 of stage A; paragraph [0064]-[0069]).
IM as modified by Xu does not teach preempt one or more second processing cores from the multiple processing cores; and scheduling the one or more second processing cores to execute the one or more first tasks.
However, VRIND, in the same field of endeavor, teaches a pre-emptive task scheduling is adopted where highest-priority tasks are executed on any available processor core (paragraphs [0032] and [0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of VRIND to the system of IM as modified by Xu, because VRIND teaches a method that tasks in a system can be executed based on priority-driven scheduling (paragraph [0032]). Thus, when applying the teaching of VRIND to the system of IM as modified by XU, when the when one or more first tasks have higher priority than other tasks of the other stages, processors execute other lower tasks must be pre-emptive so the first tasks can be executed first.
As to claim 5, IM as modified by Xu teaches split the second job chain into the one or more second tasks (see IM: stages B0, B1 of stage B; paragraph [0064]-[0069]);
IM as modified by Xu does not teach preempt the at least one first processing core when the at least one first processing core in the multiple processing cores is in the idle state; and scheduling the at least one second task in the one or more second tasks to the at least one first processing core for execution.
However, Xu, in the same field of endeavor, teaches schedule at least one second task in the second job chain to at least one first processing core for execution when the at least one first processing core in the multiple processing cores is in an idle state (After task manager assigns the job to accelerator 28, core 18 is then available for task manager to assign it to a second task. While accelerator is executing the job it has been assigned, core 18 may begin the second task; col. 2, lines 40-44).
VRIND, in the same field of endeavor, teaches a pre-emptive task scheduling is adopted where highest-priority tasks are executed on any available processor core (paragraphs [0032] and [0035]).
Given the teaching of Xu and VRIND above, it would have obvious to one of ordinary skill in the art, the system of IM as modified by Xu and VRIND, for the same reasoning as set forth in claim 4 above, would implementing the claim 5 above.
As to claim 9, IM as modified by Xu teaches the method according to claim 8, wherein the job manager further comprises a task splitting manager (see IM: inherent from “a host processor is configured to divide an application to be processed into a plurality of stages”; paragraph [0022]. Thus, the host must include a software/hardware module to perform the splitting task) and a multi-core manager (a core capability management module 120; paragraph [0047] and [0049]);
wherein storing the multiple job chains by using the job manager comprises:
storing the multiple job chains by using the task queue in the job manager (see IM: inherent from “a host processor is configured to divide an application to be processed into a plurality of stages”; paragraph [0022], thus, the host must include a queue to store the stages of application); and
wherein determining the first job chain and the second job chain in the multiple job chains based on the dependency relationships between the multiple job chains by using the job manager further comprises:
after receiving, by using the task queue in the job manager, the first instruction sent by
using the dependency manager in the job manager, sending the first job chain and the second job
chain to the task splitting manager by using the task queue in the job manager (see IM: stages A0, A1 of stage A, stages B0, B1 of stage B, etc.; paragraph [0064]-[0069]).
IM and Xu do not teach sending a second instruction to the multi-core manager, wherein the second instruction indicates the multi-core manager to preempt a processing core for the first job chain and the second job chain.
However, VRIND, in the same field of endeavor, teaches a pre-emptive task scheduling is adopted where highest-priority tasks are executed on any available processor core (paragraphs [0032] and [0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of VRIND to the system of IM as modified by Xu, because VRIND teaches a method that tasks in a system can be executed based on priority-driven scheduling (paragraph [0032]).
As to claim 10, IM as modified by Xu teaches the method according to claim 9, wherein scheduling, by using the job manager, the part or all of the multiple processing cores to execute the one or more first tasks comprises:
splitting the first job chain into the one or more first tasks by using the task splitting
manager in the job manager (see IM: stages A0, A1 of stage A; paragraph [0064]-[0069]).
IM as modified by Xu does not teach preempting one or more second processing cores from the multiple processing cores based on the second instruction by using the multi-core manager in the job manager; sending, to the task splitting manager by using the multi-core manager in the job manager, a result of preempting the one or more second processing cores; and scheduling, by using the task splitting manager in the job manager, the one or more second processing cores to execute the one or more first tasks.
However, VRIND, in the same field of endeavor, teaches a pre-emptive task scheduling is adopted where highest-priority tasks are executed on any available processor core (paragraphs [0032] and [0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of VRIND to the system of IM as modified by Xu, because VRIND teaches a method that tasks in a system can be executed based on priority-driven scheduling (paragraph [0032]). Thus, when applying the teaching of VRIND to the system of IM as modified by XU, when the when one or more first tasks have higher priority than other tasks of the other stages, processors execute other lower tasks must be pre-emptive so the first tasks can be executed first.
As to claim 11, IM as modified by Xu teaches the method according to claim 10, wherein scheduling, by using the job manager, the at least one second task in the second job chain to the at least one first processing core for execution when the at least one first processing core in the multiple processing cores is in the idle state comprises:
splitting the second job chain into the one or more second tasks by using the task splitting
manager in the job manager (see IM: stages B0, B1 of stage B; paragraph [0064]-[0069]);
IM as modified by Xu does not teach preempting the at least one first processing core based on the second instruction by using the multi-core manager in the job manager when the at least one first processing core in the multiple processing cores is in the idle state; sending, to the task splitting manager by using the multi-core manager in the job manager, a result of preempting the at least one first processing core; and scheduling, by using the task splitting manager in the job manager, the at least one second task in the one or more second tasks to the at least one first processing core for execution.
VRIND, in the same field of endeavor, teaches a pre-emptive task scheduling is adopted where highest-priority tasks are executed on any available processor core (paragraphs [0032] and [0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teaching of VRIND to the system of IM as modified by Xu, because VRIND teaches a method that tasks in a system can be executed based on priority-driven scheduling (paragraph [0032]). Thus, when applying the teaching of VRIND to the system of IM as modified by XU, when the when one or more first tasks have higher priority than other tasks of the other stages, processors execute other lower tasks must be pre-emptive so the first tasks can be executed first.
As to claims 15-17, see rejections of claims 9-11 above, respectively.
Response to Arguments
Applicant's arguments filed 1-18 have been fully considered but they are not persuasive.
In response to Applicant’s arguments regarding Xu does not teach the limitation “while executing the one or more first tasks on the part or all of the multiple processing cores, schedule at least one second task in the second job chain to at least one first processing core for execution when the at least one first processing core in the multiple processing cores is in an idle state”, examiner respectfully disagrees because the claim 1 states “schedule a part of the multiple processing cores to execute the one or more first task”, and Xu teaches “Task manager 16 assigns tasks to cores 18, 20, 22, and 24. Cores 18, 20, 22, and 24 begin running the assigned tasks which may include a first task assigned to core 18 and other tasks assigned to cores 20, 22, and 24”. Thus, the first task is assigned to core 18, other cores are available/idle and are assigned other tasks.
Therefore, the arguments are not persuasive and the rejection is maintained.
The rejection has been clarified to show the existing prior art still teaches the limitations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DIEM K CAO/Primary Examiner, Art Unit 2196
DC
June 7, 2026
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