DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of 1-13 and 21-27 in the reply filed on June 22, 2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 21 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Funabashi et al. (US PGPUB 2019/0138671; hereinafter “Funabashi”) in view of Hamid et al. (US PGPUB 2015/0302126; hereinafter “Hamid”), Lakkapragada et al. (US Patent 7,165,189; hereinafter “Lakka”) and Panttila et al. (US PGPUB 2025/0025081; hereinafter “Panttila”).
Claim 1:
Funabashi teaches a device a device, comprising:
a processing system including a processor ([0032] “The simulation device 10 includes a CPU (Central Processing Unit) 11 as an operational unit (processor).”); and
a memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations ([0032] “The simulation device 10 includes… a memory 12 that stores the program and various data.” [0033] “the CPU 11 executes the programs (software) stored in the memory 12 to perform the processes of the MILS environment unit 200, the SPILS environment unit 100, and the test control unit 300.”),
the operations comprising:
obtaining a validation dataset; utilizing the first computer-usable model and the validation dataset to establish a baseline performance of the first computer-usable model ([0039] “The entire validation control part 310 performs a test, for example, according to the test scenario list shown in FIG. 5. For example, ‘required identifier’, ‘control to be executed’, ‘time’, ‘event’, and the like, are described in the test scenario list. In the test scenario list, the ‘required identifier’ is an identifier that identifies each test scenario. The ‘control to be performed’ is information that identifies the control to be executed. The ‘time’ is an example of the information that shows the operation condition of the ‘event’, and shows the occurrence time of the ‘event’. The ‘event’ is information that shows the operation content, which shows the event to be generated when the time managed by the MILS environment unit 200 reaches the ‘time’ of the test scenario.”); and
performing automated testing on the first computer-usable model to determine whether the first computer-usable model successfully handles a plurality of test scenarios ([0029] “The entire validation control part 310 (test control unit) carries out a test by operating a virtual device model according to a predetermined test scenario. More specifically, when the operation condition defined by the test scenario is satisfied, the entire validation control part 310 controls the car model 210 to perform the operation content defined in the test scenario. The car model 210 performs a process using the module model 220 under the control of the entire validation control part 310.”).
With further regard to Claim 1, Funabashi does not teach the following, however, Hamid teaches:
building a first computer-usable model that characterizes a system, wherein the building is based at least in part upon a defined plurality of performance metrics associated with the first computer-usable model ([0028] “a method includes generating application scenario models or performance scenario models from multiple driver scenario models. For example, portable driver scenario models for individual functions, e.g., for each IP of the SoC, etc., are combined, e.g., connected together via links, etc., to define application scenario models or performance scenario models.” [0115] “a performance scenario model is similar to the application scenario model except that in the performance scenario model, a test output is compared with an expected output to determine whether an SoC or a design of the SoC passed a test.” [0299] “the performance scenario model includes a constraint that the configuration sub-module of the image processor module representation be configured to encode or decode with a quality that is greater than the pre-set value.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device as disclosed by Funabashi with the model generating as taught by Hamid in order “to mimic an actual performance of an SoC” (Hamid [0056]).
With further regard to Claim 1, Funabashi in view of Hamid does not teach the following, however, Lakka teaches:
wherein the automated testing results in a first determination; responsive to the first determination being that the first computer-usable model successfully handles the plurality of test scenarios, performing fault injection by injecting a plurality of faults into the first computer-usable model and determining whether the first computer-usable model successfully handles the plurality of faults, wherein the fault injection results in a second determination (Col. 5 ll. 3-8: “By way of example, in a particular test situation, it may be desirable to first perform functional tests and then proceed to load testing only when the system appears to be working fine in the functional tests. Thereafter fault injection tests may be performed only after the load testing has been successful, and so on.” Col. 9 ll. 24-27: “An illustrative example of a summary test report is illustrated in FIG. 9. The test report 900 includes a number of illustrative example fields that are useful in reporting the results of a given test suite module,” see Fig. 9.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device as disclosed by Funabashi in view of Hamid with the performance of fault injection testing after initial testing as taught by Lakka since “it is typically desirable to perform testing in a progressive manner” (Lakka Col. 5 ll. 2-3).
With further regard to Claim 1, Funabashi in view of Hamid and Lakka does not teach the following, however, Panttila teaches:
responsive to the second determination being that the first computer-usable model successfully handles the plurality of faults, facilitating deployment of the first computer-usable model ([0097] “the fault injection system 408 can issue a command to deploy an AV 102 to a particular destination (e.g., a destination associated with the safety track) upon successful completion of one or more vehicle operation fault injections and/or driver responses to one or more vehicle operation fault injections associated with the AV 102.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device as disclosed by Funabashi in view of Hamid and Lakka with the deployment after fault injection testing as taught by Panttila thereby “ensuring that the AV can operate effectively, in a way that is evident, logical, or familiar” (Panttila [0003]).
Claims 21 and 25:
With regard to Claims 21 and 25, these claims are equivalent in scope to Claim 1 rejected above, merely having a different independent claim type, and as such Claims 21 and 25 are rejected under the same grounds and for the same reasons as discussed above with regard to Claim 1.
Claims 2-5 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Funabashi in view of Hamid, Lakka and Panttila as applied to Claims 1 and 21 above, and further in view of Tiwari et al. (US Patent 11,102,081; hereinafter “Tiwari”).
Claim 2:
Funabashi in view of Hamid, Lakka and Panttila teaches all the limitations of claim 1 as described above. Funabashi in view of Hamid, Lakka and Panttila does not teach the following, however, Tiwari teaches:
wherein the first computer-usable model successfully handling the plurality of test scenarios comprises the first computer-usable model encountering no errors or inconsistencies as a result of running the plurality of test scenarios (Col. 15 ll. 25-34: “the testing may continue until a threshold metric indicative of a stop testing condition is achieved (e.g., a threshold number of conditions have been tested, a threshold percentage of conditions have been tested, a threshold number of tests have been passed, a threshold percentage of tests conditions have been passed, an error rate is below a threshold, other conditions, or combinations thereof, such as a threshold percentage of test conditions have passed and the error rate is below an error rate threshold),” wherein the “error rate” threshold is zero in this instance.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device as disclosed by Funabashi in view of Hamid, Lakka and Panttila with the test success condition as taught by Tiwari in order to “improve the overall testing process and streamline each iteration of the testing process” (Tiwari Col. 15 ln. 66 – Col. 16 ln. 1).
Claim 3:
Funabashi in view of Hamid, Lakka and Panttila teaches all the limitations of claim 1 as described above. Funabashi in view of Hamid, Lakka and Panttila does not teach the following, however, Tiwari teaches:
wherein the first computer-usable model successfully handling the plurality of test scenarios comprises the first computer-usable model encountering no more than a threshold amount of errors or inconsistencies as a result of running the plurality of test scenarios (Col. 15 ll. 25-34: “the testing may continue until a threshold metric indicative of a stop testing condition is achieved (e.g., a threshold number of conditions have been tested, a threshold percentage of conditions have been tested, a threshold number of tests have been passed, a threshold percentage of tests conditions have been passed, an error rate is below a threshold, other conditions, or combinations thereof, such as a threshold percentage of test conditions have passed and the error rate is below an error rate threshold).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device as disclosed by Funabashi in view of Hamid, Lakka and Panttila with the test success condition as taught by Tiwari in order to “improve the overall testing process and streamline each iteration of the testing process” (Tiwari Col. 15 ln. 66 – Col. 16 ln. 1).
Claim 4:
Funabashi in view of Hamid, Lakka and Panttila teaches all the limitations of claim 1 as described above. Funabashi in view of Hamid, Lakka and Panttila does not teach the following, however, Tiwari teaches:
wherein the first computer-usable model successfully handling the plurality of faults comprises the plurality of faults causing no errors or inconsistencies (Col. 15 ll. 25-34: “the testing may continue until a threshold metric indicative of a stop testing condition is achieved (e.g., a threshold number of conditions have been tested, a threshold percentage of conditions have been tested, a threshold number of tests have been passed, a threshold percentage of tests conditions have been passed, an error rate is below a threshold, other conditions, or combinations thereof, such as a threshold percentage of test conditions have passed and the error rate is below an error rate threshold).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device as disclosed by Funabashi in view of Hamid, Lakka and Panttila with the test success condition as taught by Tiwari in order to “improve the overall testing process and streamline each iteration of the testing process” (Tiwari Col. 15 ln. 66 – Col. 16 ln. 1).
Claim 5:
Funabashi in view of Hamid, Lakka and Panttila teaches all the limitations of claim 1 as described above. Funabashi in view of Hamid, Lakka and Panttila does not teach the following, however, Tiwari teaches:
wherein the first computer-usable model successfully handling the plurality of faults comprises the plurality of faults causing no more than a threshold amount of errors or inconsistencies (Col. 15 ll. 25-34: “the testing may continue until a threshold metric indicative of a stop testing condition is achieved (e.g., a threshold number of conditions have been tested, a threshold percentage of conditions have been tested, a threshold number of tests have been passed, a threshold percentage of tests conditions have been passed, an error rate is below a threshold, other conditions, or combinations thereof, such as a threshold percentage of test conditions have passed and the error rate is below an error rate threshold),” wherein the “error rate” threshold is zero in this instance.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device as disclosed by Funabashi in view of Hamid, Lakka and Panttila with the test success condition as taught by Tiwari in order to “improve the overall testing process and streamline each iteration of the testing process” (Tiwari Col. 15 ln. 66 – Col. 16 ln. 1).
Claims 22-23:
With regard to Claims 22-23, these claims are equivalent in scope to Claims 3 and 5 rejected above, merely having a different independent claim type, and as such Claims 22-23 are rejected under the same grounds and for the same reasons as discussed above with regard to Claims 3 and 5.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Funabashi in view of Hamid, Lakka and Panttila as applied to Claims 1 and 21 above, and further in view of Munguia Tapai et al. (US PGPUB 2022/0067573; hereinafter “Munguia”).
Claim 12:
Funabashi in view of Hamid, Lakka and Panttila teaches all the limitations of claim 1 as described above. Funabashi in view of Hamid, Lakka and Panttila does not teach the following, however, Munguia teaches:
wherein the first computer-usable model comprises:
an artificial intelligence (Al) model;a machine learning (ML) model; or any combination thereof ([0001] “As artificial intelligence (Al) and machine learning (ML) gain prominence in different domains, statistical modeling is being increasingly used for various tasks such as making predictions, information extraction, binary or multi-class classification, etc. The generation of an ML model includes identifying an algorithm and providing the appropriate training data for the algorithm to learn from. The ML model refers to the model artifact that is created by the training data. The ML models can be trained via supervised training using labeled training data or via unsupervised training method.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device as disclosed by Funabashi in view of Hamid, Lakka and Panttila with the model type as taught by Munguia for purposes of “technical improvement in the field of model training and generation as it enables constant monitoring and improving models included in the production systems” (Munguia [0018]).
Allowable Subject Matter
Claims 6-11, 13, 24 and 26-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joanne G. Macasiano whose telephone number is (571)270-7749. The examiner can normally be reached Monday to Thursday, 10:30 AM to 6:00 PM Eastern Standard Time.
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/JOANNE G MACASIANO/Examiner, Art Unit 2197
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