DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Foreign priority is not claimed for this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/02/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 12 and 15 are objected to because of the following informalities:
Claim 12, page 3 line 24: “the output of the amplifier” should read “the output node of the amplifier” in order to align with the language of claim 1.
Claim 15, page 4 line 7: “the output of the amplifier” should read “the output node of the amplifier” in order to align with the language of claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-9 and 11-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation "the first clamping transistor element," “the second clamping transistor element,” “the second auxiliary control transistor element,” and “the second control transistor element” in lines 15-16 of page 2. There is insufficient antecedent basis for these limitations in the claim. These elements are mentioned in other claims that claim 7 does not depend on. Appropriate correction is required.
Claim 8 recites the limitations "the first clamping transistor element," “the second clamping transistor element,” “the second auxiliary control transistor element,” and “the second control transistor element” in lines 23-26 of page 2. There is insufficient antecedent basis for these limitation in the claim. These elements are mentioned in other claims that claim 8 does not depend on. Appropriate correction is required.
Claim 9 recites the limitation “an output of the amplifier assembly” in lines 1-2 of page 3. Examiner is unsure if this output is the same as the output of claim 1. If it is, then “an output” should be “the output node” in order to align with claim 1. Appropriate correction is required.
Claim 11 line 14 on page 3 has the same issue as claim 9. Appropriate correction is required.
Claim 12 recites the limitations "the control terminal of the first load transistor element," “the control terminal of the second load transistor element,” and “the channel of the first load transistor element” in lines 19-21 of page 3. There is insufficient antecedent basis for these limitations in the claim. Appropriate correction is required.
Claim 12 recites the limitations "the channel of the second load transistor element" and “the control terminal of the output transistor element” in lines 22-23 of page 3. There is insufficient antecedent basis for this limitation in the claim. Appropriate correction is required.
Claim 12 recites the limitation "the channel of the output transistor element" in line 24 of page 3. There is insufficient antecedent basis for this limitation in the claim. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 15 is/are rejected under 35 U.S.C. 102(a0(1) and (a)(2) as being anticipated by WO 2021070246 by Kojima.
Regarding claim 1, Kojima teaches an amplifier assembly suitable for use as a rail-to-rail amplifier (Fig. 3) including:
a first input circuit (Fig. 3 #311 and #321) connected to a first signal input node (Vinp) for a first input level range;
a second input circuit (Fig. 3 #312 and #322) connected to a second signal input node (Vinn) for a second input level range;
a load circuit (Fig. 3 #330 and #351p) coupled to the first input circuit, the second input circuit and an output node of the amplifier assembly (Vout), wherein
the first input circuit includes a first auxiliary control transistor element (#311), and a first control transistor element (#321), wherein
the first signal input node (Vinp) is coupled to a control terminal (gate) of the first control transistor element (#321) and a control terminal (gate) of the first auxiliary control transistor element (#311);
a path connected in parallel to the first control transistor element includes the first auxiliary control transistor element (#311 and #321 are connected in parallel).
Regarding claim 15, Kojima teaches the amplifier assembly according to claim 1, wherein
the output of the amplifier assembly is coupled to the first signal input node or to the second signal input node (Fig. 1).
Claim(s) 1-7 and 9-13 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 20030038655 by Minamizaki et al.
Regarding claim 1, Minamizaki teaches an amplifier assembly suitable for use as a rail-to-rail amplifier (fig. 1, 7-8, 10-17) including:
a first input circuit (Fig. 16 M2 and M4; Fig. 17 M1 and M3) connected to a first signal input node (INp or INm) for a first input level range;
a second input circuit (Fig. 16 M1 and M3; Fig. 17 M2 and M4) connected to a second signal input node (INp or InM) for a second input level range;
a load circuit (Fig. 16 #22 and M17, Fig. 17 M15, M16, M34) coupled to the first input circuit, the second input circuit and an output node (Fig. 16, 17 output) of the amplifier assembly, wherein
the first input circuit includes a first auxiliary control transistor element (Fig. 16 and 17 M3 or M4), and a first control transistor element (Fig. 16 and 17 M1 or M2), wherein
the first signal input node is coupled to a control terminal (gate) of the first control transistor element (Fig. 16 and 17 M1 or M2) and a control terminal (gate) of the first auxiliary control transistor element (Fig. 16 and 17 M3 or M4);
a path connected in parallel to the first control transistor element includes the first auxiliary control transistor element (Fig. 16 M4 and M2 are in parallel; Fig. 17 M3 and M1 are in parallel).
Regarding claim 2, Minamizaki teaches the amplifier assembly according to claim 1, wherein the first input circuit includes a first clamping circuit (Fig. 16 M6), wherein the path connected in parallel to the first control transistor element includes, connected in series, the first clamping circuit (M6 and M4 are connected in series and they are both parallel to M2).
Regarding claim 3, Minamizaki teaches the amplifier assembly according to claim 2, wherein the first clamping circuit includes a first clamping transistor element (Fig. 16 M6), wherein a control terminal (gate) of the first clamping transistor element is controlled by an electrical quantity at a biasing input node (gate biased by an electrical quantity coming in through the external terminal).
Regarding claim 4, Minamizaki teaches the amplifier assembly according to claim 1, wherein the second input circuit includes a second auxiliary control transistor element (Fig. 16 M3, 17 M4), and a second control transistor element (Fig. 16 M1, 17 M2), wherein the second signal input node is coupled to a control terminal (gate) of the second control transistor element (M1 or M2) and a control terminal (gate) of the second auxiliary control transistor element (M3 or M4);
a path connected in parallel to the second control transistor element includes the second auxiliary control transistor element (Fig. 16 M1 and M3 are in parallel).
Regarding claim 5, Minamizaki teaches the amplifier assembly according to claim 4, wherein the second input circuit includes a second clamping circuit (Fig. 16 M5), wherein the path connected in parallel to the second control transistor element includes, connected in series, the second clamping circuit (Fig. 16 M5 and M3 are connected in series and they are both connected in parallel to M1).
Regarding claim 6, Minamizaki teaches the amplifier assembly according to claim 5, wherein the second clamping circuit includes a second clamping transistor element (Fig. 16 M5), wherein a control terminal (gate) of the second clamping transistor element is controlled by an electrical quantity at a biasing input node (gate biased by an electrical quantity coming in through the external terminal).
Regarding claim 7, Minamizaki teaches the amplifier assembly according to claim 1, wherein the first clamping transistor element (M6), the first auxiliary control transistor element (M4), the first control transistor element (M2), the second clamping transistor element (M5), the second auxiliary control transistor element (M3), and/or the second control transistor element (M1) are n-MOS transistor elements (Par. 47-48),
and/or all transistor elements of the first input circuit and/or of the second input circuit are n-MOS transistor elements (Par. 47-48).
Regarding claim 9, Minamizaki teaches the amplifier assembly according to claim 1, wherein
the load circuit (Fig. 16 #22 and M17; Fig. 17 M15, M16, M34) includes an output transistor element (Fig. 16 M17, Fig. 17 M34) for controlling an output of the amplifier assembly based on an output electrical quantity of the first input circuit and based on an output electrical quantity of the second input circuit (Fig. 16 M17 is connected to M5 and also to M6 through #22; Fig. 17 M34 is connected to the output of M2 and M4 and to the output of M1 and M3 through current mirror M15 and M16).
Regarding claim 10, Minamizaki teaches the amplifier assembly according to claim 1, wherein the load circuit includes an output transistor element (Fig. 16 M17; Fig. 17 M34), wherein the first input circuit and the second input circuit affect an electrical quantity at a control terminal (gate) of the output transistor element (Fig. 16 M17 is connected to M5 and also to M6 through #22; Fig. 17 M34 is connected to the output of M2 and M4 and to the output of M1 and M3 through current mirror M15 and M16).
Regarding claim 11, Minamizaki teaches the amplifier assembly according to claim 1, wherein the load circuit (Fig. 16 #22 and M17; Fig. 17 M15, M16, M34) includes a current mirror circuit (M15 and M16) and an output transistor element (M17; M34), wherein the current mirror circuit is coupled to the first input circuit (Fig. 16 M2 and M4; Fig. 17 M1 and M3), the second input circuit (Fig. 16 M1 and M3; Fig. 17 M2 and M4) and the output transistor element (M17, M34), and the output transistor element controls an output of the amplifier assembly.
Regarding claim 12, Minamizaki teaches the amplifier assembly according to claim 1, wherein the load circuit (Fig. 16 #22 and M17) includes an output transistor element (Fig. 16 M17), a first load transistor element and a second load transistor element (Fig. 16 M15 and M16),
wherein the first input circuit (Fig. 16 M2 and M4) is coupled to the control terminal (gate) of the first load transistor element (M16), to the control terminal (gate) of the second load transistor element (M15), and to the channel of the first load transistor element (M16), the second input circuit (M3, M5) is coupled to the channel of the second load transistor element (M15) and to the control terminal (gate) of the output transistor element (M17), and the channel of the output transistor element (M17) is coupled to the output of the amplifier assembly (Output).
Regarding claim 13, Minamizaki teaches the amplifier assembly according to claim 12, wherein the output transistor element, the first load transistor element and/or the second load transistor element are p-MOS transistor elements, and/or all transistor elements of the load circuit are p-MOS transistor elements (Par. 12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20030038655 by Minamizaki et al.
Regarding claim 8, Minamizaki teaches the amplifier assembly according to claim 1, but doesn’t specify if the transistors are native or standard MOS transistors.
However, this is simply a design choice and transistors of different types are known in the art and it would be easy to incorporate native or standard MOS transistors in Minamizaki. WO 2021/070246 by Kojima teaches with reference to fig. 3 that the auxiliary transistors (#311 and #312 of the operational amplifier) are native NMOS transistors and that control transistors (#321 and #322) are E-type or “normal” (standard) NMOS transistors.
Regarding claim 14, Minamizaki teaches the amplifier assembly according to claim 12, but doesn’t specify if the transistors standard MOS transistors.
However, this is simply a design choice and transistors of different types are known in the art. It would be easy to incorporate standard MOS transistors in Minamizaki. WO 2021/070246 by Kojima teaches both native and E-type/normal (standard) transistors used in an operational amplifier circuit.
Conclusion
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/NAREH SHAMIRYAN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843