DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim s 1 -10 and 12-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ide et al. (US PG Pub 2015/0236472) in view of Tojo et al. (US PG Pub 2004/0206975) and Inenaga (US PG Pub 2008/0317082) . Regarding claim 1, Ide et al. disclose: a semiconductor array device comprising: a semiconductor substrate (201) (Fig. 7, [0071]-[0073]) ; mesa-stripe structures (ridges 21a to 21e) that each extend in a first direction (into and out of the page in Fig. 7) , are arranged at equal intervals adjacent to each other in a second direction (horizontal direction in Fig. 7 ) perpendicular to the first direction, and each include an active layer (205) electrically connected to the semiconductor substrate (Fig. 7, [0071]-[0073]) ; individual electrodes (210a to 210e) that are arranged adjacent to each other in the second direction, and are each electrically connected to the active layer of a corresponding one of the mesa-stripe structures (Fig. 7, [0071]-[0073]) ; and a common electrode (200) that is electrically connected to the semiconductor substrate (Fig. 7, [0071]-[0073]) , wherein: the mesa-stripe structures including a first mesa-stripe structure (21b, 21c, 21d) and a pair of second mesa-stripe structures (21a and 21e) , the pair of second mesa-stripe structures sandwiching the first mesa-stripe structure (21a and 21e sandwiches 21b to 21d) (Fig. 7, [0071]-[0073]) . Ide et al. do not disclose: common electrodes that are arranged adjacent to each other in the second direction, and are each electrically connected to the semiconductor substrate; the common electrodes including a first electrode and a pair of second electrodes, the pair of second electrodes sandwiching the first electrode, the first electrode being closest to the first mesa-stripe structure among the mesa-stripe structures, each of the pair of second electrodes being closest to a corresponding one of the pair of second mesa-stripe structures among the mesa-stripe structures, each of the pair of second electrodes being smaller in area than the first electrode. Tojo et al. disclose: n-side electrodes 20, 21 are also completely independent from each other ( Fig. 3, [0072]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ide by forming independent n-electrodes for each individual laser device in order to drive the individual laser structures independently from each other . The device as modified disclose: common electrodes that are arranged adjacent to each other in the second direction, and are each electrically connected to the semiconductor substrate; the common electrodes including a first electrode (n electrodes for mesa stripes 21b to 21d) and a pair of second electrodes (n electrode for mesa stripes 21a and 21e), the pair of second electrodes sandwiching the first electrode (n electrodes for mesa stripes 21a and 21e sandwiches n electrodes for mesa stripes 21b to 21d), the first electrode being closest to the first mesa-stripe structure among the mesa-stripe structures, each of the pair of second electrodes being closest to a corresponding one of the pair of second mesa-stripe structures among the mesa-stripe structures . Ide as modified do not disclose: each of the pair of second electrodes being smaller in area than the first electrode. Inenaga discloses: t he width of the electrode 8 of the laser diode at the center of the laser array chip 1 is larger than that of each of the electrodes 8 of the adjacent laser diodes. In addition, the widths of the electrodes 8 of the laser diodes located in each end of the laser array chip 1, that is, in the most outside thereof are the smallest. In other words, among contacting areas between the electrodes 8 of the laser diode and electrodes 31 of the sub-mount 2, the contacting area at a center position is larger than that at the end positions. With such a configuration, the heat generated in the laser diode located at the center of the laser array chip 1 easily transfers to the heat sink 3 through the sub-mount 2, thereby uniforming the temperature of each laser diode of the laser array chip 1 (Fig. 6, [0034]) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ide as modified by forming each of the pair of second electrodes with smaller areas than the first electrodes in order to more easily transfer heat generated by the laser diodes in the center of the laser array away from the laser to a heat sink . Fig. 7 of Ida Fig. 6 of Ineaga Regarding claim 2, Ide as modified disclose: wherein each of the pair of second electrodes is equal in length to the first electrode in the first direction, and each of the pair of second electrodes is smaller in width than the first electrode in the second direction (Inenaga discloses that the widths of the electrodes 8 of the laser diodes located in each end of the laser array chip 1, that is, in the most outside thereof are the smallest. In other words, among contacting areas between the electrodes 8 of the laser diode and electrodes 31 of the sub-mount 2, the contacting area at a center position is larger than that at the end positions . Therefore, each of the pair of second electrodes is equal in length to the first electrodes in the first direction) (Inenaga, Fig. 6, [0034]) . Regarding claim 3, Ide as modified disclose: wherein the individual electrodes are equal in area to each other (individual electrodes 210a to 210e are equal in area) (see the rejection of claim 1) . Regarding claim 4, Ide as modified disclose: wherein the first mesa-stripe structure includes a plurality of first mesa-stripe structures, the first electrode is one first electrode, the one first electrode includes a plurality of sections equal in size to each other and equal in number to the first mesa-stripe structures, and each of the pair of second electrodes is smaller in area than each of the portions (see the rejection of claim 1) . Regarding claim 5, Ide as modified disclose: wherein the first mesa-stripe structure includes a plurality of first mesa-stripe structures, and the first electrode includes a plurality of first electrodes, separated (see the rejection of claim 1) . Regarding claim 6, Ide as modified do not disclose: wherein the first electrodes are equal in area to each other. However, In accordance with MPEP 2144.05 II, Optimization of Ranges: Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In the prior art the general conditions are disclosed, a semiconductor array device comprising a plurality of first electrodes each having an area, the contacting area of the electrodes at a center position (first electrodes) is larger than that at the end positions (second electrodes). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to obtain a workable range of values for the area of the first electrodes by routine experimentation. Regarding claim 7, Ide as modified do not disclose: wherein a closer one of the first electrodes to either of the pair of second electrodes is smaller in area. However, In accordance with MPEP 2144.05 II, Optimization of Ranges: Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In the prior art the general conditions are disclosed, a semiconductor array device comprising a plurality of first electrodes each having an area, the contacting area of the electrodes at a center position (first electrodes) is larger than that at the end positions (second electrodes). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to obtain a workable range of values for the area of the first electrodes by routine experimentation. Regarding claim 8, Ide as modified disclose: wherein the mesa-stripe structures are on an upper surface of the semiconductor substrate, the common electrodes are on a lower surface of the semiconductor substrate, the first electrode overlaps with the first mesa-stripe structure, and each of the pair of second electrodes overlaps with a closer one of the pair of second mesa-stripe structures (see the rejection of claim 1) . Regarding claim 9, Ide as modified disclose: wherein the mesa-stripe structures are on the upper surface of the semiconductor substrate, the common electrodes are in contact with the upper surface of the semiconductor substrate (Tojo, Fig. 3, [0072]) , the first electrode is adjacent to the first mesa-stripe structure, and each of the pair of second electrodes is adjacent to a closer one of the pair of second mesa-stripe structures (see the rejection of claim 1) . Regarding claim 10, Ide as modified disclose: the top portion of each of the pair of second electrodes is smaller in area than the top portion of the first electrode (see the rejection of claim 1). Ide as modified do not explicitly disclose: wherein each of the common electrodes bends upward from the upper surface of the semiconductor substrate and includes a bottom portion in contact with the upper surface and a top portion at a higher position than the bottom portion . The examiner takes official notice that an electrode that bends upward from the upper surface of the semiconductor substrate and includes a bottom portion in contact with the upper surface and a top portion at a higher position than the bottom portion was well known in the art before the time of filing . For example, see Okaka (US PG Pub 2016/0056614) electrode 6 (Fig. 2, [0019], [0036]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ide as modified by forming each of the common electrodes so that the electrodes bends upward from the upper surface of the semiconductor substrate and includes a bottom portion in contact with the upper surface and a top portion at a higher position than the bottom portion in order to increase the bonding area of the electrodes . Regarding claim 12, Ide as modified do not disclose: wherein the mesa-stripe structures further include a pair of third mesa-stripe structures sandwiching the first mesa-stripe structure and the pair of second mesa-stripe structures, the common electrodes further include a pair of third electrodes sandwiching the first electrode and the pair of second electrodes, and the pair of third electrodes are equal in area to or larger than the pair of second electrodes. However, In accordance with MPEP 2144.04 [R-6], Legal Precedent as Source of Supporting Rationale: As discussed in MPEP § 2144, if the facts in a prior legal decision are sufficiently similar to those in an application under examination, the examiner may use the rationale used by the court. Examples directed to various common practices which the court has held normally require only ordinary skill in the art and hence are considered routine expedients are discussed below. If the applicant has demonstrated the criticality of a specific limitation, it would not be appropriate to rely solely on case law as the rationale to support an obviousness rejection. MPEP 2144.04 [R-6] VI B, Duplication of Parts: In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a “web” which lies in the joint, and a plurality of “ribs” projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to add a pair of third mesa-stripe structures sandwiching the first mesa-stripe structure and the pair of second mesa-stripe structures since adding a pair of third mesa-stripe structures does not produce a new and unexpected result. Regarding claim 13, Ide as modified do not disclose: and a submount on which the semiconductor array device is mounted, the submount individual terminals and common terminals, each of the individual terminals being electrically connected to a corresponding one of the individual electrodes, each of the common terminals being electrically connected to a corresponding one of the common electrodes. Inenaga discloses: submount (2) on which the semiconductor array device is mounted , the submount comprising terminals (31) (Fig. 6, [0034]) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ide as modified by mounting the semiconductor array device on the submount and electrically connecting the individual electrodes to the individual terminals and the common electrodes to the common terminals in order to electrically bias the laser array and to dissipate heat from the laser array. Regarding claim 14, Ide as modified disclose: wherein the common terminals include a first terminal opposed to and bonded to the first electrode, and a pair of second terminals opposed to and bonded to the respective pair of second electrodes, and each of the pair of second terminals is smaller in area than the first terminal (Inenaga, Fig. 6, [0034]) . Regarding claim 15, Ide as modified disclose: wherein each of the pair of second terminals is smaller than the first terminal in a bonding area with the corresponding one of the common electrodes (Inenaga, Fig. 6, [0034]) . Regarding claim 16, Ide as modified disclose: further comprising a wire electrically connecting each of the individual terminals and the corresponding one of the individual electrodes, each of the common terminals and the corresponding one of the common electrodes are opposed to and electrically connected to each other (Inenaga, Fig. 6, [0032]) . Regarding claim 17, Ide as modified disclose: wherein each of the individual terminals and the corresponding one of the individual electrodes are opposed to and electrically connected to each other, and each of the common terminals and the corresponding one of the common electrodes are opposed to and electrically connected to each other (Inenaga, Fig. 6, [0034]) . Regarding claim 18, Ide as modified do not disclose: wherein the mesa-stripe structures further include a pair of third mesa-stripe structures sandwiching the first mesa-stripe structure and the pair of second mesa-stripe structures, the common electrodes further include a pair of third electrodes sandwiching the first electrode and the pair of second electrodes, each of the pair of third electrodes is larger in area than either of the pair of second electrodes, and the individual terminals are not electrically connected to the active layer of either of the pair of third mesa-stripe structures. However, In accordance with MPEP 2144.04 [R-6], Legal Precedent as Source of Supporting Rationale: As discussed in MPEP § 2144, if the facts in a prior legal decision are sufficiently similar to those in an application under examination, the examiner may use the rationale used by the court. Examples directed to various common practices which the court has held normally require only ordinary skill in the art and hence are considered routine expedients are discussed below. If the applicant has demonstrated the criticality of a specific limitation, it would not be appropriate to rely solely on case law as the rationale to support an obviousness rejection. MPEP 2144.04 [R-6] VI B, Duplication of Parts: In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a “web” which lies in the joint, and a plurality of “ribs” projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to add a pair of third mesa-stripe structures sandwiching the first mesa-stripe structure and the pair of second mesa-stripe structures since adding a pair of third mesa-stripe structures does not produce a new and unexpected result. Regarding claim 19, Ide as modified disclose: wherein the common terminals include a first terminal opposed to and bonded to the first electrode, a pair of second terminals opposed to and bonded to the respective pair of second electrodes, and third terminals opposed to and bonded to the respective pair of third electrodes (see the rejection of claim 18) . Claim s 11 are rejected under 35 U.S.C. 103 as being unpatentable over Ide et al. (US PG Pub 2015/0236472) in view of Tojo et al. (US PG Pub 2004/0206975), Inenaga (US PG Pub 2008/0317082) and Hosoba (US PG Pub 2007/0177645). Regarding claim 11, Ide as modified do not disclose: further comprising a buried layer burying each of the mesa-stripe structures on both sides. Hosoba discloses: current blocking layer 19 is formed on both sides of the ridge portion (Fig. 1, [0035]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ide as modified by forming a buried layer on both sides of the mesa stripe in order to reduce current spreading in the laser device. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Maeda et al. (US PG Pub 2006/0192209) disclose: a n optical integrated semiconductor light emitting device with improved light emitting efficiency is provided by preventing leak current from flowing through a high defect region of the substrate. The optical integrated semiconductor light emitting device includes: a substrate, in which in a low defect region made of crystal having a first average dislocation density, one or more high defect regions having a second average dislocation density higher than the first average dislocation density are included; and a Group III-V nitride semiconductor layer which is formed on the substrate, has a plurality of light emitting device structures, and has a groove in the region including the region corresponding to the high defect region (high defect region) (Abstract). Iga et al. (US PG Pub 2010/0254421) disclose: w ithin a semiconductor laser device, mounting a semiconductor laser element array of multi-beam structure on a sub-mount, the semiconductor laser element array of multi-beam structure comprises one piece of a semiconductor substrate 11; a common electrode 1, which is formed on a first surface of the semiconductor substrate; a semiconductor layer 2, which is formed on the other surface of the semiconductor substrate, and has a plural number of light emitting portions 7 within an inside thereof; a plural number of anode electrodes 3 of a second conductivity type, which are formed above the plural number of light emitting portions, respectively; and a supporting portion 25, which is provided outside a region of forming the light emitting portions, wherein on one surface of the sub-mount is connected an electrode 3 of the semiconductor laser element array through a solder 4, and that solder 4 is formed to cover a supporting portion and an electrode neighboring thereto, and further on the electrode 3 is formed a groove portion 9 between the supporting portion 25 neighboring and the light emitting portions 7 (Abstract) . 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