Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 23, 2026 has been entered.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2023-0085190, filed on June 30, 2023, and parent Application No. KR10-2022-0120482, filed on September 23, 2022.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant's arguments filed January 23, 2026 have been fully considered but they are not persuasive.
In page 2 of the remarks, Applicant thanks Examiner for the interview with Applicant's representative on January 13, 2026 in which changes to the claims and the applied art were discussed. Clarifications are present in the amended claims submitted with the remarks.
In page 3 of the remarks, Applicant states that claims 1-7, 9-13, 15-22, and 24-27 were previously rejected under 35 U.S.C. § 112(b) ("112(b)") as being indefinite, with Applicant stating the following rejections in a table in pages 3-7 of the remarks: claims 1 and 22 using a term 'counting data' in claim 1, line 3, and the term “normal refresh command” in claim 1, line 6.
Examiner evaluates both of the previous rejections under 112(b) and provides a statement for each of the previous rejections and whether the comments on the right side of the table overcome the rejection. The amended claim 1 recites 'counting data' represents a number of row accesses, with Applicant providing support in the Specification in paragraphs [0029], [0034], and [0039] to support the term, along with utilizing MPEP § 2173.02 as a person of ordinary skill understanding that a row-hammer control circuit is capable of reading the counting data from a row indicated by a row address according to an active command.
However, it is not enough that a person of ordinary skill in the art would understand how the row-hammer control circuit reads ‘counting data’ in the claims of the invention, nor does the Specification provide a standard on which component generates the ‘counting data’ function, with the Broadest Reasonable Interpretation (“BRI”) of this limitation being that a component of the memory device must somehow generate counting data, which is not described in sufficient detail in the Specification. The same rationale goes for 'normal refresh command' of the independent claims, as it is not enough that a person of ordinary skill in the art would understand the meaning of 'normal refresh command' in the claims of the invention, despite paragraph [0031] reciting normal refresh command as a periodic refresh command. The independent claims have been amended to now recite “periodic refresh command” instead of “normal refresh command”, but the Specification does not provide a standard as to what a periodic refresh is, as to what a period is for a periodic refresh to occur, and in the case of “non-periodic refresh command” also described in the amended claims, what constitutes as a non-periodic refresh, as there is no other description other than a “refresh management command” (RFM) provided. Although the RFM is defined as a command provided from a memory controller for a target refresh operation generated by the memory device itself in paragraph [0033], the non-periodic refresh command itself remains unclear in the Specification. As a result, the rejections previously under 112(b) for 'counting data' of claims 1, 11, 17, 19, and 22 are maintained, and 'periodic refresh command' and ‘non-periodic refresh command’ of the independent claims are rendered indefinite in light of the Specification in response to the amendment made by the Applicant.
In page 7 of the remarks, Applicant states that claims 8, 12, and 17-18 have been previously rejected under 35 U.S.C. § 112(a) ("112(a)") as failing to comply with the written description requirement. In claim 1, Applicant states that the limitation of “[...] and a target command generation circuit configured to generate the target refresh command based on the normal refresh command” is stated, and while stated in paragraphs [0076], [0101], and [0117], the Specification does not state how this method is achieved or how a person of ordinary skill in the art can make the invention, and the drawings of Figs. 6B and 8B do not contain sufficient clarification as how the method is achieved. Applicant states that a person of ordinary skill would have no problem making the claimed invention by programming a memory controller (or its claimed components) to generate a target refresh command based on a normal refresh command. Furthermore, claim 12 was rejected for the limitation of “occurs a preset number of times” does not contain enough support in the Specification to describe how the invention of the Applicant achieves the function, or a person of ordinary skill in the art to understand or make the invention, with paragraph [0060] merely restating the claim limitation without any clarification as to what the phrase represents. Applicant states that Fig. 6B, and paragraphs [0060] and [0071]. Finally, claim 17 has been rejected under 112(a) for the limitation of “updating the counting data as a first set value and storing the row address into the first queue [...]” does not contain enough support in the Specification to describe how the invention of the Applicant achieves the function, citing paragraph [0041] of the Specification, but stating that a person of ordinary skill in the art will not understand how this function is achieved to create the invention. Applicant states paragraphs [0097]-[0098] and Fig. 8A of the Specification, and simply states that person of ordinary skill in the art would have no problem making the claimed invention by programming a memory controller to update the counting data as a first set value and storing the row address into a first queue, when the value of the counting data is less than the second set value but greater than the first set value.
Examiner disagrees with the Applicant on the three arguments presented in the table of 112(a) rejections and responses in pages 4-8 of the remarks. Although MPEP § 2161 specifies that there are three requirements of 112(a) are separate and distinct from each other, along with if a claim has written description in the invention and were enabled, it is not enough that one skilled in the art could write a program to achieve the claimed function because the specification must explain how the inventor intends to achieve the claimed function to satisfy the written description requirement. See, e.g., Vasudevan Software, Inc. v. MicroStrategy, Inc., 782 F.3d 671, 681-683, 114 USPQ2d 1349, 1356, 1357 (Fed. Cir. 2015).
In pages 9-17 of the remarks, Applicant states that a rejection under 35 U.S.C. § 102 ("102"), and that if a cited reference does not disclose each and every element of the claimed invention, then the reference fails to anticipate the claimed invention, and thus, the claimed invention is distinguishable over the cited reference. Claims 1-3, 5-6, 8, 10-11, 14-16, 19, 21-23, and 25-26 were rejected under 102(a)(2) as being anticipated by Hong. Applicant recites the amended independent claim 1, and claims 11, 17, 19, and 22 have been amended to recite “each coupled to row-hammer cells storing counting data […]”, “[…] read the counting data from the row-hammer cells […]”, and recite “non-periodic” and “periodic” refresh commands, with Applicant's [0029], [0031], and [0033] providing alleged support for the amendments in the independent claims. In particular, Applicant refers to paragraph [0033] of the Specification to state a target command generation circuit 175 to generate a target refresh command TREF whenever a number of inputs of the normal refresh command REF reaches a predetermined number of times or reaches a certain condition, with refresh management command RFM being provided from the memory controller for a target refresh operation, and TREF generated by memory device 100 itself for the operation. Applicant also states that paragraph [0040] of Hong, with refresh control circuit 290 receiving a row address RA, calculating a victim row address VRA based on row address RA, calculating refresh row address REF_RA to be refreshed based on VRA, and transfer the REF_RA to the row decoder 250, and refresh control circuit 290 including a row hammer refresh control circuit 291 that calculates the VRA, and in some embodiments, the refresh control circuit 290 further includes a normal refresh control circuit 292 to calculate a row address NRA on which a normal refresh operation is to be performed, and when refresh mode REF_MODE indicates a normal refresh mode, refresh row address selector 293 can output the row address NRA from normal refresh control circuit 292 as the REF_RA. When REF_MODE indicates a hammer refresh mode, refresh row address selector 293 may output the row address BRA from row hammer refresh control circuit 291 as REF_RA, showing Fig. 2 of Hong in page 14 of the remarks. Applicant then refers to Fig. 7 and paragraph [0068] of Hong (shown in page 15 of the remarks), as a refresh control circuit 700 includes a row address storage unit 760 that stores the row address, in particular describing count values CNT1, CNT2, and CNTN stored in refresh control circuit 700, having the maximum count value determined by the comparator 750 as a detection row address, and outputs the stored detection row address in response to a predetermined instruction (e.g., REF). Hong describes the refresh instruction REF for instruction the normal refresh or the hammer refresh. Applicant states, however, that Hong fails to teach or suggest the features of “a memory cell region including a plurality of rows each coupled to row-hammer cells storing counting data […]” and “after the active command is generated, read the counting data from the row-hammer cells of a row […]”. Furthermore, Applicant states that Hong’s description of paragraph [0045], in particular, “register 320_j having a maximum count value […] row address storage circuit 360 may store the row address having the maximum count value detected by the comparator 350 […]”, allegedly states that Hong fails to disclose the limitations of the independent claims, and requests withdrawal of the foregoing rejection of claims 1-3, 5-6, 8, 10-11, 14-16, 19, 21-23, and 25-26. Claims 8, 14, and 23 have been cancelled in this Application.
Examiner disagrees with the Applicant regarding the independent claims and the reference not disclosing or suggesting all of the limitations of the independent claims, as the comparator of Figs. 3 and 7 are used to select a register with a maximum count value from REG/CNT control circuits, and the components of Figs 3 and 7, including row address storage circuit 360/760 storing a row address with the highest count value, or the most hits being read to, all of which are taught by Hong in paragraphs [0044]-[0045], [0062], and [0068]. In particular, the limitation of ‘[…] and a row control circuit configured to refresh one or more rows corresponding to the row-hammer address according to the refresh management command or the target refresh command’ is disclosed by Hong in paragraph [0045], wherein a refresh (REF) instruction is shown in Fig. 3 is shown in storage circuit 360, which then determines a VRA to be refreshed, corresponding to a target refresh command of the applicant. As a result, Examiner maintains the rejections of the previous OA, and the independent claims 1, 11, 17, 19, and 22 remain rejected by Hong under 102(a)(2).
In pages 18-20 of the remarks, Applicant states that a rejection under 35 U.S.C. § 103 ("103"), and that a test for determining if a claim is rendered obvious by one or more references for purposes of a rejection under 103 as set forth in KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), and as stated in MPEP § 2143.03, to ascertain the differences between the prior art and the claims at issue, "all claim limitations must be considered" because "all words in a claim must be considered in judging the patentability of that claim against the prior art". In re Wilson, 424 F.2d 1382, 1385. Furthermore, as set forth in KSR International Co. v. Teleflex Inc., quoting from In re Kahn, 441 F.3d 977, 988 (CA Fed. 2006), "rejections on obviousness grounds cannot be sustained by mere conclusionary statements; instead, there must be some articulated reasonings with some rational underpinning to support the legal conclusion of obviousness". Applicant states that claims 4, 9, 12-13, and 24 stand rejected under 103 as allegedly being unpatentable over Hong in view of Lee-1; claims 7, 20, and 27 stand rejected under 103 as allegedly being unpatentable over Hong in view of Penney, with no other reasonings provided; claim 17 is rejected under 103 as allegedly being unpatentable over Hong in view of Lee-2, using the amendments made to claim 17, resembling similar amendments made to independent claim 1 above in the 35 U.S.C. 102 rejections above; and claim 18 is rejected under 103 as allegedly being unpatentable over Hong in view of Lee-2 in further view of Penney. Applicant states that any of Lee-1, Penney, and Lee-2 fails to cure the deficiencies of Hong, as Lee-1 describes a refresh management signal RFMS provided from a controller, and Penney and Lee-2 describes a row hammer refresh signal (RHR) generate inside the memory device, but states that all fail to teach the feature of 'selecting a row-hammer address by managing a first queue and second queue according to the refresh management command RFM [...]', and all prior art of record fail to teach the amended independent claim 1.
Examiner disagrees with the Applicant, as the reference of Hong teaches the limitations of ‘selecting a row-hammer address by managing a first queue and second queue’ limitation of the Applicant, and the limitations are also stated by Hong in the independent claim 1, which are equivalent to the amendments made in independent claim 17. Furthermore, Examiner maintains the rejections to the dependent claims of As a result, Examiner maintains the rejections of the previous OA, with claims 4, 9, 12-13, and 24 being unpatentable over Hong in view of Lee-1, claims 7, 20, and 27 being unpatentable over Hong in view of Penney, claim 17 as being unpatentable over Hong in view of Lee-2, and claim 18 as unpatentable over Hong in view of Lee-2 in further view of Penney. The independent claims 1, 11, 17, 19, and 22 remain rejected by Hong, and the respective dependent claims maintains their rejections from the previous OA.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7, 9-13, 15-22, and 24-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, the term “counting data” in claim 1, line 11 is stated as being read from a row indicated by a row address. The claimed function identified above is not performed by any structure recited in the claim. The BRI of the functional language is that the memory device/system must somehow perform this function. The boundaries of the functional language are unclear because the claim does not provide a discernable boundary on what performs the function. The recited function does not follow from the structure recited in the claim, i.e., the control circuit, so it is unclear whether the function requires some other structure or is simply a result of operating the memory device/system in a certain manner.
The term “periodic refresh command” in claim 1, line 6 is a relative term which renders the claim indefinite. The term “periodic refresh command” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The Specification does not provide a standard as to what a periodic refresh is, as to what a period is for a periodic refresh to occur, as to whether a certain amount of time to pass to trigger a periodic refresh, or how many processing cycles must occur to trigger a period.
The term “non-periodic refresh command” in claim 1, line 5 is a relative term which renders the claim indefinite. The term “non-periodic refresh command” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The Specification does not describe what constitutes as a non-periodic refresh, as there is no other description other than a “refresh management command” (RFM) provided. Although the RFM is defined as a command provided from a memory controller for a target refresh operation generated by the memory device itself in paragraph [0033], the non-periodic refresh command itself remains unclear in the Specification.
In claims 2-7, and 9-10, dependent claims of an independent claim inherit the deficiencies of the independent claim that are relied upon, with the independent claim being claim 1. Therefore, claims 2-10 are rejected for the same reasons as claim 1, as seen above.
In claim 11, the independent claim shares the same deficiencies as in claim 1 with regards to the term ‘counting data’. Therefore, claim 11 is rejected for the same reasons as claim 1 above.
In claims 12-13, and 15-16, dependent claims of an independent claim inherit the deficiencies of the independent claim that are relied upon, with the independent claim being claim 11. Therefore, claims 11-16 are rejected for the same reasons as claim 1, as seen above.
In claim 17, the independent claim shares the same deficiencies as in claim 1 with regards to the term ‘counting data’. Therefore, claim 17 is rejected for the same reasons as claim 1 above.
In claim 18, dependent claims of an independent claim inherit the deficiencies of the independent claim that are relied upon, with the independent claim being claim 17. Therefore, claim 18 are rejected for the same reasons as claim 1, as seen above.
In claim 19, the independent claim shares the same deficiencies as in claim 1 with regards to the term ‘counting data’. Therefore, claim 19 is rejected for the same reasons as claim 1 above.
In claims 20-21, dependent claims of an independent claim inherit the deficiencies of the independent claim that are relied upon, with the independent claim being claim 19. Therefore, claims 20-21 are rejected for the same reasons as claim 19, as seen above.
In claim 22, the independent claim shares the same deficiencies as in claim 1 with regards to the term ‘counting data’. Therefore, claim 22 is rejected for the same reasons as claim 1 above.
In claims 24-27, dependent claims of an independent claim inherit the deficiencies of the independent claim that are relied upon, with the independent claim being claim 22. Therefore, claims 23-27 are rejected for the same reasons as claim 22, as seen above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-6, 10-11, 15-16, 19, 21-22, and 25-26 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hong (US 20230298655 A1).
Regarding claim 1, Hong discloses a ‘memory device comprising: a memory cell region including a plurality of rows each coupled to row-hammer cells storing counting data representing a number of accesses to a corresponding row’ ([0044] Fig. 1, memory device 110 includes memory cell array 111, which includes memory cell rows, with paragraph [0025] describing a memory cell array as containing a plurality of rows. Paragraph [0048] states that even when row address A2 is stored in a register 320 of Fig. 3, is not replaced and maintained, and no intensive access has occurred, a row address adjacent to row address A2 is refreshed. [0041]-[0042] Refresh control circuit 290 (Fig. 2)/300 (Fig. 3), which can be a rowhammer refresh control circuit, contains a plurality of control/register control circuits 340, each containing a register 320 and a count 330, with each count 330 corresponding to a number of hits/accesses to its respective register 320. Each control/register control circuit 340 corresponds to a row-hammer cell storing counting data of the Applicant.);
‘a command decoder configured to decode an internal command from a memory controller and generate an active command, a non-periodic refresh command, and a periodic refresh command based on the internal command;’ ([0033] Fig. 2, instruction decoder 221 generates control signal by decoding an instruction CMD received from a memory controller 120 in Fig. 1 so that a memory device may perform a refresh operation, in which a normal refresh 290 and rowhammer refresh 291 is generated, with paragraph [0040] stating that a row address VRA of a rowhammer refresh circuit 291 and a row address NRA from normal refresh circuit 292 can be outputted simultaneously. Rowhammer refresh 291 corresponds to a non-periodic refresh commends, and normal refresh 290 corresponds to a periodic refresh. The instruction CMD can include an activate instruction to switch a target row of the memory cell array 111 to an active state to read or write data from target row of memory cell array 111, thus when instruction CMD is decoded, an active command is generated as well.);
‘a target command generation circuit configured to generate a target refresh command by counting a number of inputs of the periodic refresh command’ ([0040] Fig. 2, normal refresh control circuit 292 calculates a row address NRA based on a normal refresh operation, and along with paragraph [0058] stating that a predetermined period is set for refresh when a predetermined condition of a maximum count value is exceeded, corresponds to a target refresh operation generated by a target command generation circuit based on a periodic refresh command of the applicant.);
‘a row-hammer control circuit including first and second queues, and configured to’ ([0041] Fig. 7, rowhammer refresh control circuit 700, with RA storage circuit 760 corresponding to first queue, and REG/CNT control circuits 740_1 through 740_N corresponding to second queue.):
‘after the active command is generated, read the counting data from the row-hammer cells of a row indicated by a row address, among the plurality of rows’ ([0027] Read instructions is done for reading operation of a target memory cell of a row, indicated by a row address, and a read instruction corresponds to an active command of the applicant. [0062] Each of the REG/CNT control circuits 740 may store a row address and a counter, with counters 730_1 through 730_N count number of hits for an incoming row address, which is compared to "from an initial value (e.g., zero)", or a previous number stored in the CNT portion of a control circuit in Fig. 7, as stated in paragraph [0044], as Fig. 7 describes most components that are also in Fig. 3.),
‘store the row address in the first queue according to a comparison result of the counting data and a first set value’ ([0068] Row address storage circuit 760 stores a row address with a maximum count value determined by comparator 750, after the incoming row address RA has been put into a REG/CNT control circuit 740, wherein the maximum value is the first value of the applicant. Furthermore, a replacement row address surpasses the previous maximum value by a count of 1, and in turn, remain in the RA storage circuit 760, corresponding to updating a first set value when a value of counting data is greater than the previous first set value.),
‘store the row address in the second queue according to a comparison result of the counting data and a second set value’ ([0044] "In some embodiments, the counter/register control circuit 340_p may store the incoming row address RA in the corresponding register 320_p again", which means that the same row address can be stored multiple times in different control circuits according to the Hong. [0062] Counters of 730 count the number of hits for incoming row addresses, and paragraph [0040] clarifies that based on a minimum count value among counters 730 for registers, a row address with the minimum value may be replaced with that of the incoming row address RA, wherein the minimum count corresponds to a second set value of the applicant. Paragraph [0047] further explains that when a row stored is stored in a REG/CNT control circuit 340/740, count value is increased by one, indicating that the incoming row address has a higher count value than the previous minimum count value.),
‘and select, as a row-hammer address according to the non-periodic refresh command or the target refresh command, one of row addresses stored in the first queue and the second queue’ ([0045] Comparator 350/750 selects a row address stored in a register of any control circuit with a maximum value, and following the scenario in which the same address can be stored multiple times in paragraph [0044], will select the one address with a maximum count value stored in any REG/CNT control circuit 740 as a row address with a maximum count value into storage circuit 760, and calculate the victim row address (VRA) utilizing an address in both a REG/CNT control circuit 340/740 and in RA storage circuit 360/760 to be calculated and refreshed, which corresponds to a target refresh command of the applicant refreshing a row address in both the first and second queue.);
‘and a row control circuit configured to refresh one or more rows corresponding to the row-hammer address according to the non-periodic command or the target refresh command’ ([0045] A refresh (REF) instruction is shown in Fig. 3 is shown in storage circuit 360, which then determines a VRA to be refreshed, corresponding to a target refresh command of the applicant.).
Regarding claim 2, Hong discloses the memory device of claim 1 as recited above. Hong also discloses ‘wherein the first set value is a maximum value among the counting data read from the plurality of rows’ ([0045] Fig. 7, row address storage circuit 760 stores an address with a maximum count value, wherein the maximum count value corresponds to a first set value of the applicant.),
‘and wherein the first queue is configured to have a single field for storing therein the row address corresponding to the maximum value’ ([0068] Fig. 7, comparator 750 selects a row address stored in a register of any REG/CNT control circuit 740 with a maximum count value, and stores the row address with the maximum count into RA storage circuit 760.).
Regarding claim 3, Hong discloses the memory device of claim 1 as recited above. Hong also discloses ‘wherein the second queue is configured to have a plurality of fields for respectively storing therein the row addresses indicating rows each corresponding to the counting data equal to or greater than the second set value’ ([0062] Register/counter control circuits 740 are multiple address circuits with different row addresses and counter values corresponding to hits in the row addresses, and the REG/CNT control circuits 740 are connected to a comparator 750, wherein REG/CNT control circuits corresponding to a second queue. In paragraph [0067], a minimum count value, corresponding to a second set value of the applicant, amongst the registers is stated by having RA control circuit transferring a row address RA to a REG/CNT control circuit 740 with the minimum value amongst the REG/CNT control circuits 740, and replace the previous row address. Paragraph [0047] further explains that when a row stored is stored in a REG/CNT control circuit 340/740, count value is increased by one, indicating that the incoming row address has a higher count value than the previous minimum count value.).
Regarding claim 5, Hong discloses the memory device of claim 1 as recited above. Hong also discloses ‘wherein the row-hammer control circuit is further configured to update the counting data as the first set value when a value of the counting data is greater than the first set value’ ([0044] "In some embodiments, the counter/register control circuit 340_p may store the incoming row address RA in the corresponding register 320_p again", indicating that the same row address can be stored multiple times with the counter value for the register increasing by one each time the same address is 'replaced'. A row address already in RA storage circuit that has the maximum count amongst the registers in REG/CNT control circuits 740 can have its count increase by 1, or have a replacement row address surpass the previous maximum value by a count of 1, and in turn, remain in the RA storage circuit 760, corresponding to updating a first set value when a value of counting data is greater than first set value.),
‘wherein the row-hammer control circuit stores the row address into the first queue when the value of the counting data is greater than the first set value’ ([0044] If a row address is already at a maximum value, the row address that is replacing the previous address is required to be greater than the previous maximum value by a value of one.),
‘and wherein the row-hammer control circuit stores the row address into the second queue when the value of the counting data is greater than or equal to the second set value’ ([0067] Minimum count value amongst the registers is stated by having RA control circuit transferring a row address RA to a REG/CNT control circuit 740 with the minimum value amongst the REG/CNT control circuits 740, and replace the previous row address with an address of a higher count value than a previous minimum value, which corresponds to storing a row address into the second queue with a value greater than the previous second set value of the applicant.).
Regarding claim 6, Hong discloses the memory device of claim 1 as recited above. Hong also discloses ‘wherein the row-hammer control circuit selects: the row address stored in the second queue according to the non-periodic refresh command’ ([0057] Fig. 5, a row address stored in a register, which is also in REG/CNT control circuits 740, can be refreshed by a refresh control circuit 500, which corresponds to a non-periodic refresh command of the applicant.),
‘and the row address stored in the first queue according to the target refresh command’ ([0057] Victim row address in RA storage circuit 760 in Fig. 7 may be a row address to be refreshed according to a target row address of a rowhammer refresh, corresponding to a target refresh command of the applicant.).
Regarding claim 10, Hong discloses the memory device of claim 1 as recited above. Hong also discloses ‘a counting management circuit configured to update the counting data according to the active command and configured to initialize the counting data after the refreshing’ ([0064] Replacement control circuit 780 receives count values from counters and determines replacement based on a minimum count value of counters 730. [0069] Memory device may initialize registers 720 and counters after refreshing a victim row.).
Regarding claim 11, Hong discloses similar limitations also present in independent claim 1 above, and also discloses the additional limitations of ‘an operating method of a memory device including a plurality of rows each coupled to row-hammer cells storing counting data representing a number of accesses to a corresponding row, the operating method comprising: generating an active command, a non-periodic refresh command or a periodic refresh command by decoding an internal command from a memory controller;’ (Paragraph [0048] states that even when row address A2 is stored in a register 320 of Fig. 3, is not replaced and maintained, and no intensive access has occurred, a row address adjacent to row address A2 is refreshed. [0041]-[0042] Refresh control circuit 290 (Fig. 2)/300 (Fig. 3), which can be a rowhammer refresh control circuit, contains a plurality of control/register control circuits 340, each containing a register 320 and a count 330, with each count 330 corresponding to a number of hits/accesses to its respective register 320. Each control/register control circuit 340 corresponds to a row-hammer cell storing counting data of the Applicant. [0033] Fig. 2, instruction decoder 221 generates control signal by decoding an instruction CMD received from a memory controller 120 in Fig. 1 so that a memory device may perform a refresh operation, in which a normal refresh 290 and rowhammer refresh 291 is generated, with paragraph [0040] stating that a row address VRA of a rowhammer refresh circuit 291 and a row address NRA from normal refresh circuit 292 can be outputted simultaneously. The instruction CMD can include an activate instruction to switch a target row of the memory cell array 111 to an active state to read or write data from target row of memory cell array 111, thus when instruction CMD is decoded, an active command is generated as well. Rowhammer refresh 291 corresponds to a non-periodic refresh commends, and normal refresh 290 corresponds to a periodic refresh.);
‘updating the counting data as a first set value and storing the row address into a first queue, when a value of the counting data is greater than the first set value’ ([0068] Row address storage circuit 760 stores a row address with a maximum count value determined by comparator 750, after the incoming row address RA has been put into a REG/CNT control circuit 740, wherein the maximum value is the first value of the applicant. [0044] "In some embodiments, the counter/register control circuit 340_p may store the incoming row address RA in the corresponding register 320_p again", indicating that the same row address can be stored multiple times with the counter value for the register increasing by one each time the same address is 'replaced'. A row address already in RA storage circuit that has the maximum count amongst the registers in REG/CNT control circuits 740 can have its count increase by 1, or have a replacement row address surpass the previous maximum value by a count of 1, and in turn, remain in the RA storage circuit 760, corresponding to updating a first set value when a value of counting data is greater than the previous first set value.);
‘storing the row address into a second queue when the value of the counting data is less than or equal to the first set value but greater than or equal to a second set value’ ([0044] "In some embodiments, the counter/register control circuit 340_p may store the incoming row address RA in the corresponding register 320_p again", which means that the same row address can be stored multiple times in different control circuits according to the Hong. [0062] Counters of 730 count the number of hits for incoming row addresses, and paragraph [0040] clarifies that based on a minimum count value among counters 730 for registers, a row address with the minimum value may be replaced with that of the incoming row address RA, wherein the minimum count corresponds to a second set value of the applicant. Paragraph [0047] further explains that when a row stored is stored in a REG/CNT control circuit 340/740, count value is increased by one, indicating that the incoming row address has a higher count value than the previous minimum count value. A comparator 750 requires a register to exceed the maximum value in order to be in the RA storage circuit 760, and when a register is inserted into a REG/CNT storage circuit, but does not get stored into a RA storage circuit 760, it corresponds to the register count value being less than the first set value of the applicant, which is treated as a maximum value in both the applicant and Hong’s application.);
‘and refreshing, according to the non-periodic refresh command or the target refresh command, one or more rows corresponding to a selected row address of the row addresses stored in the first queue and the second queue’ ([0045] Comparator 350/750 selects a row address stored in a register of any control circuit with a maximum value, and following the scenario in which the same address can be stored multiple times in paragraph [0044], will select the one address with a maximum count value stored in any REG/CNT control circuit 740 as a row address with a maximum count value into storage circuit 760, and calculate the victim row address (VRA) utilizing an address in both a REG/CNT control circuit 340/740 and in RA storage circuit 360/760 to be calculated and refreshed, which corresponds to a target refresh command of the applicant refreshing a row address in both the first and second queue. [0045] A refresh (REF) instruction is shown in Fig. 3 is shown in storage circuit 360, which then determines a VRA to be refreshed, corresponding to a target refresh command of the applicant.).
Regarding claim 15, Hong discloses the operating method of claim 11 as recited above. Hong also discloses ‘refreshing, according to the non-periodic refresh command, the rows corresponding to the row address stored in the second queue’ ([0057] Fig. 5, a row address stored in a register, which is also in REG/CNT control circuits 740, can be refreshed by a refresh control circuit 500, which corresponds to a non-periodic refresh command of the applicant.);
‘and refreshing, according to the target refresh command, the rows corresponding to the row address stored in the first queue’ ([0057] Victim row address in RA storage circuit 760 in Fig. 7 may be a row address to be refreshed according to a target row address of a rowhammer refresh, corresponding to a target refresh command of the applicant.).
Regarding claim 16, Hong discloses the operating method of claim 11 as recited above. Hong also discloses ‘updating the counting data and writing back the updated counting data to the row indicated by the row address, according to the active command’ ([0064] Replacement control circuit 780 receives count values from counters and determines replacement based on a minimum count value of counters 730, which occurs through row addresses being determined throughout Fig. 7 and a write command, corresponding to the active command of the applicant.);
‘and initializing the counting data and writing back the initialized counting data to the row indicated by the selected row address’ ([0069] Memory device may initialize registers 720 and counters 730 after refreshing a victim row, in which a register that is indicated can be initialized.).
Regarding claim 19, Hong discloses similar limitations also present in independent claim 1 above, and also discloses the additional limitations of ‘an operating method of a memory device including a plurality of rows each coupled to row-hammer cells storing counting data representing a number of accesses to a corresponding row, the operating method comprising: generating an active command, a non-periodic refresh command or a periodic refresh command by decoding an internal command from a memory controller’ (Paragraph [0048] states that even when row address A2 is stored in a register 320 of Fig. 3, is not replaced and maintained, and no intensive access has occurred, a row address adjacent to row address A2 is refreshed. [0041]-[0042] Refresh control circuit 290 (Fig. 2)/300 (Fig. 3), which can be a rowhammer refresh control circuit, contains a plurality of control/register control circuits 340, each containing a register 320 and a count 330, with each count 330 corresponding to a number of hits/accesses to its respective register 320. Each control/register control circuit 340 corresponds to a row-hammer cell storing counting data of the Applicant. [0033] Fig. 2, instruction decoder 221 generates control signal by decoding an instruction CMD received from a memory controller 120 in Fig. 1 so that a memory device may perform a refresh operation, in which a normal refresh 290 and rowhammer refresh 291 is generated, with paragraph [0040] stating that a row address VRA of a rowhammer refresh circuit 291 and a row address NRA from normal refresh circuit 292 can be outputted simultaneously. The instruction CMD can include an activate instruction to switch a target row of the memory cell array 111 to an active state to read or write data from target row of memory cell array 111, thus when instruction CMD is decoded, an active command is generated as well. Rowhammer refresh 291 corresponds to a non-periodic refresh commends, and normal refresh 290 corresponds to a periodic refresh.);
‘updating the counting data as a first set value and storing the row address into a first queue, when a value of the counting data is greater than the first set value’ ([0068] Row address storage circuit 760 stores a row address with a maximum count value determined by comparator 750, after the incoming row address RA has been put into a REG/CNT control circuit 740, wherein the maximum value is the first value of the applicant. [0044] "In some embodiments, the counter/register control circuit 340_p may store the incoming row address RA in the corresponding register 320_p again", indicating that the same row address can be stored multiple times with the counter value for the register increasing by one each time the same address is 'replaced'. A row address already in RA storage circuit that has the maximum count amongst the registers in REG/CNT control circuits 740 can have its count increase by 1, or have a replacement row address surpass the previous maximum value by a count of 1, and in turn, remain in the RA storage circuit 760, corresponding to updating a first set value when a value of counting data is greater than the previous first set value.);
‘storing the row address into a second queue when the value of the counting data is greater than or equal to a second set value’ ([0044] "In some embodiments, the counter/register control circuit 340_p may store the incoming row address RA in the corresponding register 320_p again", which means that the same row address can be stored multiple times in different control circuits according to the Hong. [0062] Counters of 730 count the number of hits for incoming row addresses, and paragraph [0040] clarifies that based on a minimum count value among counters 730 for registers, a row address with the minimum value may be replaced with that of the incoming row address RA, wherein the minimum count corresponds to a second set value of the applicant. Paragraph [0047] further explains that when a row stored is stored in a REG/CNT control circuit 340/740, count value is increased by one, indicating that the incoming row address has a higher count value than the previous minimum count value. A comparator 750 requires a register to exceed the maximum value in order to be in the RA storage circuit 760, and when a register is inserted into a REG/CNT storage circuit, but does not get stored into a RA storage circuit 760, it corresponds to the register count value being less than the first set value of the applicant, which is treated as a maximum value in both the applicant and Hong’s application.);
‘refreshing, according to the non-periodic refresh command or a target refresh command, one or more rows corresponding to one of the row addresses stored in the first queue and the second queue’ ([0045] Comparator 350/750 selects a row address stored in a register of any control circuit with a maximum value, and following the scenario in which the same address can be stored multiple times in paragraph [0044], will select the one address with a maximum count value stored in any REG/CNT control circuit 740 as a row address with a maximum count value into storage circuit 760, and calculate the victim row address (VRA) utilizing an address in both a REG/CNT control circuit 340/740 and in RA storage circuit 360/760 to be calculated and refreshed, which corresponds to a target refresh command of the applicant refreshing a row address in both the first and second queue. [0045] A refresh (REF) instruction is shown in Fig. 3 is shown in storage circuit 360, which then determines a VRA to be refreshed, corresponding to a target refresh command of the applicant.).
Regarding claim 21, Hong discloses the operating method of claim 19 as recited above. Hong also discloses the limitations present in dependent claim 15 above.
Regarding claim 22, Hong discloses similar limitations also present in independent claim 1 above, and also discloses ‘a memory system comprising: a memory controller configured to provide an active command with a row address, or a periodic refresh command, or a non-periodic refresh command’ ([0026] Fig. 1, memory controller 120 can control a memory operation of memory device 110 in memory system 100, and the memory controller 120 can provide an instruction CMD and an address ADDR simultaneously.);
Regarding claim 25, Hong discloses the memory system of claim 22 as recited above. Hong also discloses the limitations present in dependent claim 5 above.
Regarding claim 26, Hong discloses the memory system of claim 22 as recited above. Hong also discloses the limitations present in dependent claim 6 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 9, 12-13, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Lee et al. (US 20240028221 A1), hereinafter Lee-1.
Regarding claim 4, Hong discloses the memory device of claim 1 as recited above. Hong does not appear to disclose, but Lee-1 teaches the limitation of ‘wherein the row-hammer control circuit is further configured to output an alert signal to an external device when the second queue is full’ ([0055] Hammer address queue stores one or more candidate addresses up to a first number, and when reached, an alert signal ALRT is provided to a memory controller 30 in response to the first number being reached, which corresponds to a second queue being full in the applicant as well and outputting an alert signal.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hong and Lee-1 before them, to include Lee-1’s ‘wherein the row-hammer control circuit is further configured to output an alert signal to an external device when the second queue is full’ in Hong’s memory device performing ‘read counting data from a row indicated by a row address according to an active command’, ‘select, as a row-hammer address according to a non-periodic refresh command or a target refresh command, one of the row addresses stored in the first queue and the second queue’, and other functions. One would have been motivated to make such a combination to increase efficiency by alerting a memory controller of a memory device to prevent overflowing of a queue, and a memory controller can apply a non-periodic refresh command to a bank array to refresh rows corresponding to a row address, as taught by Lee [0169].
Regarding claim 9, Hong discloses the memory device of claim 1 as recited above. Hong also discloses the limitations of ‘a first management circuit configured to update the counting data as the first set value and store the row address into the first queue, when a value of the counting data is greater than the first set value’ ([0068] Fig. 3 or 7, RA storage circuit 360/760 stores an address that contains a maximum count value amongst the registers in REG/CNT control circuit 340/740. [0044] A row address can be stored multiple times with the counter value for the register increasing by one each time the same address is 'replaced'. A row address already in RA storage circuit that has the maximum count amongst the registers in REG/CNT control circuits 740 can have its count increase by 1, or have a replacement row address surpass the previous maximum value by a count of 1, and in turn, remain in the RA storage circuit 760, corresponding to updating a first set value when a value of counting data is greater than the previous first set value.);
‘a second management circuit configured to store the row address into the second queue when the value of the counting data is greater than or equal to the second set value’ ([0050] Fig. 5, refresh control circuit 500 may contain a plurality of registers, and has a relation to a minimum count value, which corresponds to Fig. 3 or 7 having multiple registers and count values for each. [0067] Fig. 7, minimum count value amongst the registers is stated by having RA control circuit transferring a row address RA to a REG/CNT control circuit 740 with the minimum value amongst the REG/CNT control circuits 740, and replace the previous row address, which corresponds to storing a row address into the second queue with a value greater than or equal to the second set value of the applicant.);
‘and an output control circuit configured to select the row-hammer address according to the non-periodic refresh command or the target refresh command’ ([0040] Fig. 2, refresh row address selector selects and outputs a row address to be refreshed, in which a VRA that is selected to be refreshed corresponds to a target refresh command of the applicant. [0068] Fig. 7, victim RA calculator 770 can calculate a victim row address VRA and output a VRA.);
Hong does not appear to disclose, but Lee-1 teaches the limitation of ‘and configured to generate an alert signal when the second queue is full’ ([0055] Hammer address queue stores one or more candidate addresses up to a first number, and when reached, an alert signal ALRT is provided to a memory controller 30 in response to the first number being reached, which corresponds to a second queue being full in the applicant as well and outputting an alert signal.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hong and Lee-1 before them, to include Lee-1’s ‘and configured to generate an alert signal when the second queue is full’ in Hong’s memory device performing ‘read counting data from a row indicated by a row address according to an active command’, ‘select, as a row-hammer address according to a non-periodic refresh command or a target refresh command, one of the row addresses stored in the first queue and the second queue’, and other functions. One would have been motivated to make such a combination to increase efficiency by alerting a memory controller of a memory device to prevent overflowing of a queue, and a memory controller can apply a non-periodic refresh command to a bank array to refresh rows corresponding to a row address, as taught by Lee-1 [0169].
Regarding claim 12, Hong discloses the operating method of claim 11 as recited above. Hong does not appear to disclose, but Lee-1 teaches the limitation of ‘wherein the storing the row address into the second queue includes storing the row address into the second queue when the counting data being less than or equal to the first set value but greater than or equal to the second set value’ ([0067] Minimum count value amongst the registers is stated by having RA control circuit transferring a row address RA to a REG/CNT control circuit 740 with the minimum value amongst the REG/CNT control circuits 740, and replace the previous row address, which corresponds to storing a row address into the second queue with a value greater than the second set value of the applicant. [0062] A comparator 750 requires a register to exceed the maximum value in order to be in the RA storage circuit 760, and when a register is inserted into a REG/CNT storage circuit, but does not get stored into a RA storage circuit 760, it corresponds to the register count value being less than the first set value of the applicant, which is treated as a maximum value in both the applicant and Hong’s application.).
Hong does not appear to disclose, but Lee-1 teaches the limitation of ‘satisfies a predetermined condition’ ([0118]-[0119] Fig. 8, comparator 520 activates a store signal STR when count data is equal to or greater than a first reference number of times NTH1, and NTH1 be include or be a default reference number of times and multiples of the default reference number of times, and a default reference number of times corresponds to a predetermined condition of the Applicant.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hong and Lee-1 before them, to include Lee-1’s ‘occurs a preset number of times’ in Hong’s operating method of a memory device performing ‘reading counting data from a row indicated by a row address according to an active command’, ‘refreshing, according to a non-periodic refresh command or a target refresh command, one or more rows corresponding to a selected row address of the row addresses stored in the first queue and the second queue’, and other functions. One would have been motivated to make such a combination to increase efficiency by using the default value as a base value in order to determine addresses that are at risk of a rowhammer attack when count data of how many times a row address has been accessed exceeds the first reference number of times NTH1, as taught by Lee [0120].
Regarding claim 13, Hong discloses the operating method of claim 11 as recited above. Hong in view of Lee-1 teach the limitations also present in dependent claim 4 above.
Regarding claim 24, Hong discloses the memory system of claim 22 as recited above. Hong does not appear to disclose, but Lee-1 teaches the limitation of ‘wherein the memory device is further configured to generate an alert signal when the second queue is full’ ([0055] Hammer address queue stores one or more candidate addresses up to a first number, and when reached, an alert signal ALRT is provided to a memory controller 30 in response to the first number being reached, which corresponds to a second queue being full in the applicant as well and outputting an alert signal.),
‘and wherein the memory controller provides the non-periodic refresh command every preset time, or each time the active command is provided a preset number of times, or according to the alert signal’ ([0100] Control logic circuit provides refresh control circuit 400 with non-periodic refresh signal RFMS based on a non-periodic refresh command from the memory controller 30. [0146] Fig. 12, monitor logic 650a may transition an alert signal ALRT to first logic level in response to a hammer refresh operation after a predetermined time interval elapses from a time point, corresponding to providing a non-periodic refresh command every preset time of the applicant.),
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hong and Lee-1 before them, to include Lee-1’s ‘wherein the memory device is further configured to generate an alert signal when the second queue is full’ and ‘and wherein the memory controller provides the non-periodic refresh command every preset time, or each time the active command is provided a preset number of times, or according to the alert signal’ in Hong’s memory system performing ‘generate a target refresh command indicating row-hammer cells comprising one or more neighboring rows to a target row being refreshed by the normal refresh command’. One would have been motivated to make such a combination to increase efficiency by alerting a memory controller of a memory device to prevent overflowing of a queue, and a memory controller can apply a non-periodic refresh command to a bank array to refresh rows corresponding to a row address, as taught by Lee [0169], and to increase efficiency by having a time interval correspond to a precharge time tRP, a scheduler 55 applies a second command to a memory device, and when a clock signal reaches an edge, a non-periodic refresh command RFM is applied to the memory device, ensuring periodic refreshes to memory addresses, as taught by Lee [0223].
Claims 7, 20, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Penney et al. (US 11424005 B2), hereinafter Penney.
Regarding claim 7, Hong discloses the memory device of claim 1 as recited above. Hong also discloses ‘wherein the row-hammer control circuit selects: the row address stored in the second queue according to the non-periodic refresh command’ ([0057] Fig. 5, a row address stored in a register can be refreshed by a refresh control circuit 500, which corresponds to a non-periodic refresh command of the applicant.);
‘and the row address stored in the second queue, when the second queue is not empty’ ([0057] Fig. 5, a row address stored in a register can be refreshed by a refresh control circuit 500 when there is an empty register in REG/CNT control circuit 740, which corresponds to a non-periodic refresh command of the applicant.);
Hong does not appear to disclose, but Penney teaches the limitation of ‘while selecting the row address stored in the first queue, when the second queue is empty, according to the target refresh command’ ([Col. 13, lines 1-5] If Empty signal is active (where the targeted address queue 240 is empty), a current Pre_RXADD is provided for a refresh.);
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hong and Penney before them, to include Penney’s ‘and the row address stored in the first queue, when the second queue is empty, according to the target refresh command’ in Hong’s memory device performing ‘read counting data from a row indicated by a row address according to an active command’, ‘select, as a row-hammer address according to a non-periodic refresh command or a target refresh command, one of the row addresses stored in the first queue and the second queue’, and other functions. One would have been motivated to make such a combination to increase efficiency by means of having an Empty signal of a queue override a command signal RHR [row hammer refresh] to prevent suspension of automatic refresh of an auto-refresh address Pre_RXADD, ensuring that a portion of memory is always refreshed and safe from further attacks, as taught by Penney [Col. 10, line 60-Col. 11, line 14].
Regarding claim 20, Hong discloses the operating method of claim 19 as recited above. Hong also discloses ‘wherein the refreshing includes: refreshing, according to the non-periodic refresh command, the rows corresponding to the row address stored in the second queue’ ([0057] Fig. 5, a row address stored in a register can be refreshed by a refresh control circuit 500, which corresponds to a non-periodic refresh command of the applicant in a second queue.);
‘refreshing, according to the target refresh command, the rows corresponding to the row address stored in the second queue when the second queue is not empty’ ([0057] Fig. 5, a row address stored in a register can be refreshed by a refresh control circuit 500 when there is an empty register in REG/CNT control circuit 740, which corresponds to a non-periodic refresh command of the applicant.);
Hong does not appear to disclose, but Penney teaches the limitation of ‘and refreshing, according to the target refresh command, the rows corresponding to the row address stored in the first queue when the second queue is empty while refreshing’ ([Col. 13, lines 1-5] If Empty signal is active (where the targeted address queue 240 is empty), a current Pre_RXADD is provided for a refresh.);
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hong and Penney before them, to include Penney’s ‘and refreshing, according to the target refresh command, the rows corresponding to the row address stored in the first queue when the second queue is empty’ in Hong’s operating method of a memory device performing ‘reading counting data from a row indicated by a row address according to an active command’, ‘refreshing, according to a non-periodic refresh command or a target refresh command, one or more rows corresponding to one of the row addresses stored in the first queue and the second queue’, and other functions. One would have been motivated to make such a combination to increase efficiency by means of having an Empty signal of a queue override a command signal RHR [row hammer refresh] to prevent suspension of automatic refresh of an auto-refresh address Pre_RXADD, ensuring that a portion of memory is always refreshed and safe from further attacks, as taught by Penney [Col. 10, line 60-Col. 11, line 14].
Regarding claim 27, Hong discloses the memory system of claim 22 as recited above. Hong in view of Penney teach the limitations also present in dependent claim 7 above.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Lee et al. (US 20230420027 A1), hereinafter Lee-2.
Regarding claim 17, Hong discloses similar limitations also present in independent claims 1 and 11 above, and also discloses the additional limitations ‘an operating method of a memory device including a plurality of rows each coupled to row-hammer cells storing counting data representing a number of accesses to a corresponding row, the operating method comprising: generating an active command, a non-periodic refresh command or a periodic refresh command by decoding an internal command from a memory controller;’ ([0033] Fig. 2, instruction decoder 221 generates control signal by decoding an instruction CMD received from a memory controller 120 in Fig. 1 so that a memory device may perform a refresh operation, in which a normal refresh 290 and rowhammer refresh 291 is generated, with paragraph [0040] stating that a row address VRA of a rowhammer refresh circuit 291 and a row address NRA from normal refresh circuit 292 can be outputted simultaneously. The instruction CMD can include an activate instruction to switch a target row of the memory cell array 111 to an active state to read or write data from target row of memory cell array 111, thus when instruction CMD is decoded, an active command is generated as well.);
‘storing the row address into a second queue when a value of the counting data is greater than or equal to a second set value’ ([0044] "In some embodiments, the counter/register control circuit 340_p may store the incoming row address RA in the corresponding register 320_p again", which means that the same row address can be stored multiple times in different control circuits according to the Hong. [0062] Counters of 730 count the number of hits for incoming row addresses, and paragraph [0040] clarifies that based on a minimum count value among counters 730 for registers, a row address with the minimum value may be replaced with that of the incoming row address RA, wherein the minimum count corresponds to a second set value of the applicant. Paragraph [0047] further explains that when a row stored is stored in a REG/CNT control circuit 340/740, count value is increased by one, indicating that the incoming row address has a higher count value than the previous minimum count value.);
‘and refreshing, according to a non-periodic refresh command or a target refresh command, one or more rows corresponding to one of the row addresses stored in the first queue and the second queue’ ([0045] Comparator 350/750 selects a row address stored in a register of any control circuit with a maximum value, and following the scenario in which the same address can be stored multiple times in paragraph [0044], will select the one address with a maximum count value stored in any REG/CNT control circuit 740 as a row address with a maximum count value into storage circuit 760, and calculate the victim row address (VRA) utilizing an address in both a REG/CNT control circuit 340/740 and in RA storage circuit 360/760 to be calculated and refreshed, which corresponds to a target refresh command of the applicant. [0045] A refresh (REF) instruction is shown in Fig. 3 is shown in storage circuit 360, which then determines a VRA to be refreshed, corresponding to a target refresh command of the applicant.).
Hong does not appear to disclose, but Lee-2 teaches the limitation of ‘updating the counting data as a first set value and storing the row address into a first queue, when the value of the counting data is less than the second set value but greater than the first set value’ ([0048] Fig. 3, incoming row address may be put into a queue 340 when a count value is greater than a second threshold but does not reach the first threshold, with paragraph [0042] stating that a queue 340 can store an aggressor row address ARA, that being one address, corresponding to a first queue of the applicant. In Lee-2, second threshold corresponds to first set value, where a count of row address needs to exceed a second threshold, and first threshold corresponds to a second set value.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hong and Lee-2 before them, to include Lee-2’s ‘updating the counting data as a first set value and storing the row address into a first queue, when the value of the counting data is less than the second set value but greater than the first set value’ in Hong’s operating method of a memory device performing ‘reading counting data from a row indicated by a row address according to an active command’, ‘refreshing, according to a refresh management command or a target refresh command, one or more rows corresponding to one of the row addresses stored in the first queue and the second queue’, and other functions. One would have been motivated to make such a combination to increase efficiency by having a comparing circuit 711 in Fig. 7 compare a count value of a row address that is to be added to a queue with a thirst threshold and a second threshold, with the second threshold being smaller than the first threshold. and when the count value of a row address falls in between the thresholds, it is added to a queue, and can enable a refresh flag 715 to mitigate a row hammer issue, as taught by Lee-2 [0065].
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Lee-2 in further view of Penney.
Regarding claim 18, Hong discloses the operating method of claim 17 as recited above. Hong in view of Lee-2, further in view of Penney teach the limitations also present in dependent claim 20 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210311463 A1 (Nalala Pochaiah et al., “SYSTEMS AND METHODS FOR OPERATION AND DESIGN OF INDUSTRIAL SYSTEM”)
US 20150149721 A1 (Kannan et al., “SELECTIVE VICTIMIZATION IN A MULTI-LEVEL CACHE HIERARCHY”)
US 20220270662 A1 (Kang et al., “MEMORY DEVICE AND OPERATING METHOD THEREOF”)
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/T.M./Examiner, Art Unit 2496
/JORGE L ORTIZ CRIADO/Supervisory Patent Examiner, Art Unit 2496