Or Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2023-0085190, filed on June 30, 2023, and parent Application No. KR10-2022-0120482, filed on September 23, 2022.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
In pages 2-9 of the remarks, Applicant states that claims 1-7, 9-13, 15-22, and 24-27 stand rejected under 35 U.S.C. § 112(b) as allegedly being indefinite for the terms “counting data” and “periodic refresh command” and “non-periodic refresh command”, particularly that the terms do not provide sufficient functional language that provide a discernable boundary on what aspect of the invention performs the functions of providing counting data, and the two different types of refresh commands. Applicant states, in pages 6-9 of the remarks, that support is provided for the amended limitations that pertain to the terms that were previously rejected under 112(b), including paragraphs [0029], [0041], [0045]-[0046] for “counting data”, and paragraphs [0040], [0043] for “periodic refresh command” and “non-periodic refresh command”.
Examiner states that regarding the support for the terms provided in the amendments, and for the term “counting data”, paragraph [0041] describes a comparison between the counting data A_CNT, which contains the value for the amount of row accesses for a row address, against a first set value MAX_CNT for a first queue, as well as a corresponding row address in the second queue Q2. The term “counting data” referring to the amount of times a row address has been accessed by a read or write command causes the variable A_CNT value to go up by a value of “+1” for each subsequent access is also described in paragraph [0046] in the Specification. Next, the terms “periodic refresh command” and “non-periodic refresh command”, which are now replaced with the terms “normal refresh command”, and “refresh management command”, as described in paragraph [0031]. The term “normal periodic refresh”, which is performed by sequentially refreshing a plurality of rows WL corresponding to the counting address when the normal refresh command “REF” in an input to the row control circuit 120, with paragraph [0123] stating that a memory controller 20 applies REF command so that all rows are sequentially refreshed within a refresh time (“tREF”). Finally, the term “refresh management command” is described in paragraph [0033] as a command provided from the memory controller when a target refresh operation (“TREF”) when a normal refresh command is provided a predetermined number of times, or when a certain condition is reached, with paragraph [0060] describing the conditions as ““YES” in S682” in Fig. 6B, showing a target refresh operation as an input corresponding to a row-hammer address RH_ADD, as well as any adjacent rows, shown in paragraph [0101] and Fig. 8B, S892. As a result of the terms being defined and pointed out in the Specification as well as how the commands achieve the invention’s purpose of automatically and providing a manual method of refreshing row addresses affected by a row-hammer attack, Examiner withdraws the rejections made under 112(b) for the claims 1-7, 9-13, 15-22, and 24-27.
In pages 10-17 of the remarks, Applicant states that claims 1-3, 5-6, 10-11, 15-16, 19, 21-22, and 25-26 stand rejected under 35 U.S.C. §102(a)(2) as allegedly being anticipated by U.S. Patent Application Publication No. 2023/0298655 to Hong ("Hong"). Applicant has amended the claims that now recite “wherein the memory cell region is divided into a normal cell region storing user data and a separate row-hammer (RH) cell region adjacent the normal cell region, the RH cell region storing counting data representing a number of accesses associated with a corresponding row in the normal cell region”, and “a counting management circuit configured to initialize the counting data in the row-hammer cells of the RH cell region and update the counting data read from the row-hammer cells by increasing a value of the counting data by "+1"”. Applicant states that Hong does not disclose these limitations, especially a memory cell region that is divided into a normal cell and RH cell region, and read counting data that represents a number of accesses associated with a corresponding row in the normal cell region. Furthermore, in page 15 of the remarks, Applicant states that when Hong teaches in [0068] that "comparator 750 may compare the count values of the counters 730_1 to 730_N with each other, and detect a row address stored in a register 720_j having a maximum count value," the comparison is not to a largest value of a largest value of the counting data stored in the RH cell region, and instead is to the maximum counting value is determined only with respect to the incoming row addresses being compared. As a result, Applicant states that independent claims 11, 19, and 22 reciting similar elements, withdrawal of the foregoing rejection of claims 1-3, 5-6, 10-11, 15-16, 19, 21-22, and 25-26 under 35 U.S.C. § 102(a)(2) as allegedly being anticipated by Hong is respectfully requested.
Examiner disagrees with the Applicant as to the statement that the amendments made to the independent claims 1, 11, 17, 19, and 22 being allowable over the prior art, with the arguments mainly focusing on the amended limitations of “a separate row-hammer (RH) cell region adjacent the normal cell region, the RH cell region storing counting data representing a number of accesses associated with a corresponding row in the normal cell region” and “a counting management circuit configured to initialize the counting data in the row-hammer cells of the RH cell region and update the counting data read from the row-hammer cells by increasing a value of the counting data by "+1"”. Hong discloses the limitation of a counting management circuit that updates counting data read from row-hammer cells in paragraph [0044] Fig. 3, counter/register control circuit 340_p increases count value of the counter 330_p without storing the row address RA again, updating the count by “+1”. Also shown in Fig. 7. This aspect of increasing a count value for every time the row address RA is accessed in the counter/register control circuit 340/740, where the counter/register control circuit corresponds to the counting management circuit. As for the other limitation involving “a separate row-hammer (RH) cell region adjacent the normal cell region”, the prior art of Hong does not disclose or suggest this limitation, as there is no other region within the memory cell array within Hong’s invention. However, the prior art of Lee et al. (US 20240028221 A1), hereinafter Lee-1 teaches the amended limitation in paragraph [0172]-[0173] Fig. 16, Redundancy cell array (“RCA”) 314 is part of memory cell array 310, with the RCA being utilized for error correction code (“ECC”), as described in paragraph [0072] or redundancy repair of the cell count, which the RCA 314 is connected to an ECC engine 350 which keeps count of the count data CNTD, which represents the amount of times a row of memory cells is accessed to read from, with count parity data (“CPRT”) that corresponds to count data (“CNTD”) that counts the amount of times a memory cell row has been accessed. The RCA is adjacent to the normal cell array (“NCA”) 310 that is shown in the memory cell array next to the RCA, and the motivation to combine the limitations together is to integrate the prior art of Lee-1 to provide data line repair and block repair to repair “failed” cells that are generated in the first memory blocks with redundancy protections to verify information for row address accesses (Lee-1 [0173]). Furthermore, the statement used in paragraph [0068] of Hong to disclose the limitation of “store the row address in the first queue according to a comparison result of the counting data and a first set value” is insufficient, and states that the comparison performed is not to a largest value of the counting data stored in the RH cell region, and is instead with respect to the incoming row addresses being compared. As a result, Examiner states that claims 1-6, 9-13, 15-16, 19, 21-22, and 24-26 are rejected under §103 (“103”) as being unpatentable over Hong in view of Lee-1.
In pages 18-20, the following rationales are described as being rejected under 35 U.S.C. §103. Page 18 of the remarks, claims 4, 9, 12-13, and 24 stand rejected under §103 as allegedly being unpatentable over Hong in view of U.S. Patent Application Publication No. 2024/0028221 to Lee et al. ("Lee-1"). Page 18 of the remarks, claims 7, 20, and 27 stand rejected under §103 as allegedly being unpatentable over Hong in view of U.S. Patent No. 11,424,005 to Penney et al. ("Penney"). Page 19 of the remarks, claim 17 stands rejected under § 103 as allegedly being unpatentable over Hong in view of U.S. Patent Application Publication No. 2023/0420027 to Lee et al. ("Lee-2"). Page 19 of the remarks, claim 18 stands rejected under §103 as allegedly being unpatentable over Hong in view of Lee-2 in further view of Penney.
Examiner states that claims being rejected are now rejected under the following rationale in response to the amendments made to the claims: claims 1-6, 9-13, 15-16, 19, 21-22, and 24-26 are rejected under §103 (“103”) as being unpatentable over Hong in view of Lee-1; claims 7, 20, and 27 are rejected under 103 over Hong in view of Lee-1, further in view of Penney; claim 17 is rejected under 103 over Hong in view of Lee-1, further in view of Lee-2; finally, claim 17 is rejected under 103 over Hong in view of Lee-1, further in view of Lee-2, and further in view of Penney. As a result of minor amendments made to the dependent claims that do not sufficiently overcome the rejections previously made, Examiner maintains the rejections made previously.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7, 9-13, 15-22, and 24-27 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, the term “+1”, such as in “update the counting data read from the row-hammer cells by increasing a value of the counting data by “+1””, which is written in quotation marks, remains unclear as to whether the term is an actual value that updates a counting value or is a reference character. The term appears in paragraph [0046] for increasing counting data for variable A_CNT by a value of 1 for keeping track of variable A_CNT, where paragraph [0029] defines the variable as “storing the number of accesses to a corresponding row”. The term “+1” is also found in paragraphs [0067], [0071], and [0094], where “+1” increases counting values for different variables, including MAX_CNT. Examiner recommends that Applicant change the term to better reflect its intended function, such as “increase/increment the counting value [A_CNT, MAX_CNT, etc.] by a value of 1”.
In claims 2-7, and 9-10, dependent claims of an independent claim inherit the deficiencies of the independent claim that are relied upon, with the independent claim being claim 1. Therefore, claims 2-7, and 9-10 are rejected for the same reasons as claim 1, as seen above.
In claim 11, the independent claim shares the same deficiencies as in claim 1 with regards to the term ‘+1’. Therefore, claim 11 is rejected for the same reasons as claim 1 above.
In claims 12-13, and 15-16, dependent claims of an independent claim inherit the deficiencies of the independent claim that are relied upon, with the independent claim being claim 11. Therefore, claims 11-13, and 15-16 are rejected for the same reasons as claim 11, as seen above.
In claim 17, the independent claim shares the same deficiencies as in claim 1 with regards to the term ‘+1’. Therefore, claim 17 is rejected for the same reasons as claim 1 above.
In claim 18, dependent claims of an independent claim inherit the deficiencies of the independent claim that are relied upon, with the independent claim being claim 17. Therefore, claim 18 is rejected for the same reasons as claim 17, as seen above.
In claim 19, the independent claim shares the same deficiencies as in claim 1 with regards to the term ‘+1’. Therefore, claim 19 is rejected for the same reasons as claim 1 above.
In claims 20-21, dependent claims of an independent claim inherit the deficiencies of the independent claim that are relied upon, with the independent claim being claim 19. Therefore, claims 20-21 are rejected for the same reasons as claim 19, as seen above.
In claim 22, the independent claim shares the same deficiencies as in claim 1 with regards to the term ‘counting data’. Therefore, claim 22 is rejected for the same reasons as claim 1 above.
In claims 24-27, dependent claims of an independent claim inherit the deficiencies of the independent claim that are relied upon, with the independent claim being claim 22. Therefore, claims 24-27 are rejected for the same reasons as claim 22, as seen above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9-13, 15-16, 19, 21-22, and 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20230298655 A1), in view of Lee et al. (US 20240028221 A1), hereinafter Lee-1.
Regarding claim 1, Hong discloses a ‘memory device comprising: a memory cell region including a plurality of rows wherein the memory cell region is divided into a normal cell region storing user data’ ([0044] Fig. 1, memory device 110 includes memory cell array 111, which includes memory cell rows, with paragraph [0025] describing a memory cell array as containing a plurality of rows. Paragraph [0048] states that even when row address A2 is stored in a register 320 of Fig. 3, is not replaced and maintained, and no intensive access has occurred, a row address adjacent to row address A2 is refreshed. [0041]-[0042] Refresh control circuit 290 (Fig. 2)/300 (Fig. 3), which can be a rowhammer refresh control circuit, contains a plurality of control/register control circuits 340, each containing a register 320 and a count 330, with each count 330 corresponding to a number of hits/accesses to its respective register 320. Each control/register control circuit 340 corresponds to a row-hammer cell storing counting data.);
‘a command decoder configured to decode an internal command from a memory controller and generate an active command, a normal refresh command that sequentially refreshes the plurality of rows, and a refresh management command issued every time a number of active commands reaches a present number;’ ([0033] Fig. 2, instruction decoder 221 generates control signal by decoding an instruction CMD received from a memory controller 120 in Fig. 1 so that a memory device may perform a refresh operation, in which a normal refresh 290 and rowhammer refresh 291 is generated, with paragraph [0040] stating that a row address VRA of a rowhammer refresh circuit 291 and a row address NRA from normal refresh circuit 292 can be outputted simultaneously. Rowhammer refresh 291 corresponds to a non-periodic refresh commends, and normal refresh 290 corresponds to a periodic refresh. The instruction CMD can include an activate instruction to switch a target row of the memory cell array 111 to an active state to read or write data from target row of memory cell array 111, thus when instruction CMD is decoded, an active command is generated as well.);
‘a target command generation circuit configured to generate a target refresh command by counting a number of inputs of the refresh management command’ ([0040] Fig. 2, normal refresh control circuit 292 calculates a row address NRA based on a normal refresh operation, and along with paragraph [0058] stating that a predetermined period is set for refresh when a predetermined condition of a maximum count value is exceeded, corresponds to a target refresh operation generated by a target command generation circuit based on a periodic refresh command.);
“a counting management circuit configured to initialize the counting data in the row-hammer cells of the RH cell region and update the counting data read from the row-hammer cells by increasing a value of the counting data by "+1"” ([0044] Fig. 3, counter/register control circuit 340_p increases count value of the counter 330_p without storing the row address RA again, updating the count by “+1”. Also shown in Fig. 7.);
‘a row-hammer control circuit including first and second queues, and configured to:’ ([0041] Fig. 7, rowhammer refresh control circuit 700, with RA storage circuit 760 corresponding to first queue, and REG/CNT control circuits 740_1 through 740_N corresponding to second queue.):
‘after the active command is generated, read the counting data from the row-hammer cells in the RH cell region adjacent the normal cell region of the memory cell region, of a row indicated by a row address, among the plurality of rows’ ([0027] Read instructions is done for reading operation of a target memory cell of a row, indicated by a row address, and a read instruction corresponds to an active command. [0062] Each of the REG/CNT control circuits 740 may store a row address and a counter, with counters 730_1 through 730_N count number of hits for an incoming row address, which is compared to "from an initial value (e.g., zero)", or a previous number stored in the CNT portion of a control circuit in Fig. 7, as stated in paragraph [0044], as Fig. 7 describes most components that are also in Fig. 3.),
‘store the row address in the first queue according to a first comparison result of the counting data and a first set value comprising a largest value of the counting data stored in the RH cell region’ ([0068] Row address storage circuit 760 stores a row address with a maximum count value determined by comparator 750, after the incoming row address RA has been put into a REG/CNT control circuit 740, wherein the maximum value is the first value. Furthermore, a replacement row address surpasses the previous maximum value by a count of 1, and in turn, remain in the RA storage circuit 760, corresponding to updating a first set value when a value of counting data is greater than the previous first set value.),
‘store the row address in the second queue according to a second comparison result of the counting data and a second set value comprising a threshold different from the first set value’ ([0044] "In some embodiments, the counter/register control circuit 340_p may store the incoming row address RA in the corresponding register 320_p again", which means that the same row address can be stored multiple times in different control circuits according to the Hong. [0062] Counters of 730 count the number of hits for incoming row addresses, and paragraph [0040] clarifies that based on a minimum count value among counters 730 for registers, a row address with the minimum value may be replaced with that of the incoming row address RA, wherein the minimum count corresponds to a second set value. Paragraph [0047] further explains that when a row stored is stored in a REG/CNT control circuit 340/740, count value is increased by one, indicating that the incoming row address has a higher count value than the previous minimum count value.),
‘and select, as a row-hammer address according to the normal refresh command or the target refresh command, one of row addresses stored in the first queue and the second queue’ ([0045] Comparator 350/750 selects a row address stored in a register of any control circuit with a maximum value, and following the scenario in which the same address can be stored multiple times in paragraph [0044], will select the one address with a maximum count value stored in any REG/CNT control circuit 740 as a row address with a maximum count value into storage circuit 760, and calculate the victim row address (VRA) utilizing an address in both a REG/CNT control circuit 340/740 and in RA storage circuit 360/760 to be calculated and refreshed, which corresponds to a target refresh command refreshing a row address in both the first and second queue.);
‘and a row control circuit configured to refresh one or more rows corresponding to the row-hammer address according to the normal command or the target refresh command’ ([0045] A refresh (REF) instruction is shown in Fig. 3 is shown in storage circuit 360, which then determines a VRA to be refreshed, corresponding to a target refresh command.).
Hong does not appear to disclose, but Lee-1 teaches the limitation of “a separate row-hammer (RH) cell region adjacent the normal cell region, the RH cell region storing counting data representing a number of accesses associated with a corresponding row in the normal cell region” ([0172]-[0173] Fig. 16, Redundancy cell array (“RCA”) 314 is part of memory cell array 310, with the RCA being utilized for error correction code (“ECC”), as described in paragraph [0072] or redundancy repair of the cell count, which the RCA 314 is connected to an ECC engine 350 which keeps count of the count data CNTD, which represents the amount of times a row of memory cells is accessed to read from, with count parity data (“CPRT”) that corresponds to count data (“CNTD”) that counts the amount of times a memory cell row has been accessed. The RCA is adjacent to the normal cell array (“NCA”) 310 that is shown in the memory cell array next to the RCA.).
Therefore, one of ordinary skill in the art would have been capable of applying this known method of "a separate row-hammer (RH) cell region adjacent the normal cell region, the RH cell region storing counting data representing a number of accesses associated with a corresponding row in the normal cell region" in a memory device comprising: a memory cell region including a plurality of rows and the results would have been predictable to one of ordinary skill in the art. The one of ordinary skill in the art would have been motivated to provide data line repair and block repair to repair “failed” cells that are generated in the first memory blocks with redundancy protections to verify information for row address accesses (Lee-1 [0173]).
Regarding claim 2, Hong in view of Lee-1 teaches the memory device of claim 1 as recited above. Hong also discloses ‘wherein the first set value is a maximum value among the counting data read from the plurality of rows’ ([0045] Fig. 7, row address storage circuit 760 stores an address with a maximum count value, wherein the maximum count value corresponds to a first set value.),
‘and wherein the first queue is configured to have a single field for storing therein the row address corresponding to the maximum value’ ([0068] Fig. 7, comparator 750 selects a row address stored in a register of any REG/CNT control circuit 740 with a maximum count value, and stores the row address with the maximum count into RA storage circuit 760.).
Regarding claim 3, Hong in view of Lee-1 teaches the memory device of claim 1 as recited above. Hong also discloses ‘wherein the second queue is configured to have a plurality of fields for respectively storing therein the row addresses indicating rows each corresponding to the counting data equal to or greater than the second set value’ ([0062] Register/counter control circuits 740 are multiple address circuits with different row addresses and counter values corresponding to hits in the row addresses, and the REG/CNT control circuits 740 are connected to a comparator 750, wherein REG/CNT control circuits corresponding to a second queue. In paragraph [0067], a minimum count value, corresponding to a second set value, amongst the registers is stated by having RA control circuit transferring a row address RA to a REG/CNT control circuit 740 with the minimum value amongst the REG/CNT control circuits 740, and replace the previous row address. Paragraph [0047] further explains that when a row stored is stored in a REG/CNT control circuit 340/740, count value is increased by one, indicating that the incoming row address has a higher count value than the previous minimum count value.).
Regarding claim 4, Hong in view of Lee-1 teaches the memory device of claim 1 as recited above. Hong does not appear to disclose, but Lee-1 teaches the limitation of ‘wherein the row-hammer control circuit is further configured to output an alert signal to an external device when the second queue is full’ ([0055] Hammer address queue stores one or more candidate addresses up to a first number, and when reached, an alert signal ALRT is provided to a memory controller 30 in response to the first number being reached, which corresponds to a second queue being full as well and outputting an alert signal.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hong and Lee-1 before them, to include Lee-1’s ‘wherein the row-hammer control circuit is further configured to output an alert signal to an external device when the second queue is full’ in Hong’s memory device performing ‘read counting data from a row indicated by a row address according to an active command’, ‘select, as a row-hammer address according to a non-periodic refresh command or a target refresh command, one of the row addresses stored in the first queue and the second queue’, and other functions. One would have been motivated to make such a combination to increase efficiency by alerting a memory controller of a memory device to prevent overflowing of a queue, and a memory controller can apply a non-periodic refresh command to a bank array to refresh rows corresponding to a row address, as taught by Lee [0169].
Regarding claim 5, Hong in view of Lee-1 teaches the memory device of claim 1 as recited above. Hong also discloses ‘wherein the row-hammer control circuit is further configured to update the counting data as the first set value when a value of the counting data is greater than the first set value’ ([0044] "In some embodiments, the counter/register control circuit 340_p may store the incoming row address RA in the corresponding register 320_p again", indicating that the same row address can be stored multiple times with the counter value for the register increasing by one each time the same address is 'replaced'. A row address already in RA storage circuit that has the maximum count amongst the registers in REG/CNT control circuits 740 can have its count increase by 1, or have a replacement row address surpass the previous maximum value by a count of 1, and in turn, remain in the RA storage circuit 760, corresponding to updating a first set value when a value of counting data is greater than first set value.),
‘wherein the row-hammer control circuit stores the row address into the first queue when the value of the counting data is greater than the first set value’ ([0044] If a row address is already at a maximum value, the row address that is replacing the previous address is required to be greater than the previous maximum value by a value of one.),
‘and wherein the row-hammer control circuit stores the row address into the second queue when the value of the counting data is greater than or equal to the second set value’ ([0067] Minimum count value amongst the registers is stated by having RA control circuit transferring a row address RA to a REG/CNT control circuit 740 with the minimum value amongst the REG/CNT control circuits 740, and replace the previous row address with an address of a higher count value than a previous minimum value, which corresponds to storing a row address into the second queue with a value greater than the previous second set value.).
Regarding claim 6, Hong in view of Lee-1 teaches the memory device of claim 1 as recited above. Hong also discloses ‘wherein the row-hammer control circuit selects: the row address stored in the second queue according to the non-periodic refresh command’ ([0057] Fig. 5, a row address stored in a register, which is also in REG/CNT control circuits 740, can be refreshed by a refresh control circuit 500, which corresponds to a non-periodic refresh command.),
‘and the row address stored in the first queue according to the target refresh command’ ([0057] Victim row address in RA storage circuit 760 in Fig. 7 may be a row address to be refreshed according to a target row address of a rowhammer refresh, corresponding to a target refresh command.).
Regarding claim 9, Hong in view of Lee-1 teaches the memory device of claim 1 as recited above. Hong also discloses the limitations of ‘a first management circuit configured to update the counting data as the first set value and store the row address into the first queue, when a value of the counting data is greater than the first set value’ ([0068] Fig. 3 or 7, RA storage circuit 360/760 stores an address that contains a maximum count value amongst the registers in REG/CNT control circuit 340/740. [0044] A row address can be stored multiple times with the counter value for the register increasing by one each time the same address is 'replaced'. A row address already in RA storage circuit that has the maximum count amongst the registers in REG/CNT control circuits 740 can have its count increase by 1, or have a replacement row address surpass the previous maximum value by a count of 1, and in turn, remain in the RA storage circuit 760, corresponding to updating a first set value when a value of counting data is greater than the previous first set value.);
‘a second management circuit configured to store the row address into the second queue when the value of the counting data is greater than or equal to the second set value’ ([0050] Fig. 5, refresh control circuit 500 may contain a plurality of registers, and has a relation to a minimum count value, which corresponds to Fig. 3 or 7 having multiple registers and count values for each. [0067] Fig. 7, minimum count value amongst the registers is stated by having RA control circuit transferring a row address RA to a REG/CNT control circuit 740 with the minimum value amongst the REG/CNT control circuits 740, and replace the previous row address, which corresponds to storing a row address into the second queue with a value greater than or equal to the second set value.);
‘and an output control circuit configured to select the row-hammer address according to the normal refresh command or the target refresh command’ ([0040] Fig. 2, refresh row address selector selects and outputs a row address to be refreshed, in which a VRA that is selected to be refreshed corresponds to a target refresh command. [0068] Fig. 7, victim RA calculator 770 can calculate a victim row address VRA and output a VRA.);
Hong does not appear to disclose, but Lee-1 teaches the limitation of ‘and configured to generate an alert signal when the second queue is full’ ([0055] Hammer address queue stores one or more candidate addresses up to a first number, and when reached, an alert signal ALRT is provided to a memory controller 30 in response to the first number being reached, which corresponds to a second queue being full as well and outputting an alert signal.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hong and Lee-1 before them, to include Lee-1’s ‘and configured to generate an alert signal when the second queue is full’ in Hong’s memory device performing ‘read counting data from a row indicated by a row address according to an active command’, ‘select, as a row-hammer address according to a non-periodic refresh command or a target refresh command, one of the row addresses stored in the first queue and the second queue’, and other functions. One would have been motivated to make such a combination to increase efficiency by alerting a memory controller of a memory device to prevent overflowing of a queue, and a memory controller can apply a non-periodic refresh command to a bank array to refresh rows corresponding to a row address, as taught by Lee-1 [0169].
Regarding claim 10, Hong in view of Lee-1 teaches the memory device of claim 1 as recited above. Hong also discloses ‘a counting management circuit configured to update the counting data according to the active command and configured to initialize the counting data after the refreshing’ ([0064] Replacement control circuit 780 receives count values from counters and determines replacement based on a minimum count value of counters 730. [0069] Memory device may initialize registers 720 and counters after refreshing a victim row.).
Regarding claim 11, Hong in view of Lee-1 teaches similar limitations also present in independent claim 1 above, and also discloses the additional limitations of ‘an operating method of a memory device having a memory cell region’ (Paragraph [0048] states that even when row address A2 is stored in a register 320 of Fig. 3, is not replaced and maintained, and no intensive access has occurred, a row address adjacent to row address A2 is refreshed. [0041]-[0042] Refresh control circuit 290 (Fig. 2)/300 (Fig. 3), which can be a rowhammer refresh control circuit, contains a plurality of control/register control circuits 340, each containing a register 320 and a count 330, with each count 330 corresponding to a number of hits/accesses to its respective register 320.);
Regarding claim 12, Hong in view of Lee-1 teaches the operating method of claim 11 as recited above. Hong does not appear to disclose, but Lee-1 teaches the limitation of ‘wherein the storing the row address into the second queue includes storing the row address into the second queue when the counting data being less than or equal to the first set value but greater than or equal to the second set value’ ([0067] Minimum count value amongst the registers is stated by having RA control circuit transferring a row address RA to a REG/CNT control circuit 740 with the minimum value amongst the REG/CNT control circuits 740, and replace the previous row address, which corresponds to storing a row address into the second queue with a value greater than the second set value. [0062] A comparator 750 requires a register to exceed the maximum value in order to be in the RA storage circuit 760, and when a register is inserted into a REG/CNT storage circuit, but does not get stored into a RA storage circuit 760, it corresponds to the register count value being less than the first set value, which is treated as a maximum value.).
Hong does not appear to disclose, but Lee-1 teaches the limitation of ‘satisfies a predetermined condition’ ([0118]-[0119] Fig. 8, comparator 520 activates a store signal STR when count data is equal to or greater than a first reference number of times NTH1, and NTH1 be include or be a default reference number of times and multiples of the default reference number of times, and a default reference number of times corresponds to a predetermined condition.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hong and Lee-1 before them, to include Lee-1’s ‘occurs a preset number of times’ in Hong’s operating method of a memory device performing ‘reading counting data from a row indicated by a row address according to an active command’, ‘refreshing, according to a non-periodic refresh command or a target refresh command, one or more rows corresponding to a selected row address of the row addresses stored in the first queue and the second queue’, and other functions. One would have been motivated to make such a combination to increase efficiency by using the default value as a base value in order to determine addresses that are at risk of a rowhammer attack when count data of how many times a row address has been accessed exceeds the first reference number of times NTH1, as taught by Lee [0120].
Regarding claim 13, Hong in view of Lee-1 teaches the operating method of claim 11 as recited above. Hong in view of Lee-1 teach the limitations also present in dependent claim 4 above.
Regarding claim 15, Hong in view of Lee-1 teaches the operating method of claim 11 as recited above. Hong also discloses ‘refreshing, according to the normal refresh command, the rows corresponding to the row address stored in the second queue’ ([0057] Fig. 5, a row address stored in a register, which is also in REG/CNT control circuits 740, can be refreshed by a refresh control circuit 500, which corresponds to a non-periodic refresh command.);
‘and refreshing, according to the target refresh command, the rows corresponding to the row address stored in the first queue’ ([0057] Victim row address in RA storage circuit 760 in Fig. 7 may be a row address to be refreshed according to a target row address of a rowhammer refresh, corresponding to a target refresh command.).
Regarding claim 16, Hong in view of Lee-1 teaches the operating method of claim 11 as recited above. Hong also discloses ‘updating the counting data and writing back the updated counting data to the row indicated by the row address, according to the active command’ ([0064] Replacement control circuit 780 receives count values from counters and determines replacement based on a minimum count value of counters 730, which occurs through row addresses being determined throughout Fig. 7 and a write command, corresponding to the active command.);
‘and initializing the counting data and writing back the initialized counting data to the row indicated by the selected row address’ ([0069] Memory device may initialize registers 720 and counters 730 after refreshing a victim row, in which a register that is indicated can be initialized.).
Regarding claim 19, Hong in view of Lee-1 teaches similar limitations also present in independent claim 1 above. Hong also discloses ‘updating the counting data as a first set value and storing the row address into a first queue, when a value of the counting data is greater than the first set value’ ([0068] Row address storage circuit 760 stores a row address with a maximum count value determined by comparator 750, after the incoming row address RA has been put into a REG/CNT control circuit 740, wherein the maximum value is the first value. [0044] "In some embodiments, the counter/register control circuit 340_p may store the incoming row address RA in the corresponding register 320_p again", indicating that the same row address can be stored multiple times with the counter value for the register increasing by one each time the same address is 'replaced'. A row address already in RA storage circuit that has the maximum count amongst the registers in REG/CNT control circuits 740 can have its count increase by 1, or have a replacement row address surpass the previous maximum value by a count of 1, and in turn, remain in the RA storage circuit 760, corresponding to updating a first set value when a value of counting data is greater than the previous first set value.);
‘storing the row address into a second queue when the value of the counting data is greater than or equal to a second set value’ ([0044] "In some embodiments, the counter/register control circuit 340_p may store the incoming row address RA in the corresponding register 320_p again", which means that the same row address can be stored multiple times in different control circuits according to the Hong. [0062] Counters of 730 count the number of hits for incoming row addresses, and paragraph [0040] clarifies that based on a minimum count value among counters 730 for registers, a row address with the minimum value may be replaced with that of the incoming row address RA, wherein the minimum count corresponds to a second set value. Paragraph [0047] further explains that when a row stored is stored in a REG/CNT control circuit 340/740, count value is increased by one, indicating that the incoming row address has a higher count value than the previous minimum count value. A comparator 750 requires a register to exceed the maximum value in order to be in the RA storage circuit 760, and when a register is inserted into a REG/CNT storage circuit, but does not get stored into a RA storage circuit 760, it corresponds to the register count value being less than the first set value, which is treated as a maximum value.);
Regarding claim 21, Hong in view of Lee-1 teaches the operating method of claim 19 as recited above. Hong also discloses the limitations present in dependent claim 15 above.
Regarding claim 22, Hong in view of Lee-1 teaches similar limitations also present in independent claim 1 above, and also discloses ‘a memory system comprising: a memory controller configured to provide an active command with a row address, or a periodic refresh command, or a non-periodic refresh command’ ([0026] Fig. 1, memory controller 120 can control a memory operation of memory device 110 in memory system 100, and the memory controller 120 can provide an instruction CMD and an address ADDR simultaneously.);
Regarding claim 24, Hong in view of Lee-1 teaches the memory system of claim 22 as recited above. Hong does not appear to disclose, but Lee-1 teaches the limitation of ‘wherein the memory device is further configured to generate an alert signal when the second queue is full’ ([0055] Hammer address queue stores one or more candidate addresses up to a first number, and when reached, an alert signal ALRT is provided to a memory controller 30 in response to the first number being reached, which corresponds to a second queue being full as well and outputting an alert signal.),
‘and wherein the memory controller provides the refresh management command every preset time, or each time the active command is provided a preset number of times, or according to the alert signal’ ([0100] Control logic circuit provides refresh control circuit 400 with non-periodic refresh signal RFMS based on a non-periodic refresh command from the memory controller 30. [0146] Fig. 12, monitor logic 650a may transition an alert signal ALRT to first logic level in response to a hammer refresh operation after a predetermined time interval elapses from a time point, corresponding to providing a non-periodic refresh command every preset time.),
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hong and Lee-1 before them, to include Lee-1’s ‘wherein the memory device is further configured to generate an alert signal when the second queue is full’ and ‘and wherein the memory controller provides the non-periodic refresh command every preset time, or each time the active command is provided a preset number of times, or according to the alert signal’ in Hong’s memory system performing ‘generate a target refresh command indicating row-hammer cells comprising one or more neighboring rows to a target row being refreshed by the normal refresh command’. One would have been motivated to make such a combination to increase efficiency by alerting a memory controller of a memory device to prevent overflowing of a queue, and a memory controller can apply a non-periodic refresh command to a bank array to refresh rows corresponding to a row address, as taught by Lee [0169], and to increase efficiency by having a time interval correspond to a precharge time tRP, a scheduler 55 applies a second command to a memory device, and when a clock signal reaches an edge, a non-periodic refresh command RFM is applied to the memory device, ensuring periodic refreshes to memory addresses, as taught by Lee [0223].
Regarding claim 25, Hong in view of Lee-1 teaches the memory system of claim 22 as recited above. Hong also discloses the limitations present in dependent claim 5 above.
Regarding claim 26, Hong in view of Lee-1 teaches the memory system of claim 22 as recited above. Hong also discloses the limitations present in dependent claim 6 above.
Claims 7, 20, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Lee-1, further in view of Penney et al. (US 11424005 B2), hereinafter Penney.
Regarding claim 7, Hong in view of Lee-1 teaches the memory device of claim 1 as recited above. Hong also discloses ‘wherein the row-hammer control circuit selects: the row address stored in the second queue according to the normal refresh command’ ([0057] Fig. 5, a row address stored in a register can be refreshed by a refresh control circuit 500, which corresponds to a non-periodic refresh command.);
‘and the row address stored in the second queue, when the second queue is not empty’ ([0057] Fig. 5, a row address stored in a register can be refreshed by a refresh control circuit 500 when there is an empty register in REG/CNT control circuit 740, which corresponds to a non-periodic refresh command.);
Hong does not appear to disclose, but Penney teaches the limitation of ‘while selecting the row address stored in the first queue, when the second queue is empty, according to the target refresh command’ ([Col. 13, lines 1-5] If Empty signal is active (where the targeted address queue 240 is empty), a current Pre_RXADD is provided for a refresh.);
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hong and Penney before them, to include Penney’s ‘and the row address stored in the first queue, when the second queue is empty, according to the target refresh command’ in Hong’s memory device performing ‘read counting data from a row indicated by a row address according to an active command’, ‘select, as a row-hammer address according to a non-periodic refresh command or a target refresh command, one of the row addresses stored in the first queue and the second queue’, and other functions. One would have been motivated to make such a combination to increase efficiency by means of having an Empty signal of a queue override a command signal RHR [row hammer refresh] to prevent suspension of automatic refresh of an auto-refresh address Pre_RXADD, ensuring that a portion of memory is always refreshed and safe from further attacks, as taught by Penney [Col. 10, line 60-Col. 11, line 14].
Regarding claim 20, Hong in view of Lee-1 teaches the operating method of claim 19 as recited above. Hong also discloses ‘wherein the refreshing includes: refreshing, according to the normal refresh command, the rows corresponding to the row address stored in the second queue’ ([0057] Fig. 5, a row address stored in a register can be refreshed by a refresh control circuit 500, which corresponds to a non-periodic refresh command in a second queue.);
‘refreshing, according to the target refresh command, the rows corresponding to the row address stored in the second queue when the second queue is not empty’ ([0057] Fig. 5, a row address stored in a register can be refreshed by a refresh control circuit 500 when there is an empty register in REG/CNT control circuit 740, which corresponds to a non-periodic refresh command.);
Hong does not appear to disclose, but Penney teaches the limitation of ‘and refreshing, according to the target refresh command, the rows corresponding to the row address stored in the first queue when the second queue is empty while refreshing’ ([Col. 13, lines 1-5] If Empty signal is active (where the targeted address queue 240 is empty), a current Pre_RXADD is provided for a refresh.);
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hong and Penney before them, to include Penney’s ‘and refreshing, according to the target refresh command, the rows corresponding to the row address stored in the first queue when the second queue is empty’ in Hong’s operating method of a memory device performing ‘reading counting data from a row indicated by a row address according to an active command’, ‘refreshing, according to a non-periodic refresh command or a target refresh command, one or more rows corresponding to one of the row addresses stored in the first queue and the second queue’, and other functions. One would have been motivated to make such a combination to increase efficiency by means of having an Empty signal of a queue override a command signal RHR [row hammer refresh] to prevent suspension of automatic refresh of an auto-refresh address Pre_RXADD, ensuring that a portion of memory is always refreshed and safe from further attacks, as taught by Penney [Col. 10, line 60-Col. 11, line 14].
Regarding claim 27, Hong in view of Lee-1 teaches the memory system of claim 22 as recited above. Hong in view of Penney teach the limitations also present in dependent claim 7 above.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Lee-1, further in view of Lee et al. (US 20230420027 A1), hereinafter Lee-2.
Regarding claim 17, Hong in view of Lee-1 teaches similar limitations also present in independent claims 1 and 11 above. Hong does not appear to disclose, but Lee-2 teaches the limitation of ‘updating the counting data as a first set value and storing the row address into a first queue, when the value of the counting data is less than the second set value but greater than the first set value’ ([0048] Fig. 3, incoming row address may be put into a queue 340 when a count value is greater than a second threshold but does not reach the first threshold, with paragraph [0042] stating that a queue 340 can store an aggressor row address ARA, that being one address, corresponding to a first queue. In Lee-2, second threshold corresponds to first set value, where a count of row address needs to exceed a second threshold, and first threshold corresponds to a second set value.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hong and Lee-2 before them, to include Lee-2’s ‘updating the counting data as a first set value and storing the row address into a first queue, when the value of the counting data is less than the second set value but greater than the first set value’ in Hong’s operating method of a memory device performing ‘reading counting data from a row indicated by a row address according to an active command’, ‘refreshing, according to a refresh management command or a target refresh command, one or more rows corresponding to one of the row addresses stored in the first queue and the second queue’, and other functions. One would have been motivated to make such a combination to increase efficiency by having a comparing circuit 711 in Fig. 7 compare a count value of a row address that is to be added to a queue with a thirst threshold and a second threshold, with the second threshold being smaller than the first threshold. and when the count value of a row address falls in between the thresholds, it is added to a queue, and can enable a refresh flag 715 to mitigate a row hammer issue, as taught by Lee-2 [0065].
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Lee-1, further in view of Lee-2 in further view of Penney.
Regarding claim 18, Hong in view of Lee-1 teaches the operating method of claim 17 as recited above. Hong in view of Lee-2, further in view of Penney teach the limitations also present in dependent claim 20 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/T.M./ Examiner, Art Unit 2496
/JORGE L ORTIZ CRIADO/ Supervisory Patent Examiner, Art Unit 2496
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