Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 12, 14, 15 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsutsui (9,647,775).
Regarding claims 1, 14, 15 and 20, Tsutsui (Fig. 3) discloses a power amplification module comprising: a logic control circuit, which is inherently seen for control switches (SW1, SW2 and SW7), a switching circuit (SW1, SW2 and SW7) and an amplifier module assembly (PA1/PA2; PA3/PA4 and PA11/PA12) that are integrated onto an integrated circuit die or chip (110C), wherein the logic control circuit is connected to the switching circuit and configured to control the switching circuit (SW1, SW2 and SW7), and the switching circuit is integrated into the amplifier module assembly and precedes one or more amplifiers of the amplifier module assembly (100C). Further noted, (PA1/PA2 is a first branch; PA3/PA4 is a second branch and PA11/PA12 is a third branch) are connected in parallel and thus read on claim 15 and 20.
Regarding claim 2, wherein the amplifier module assembly comprises an amplifier module (PA1/PA2; PA3/PA4 and PA11/PA12) corresponding to a preset frequency band (IN1/IN2; IN3/IN4 and IN7/IN8), and the switching circuit comprises a sub-switch circuit (SW1/SW2/SW7) corresponding to the preset frequency band (IN1/IN2; IN3/IN4 and IN7/IN8), wherein the sub-switch circuit for the preset frequency band is integrated into the amplifier module for the preset frequency band.
Regarding claim 3, wherein the amplifier module corresponding to the preset frequency band comprises two or more branches provided in parallel, each branch being provided with one or more amplifiers (PA1/PA2; PA3/PA4 and PA11/PA12), and the sub-switch circuit (SW1/SW2/SW7) corresponding to the preset frequency band (IN1/IN2; IN3/IN4 and IN7/IN8) comprises a switch unit (SW1/SW2/SW7) integrated in said each branch and preceding the one or more amplifiers.
Regarding claim 4, wherein the amplifier module assembly comprises a low-frequency amplification module (RFlow), a mid-frequency amplification module (RFmid) and a high-frequency amplification module (RFhigh), and the switching circuit comprises one or more sub-switch circuits (SW1/SW2/SW7) that are integrated into one or more selected from the low-frequency amplification module, the mid-frequency amplification module and the high-frequency amplification module respectively.
Regarding claim 5, wherein the low-frequency amplification module comprises a first switch unit (SW1) and a first amplifier unit (PA1), with the first switch unit preceding the first amplifier unit; the mid-frequency amplification module comprises a first-stage amplification unit (PA3), a second switch unit (SW2) and a second-stage amplification unit (PA4), with the second switch unit being provided between the first-stage amplification unit and the second-stage amplification unit; and the high-frequency amplification module comprises a second amplifier unit (PA11/PA12).
Regarding claim 6, wherein the first switch unit has a first terminal configured to receive a low-frequency band RF signal (IN1/IN2), a second terminal electrically connected to an input terminal of the first amplifier unit, and a control terminal connected to the logic control circuit. Furthermore, a standard switch configuration, such as transistor (FET) comprising three terminals, wherein gate of the transistor is called control terminal.
Regarding claim 12, wherein the second amplifier unit comprises a ninth amplifier (PA11) and a tenth amplifier (PA12), wherein the ninth amplifier has an input terminal configured to receive a high-frequency band RF signal (IN7/IN8), and an output terminal electrically connected to an input terminal of the tenth amplifier (PA12), with an output terminal of the tenth amplifier being configured to output an amplified high-frequency band RF signal (OUT10/OUT11).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsutsui.
Regarding claim 13, recited “the RF front-end chip is a CMOS integrated chip, and the RF front-end chip is packaged by a FC-LGA flip-chip process”. However, CMOS integrate chip and FC-LGP flip-chip package are well known manufacturing/fabrication process, which is considered a matter of design engineering and thus would have been obvious to a person having ordinary skills in the art.
Regarding claim 22, wherein “upstream/downstream of the RF switch” is based on utilization of the switch in the transmitter (downstream) or receiver (upstream), wherein Tsutsui’s switch(s) is used in a transmitter. However, based on specific intended use of the invention, it can be used in a receiver.
Allowable Subject Matter
Claims 7-11, 16-19, 21, and 23-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 7 and 8, prior art(s) does not disclose the first switch unit comprises a first switch and a second switch, the first amplifier unit comprises a first branched amplifier and a second branched amplifier, wherein the first switch and the second switch have respective input terminals each configured to receive a low-frequency band RF signal, with an output terminal of the first switch being electrically connected to the first branched amplifier and an output terminal of the second switch being electrically connected to the second branched amplifier.
Regarding claims 9-11, prior art(s) does not disclose the first-stage amplification unit has an input terminal configured to receive a mid-frequency band RF signal, and an output terminal electrically connected to the second-stage amplification unit via the second switch unit, with a control terminal of the second switch unit being configured to receive a second control signal.
Regarding claim 16-19, prior art(s) does not disclose the switch assembly comprises a series circuit equivalent to a first assembly comprising a series transistor, a first resistor, a second resistor and a third resistor, the series transistor having a gate configured to receive a first bias voltage input via the first resistor, and a source and a drain with the third resistor provided therebetween, wherein the drain is further connected to the amplifier.
Regarding claim 21, prior art(s) does not disclose switches of the first branch, the second branch and the third branch are respectively connected to a first field-effect tube, a second field-effect tube and a third field-effect tube, where the first field-effect tube, the second field-effect tube and the third field-effect tube have respective input terminals each connected to a signal output terminal of a fourth field-effect tube, with a signal input terminal of the fourth field-effect tube being configured to receive an input RF signal, and any one field-effect tube of the first field-effect tube, the second field-effect tube and the third field-effect tube being controlled by a signal transmitted in one of the first branch, the second branch and the third branch that corresponds to said any one field-effect tube.
Regarding claim 23, prior art(s) does not disclose each branch is configured such that the control terminal of the switching transistor receives the logic control signal input via a first resistor, a first signal terminal of the switching transistor receives the output signal input via a first capacitor, and a second signal terminal of the switching transistor transmits the received output signal via a second capacitor.
Regarding claims 24 and 25, prior art(s) does not disclose each branch further comprises a break unit that enables breaking of said each branch comprising the break unit, the break unit comprising a pull-down transistor that enables grounding or ungrounding of said each branch comprising the break unit based on a pull-down control signal as received.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional reference(s) cited in PTO-892 show further analogous prior art circuitry.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST.
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/KHANH V NGUYEN/ Primary Examiner, Art Unit 2843