DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This non-final action is responsive to the RCE filed on 07/29/2026.
Claims 1-20 are pending.
Response to Amendment
Applicant has amended independent claims 1, 11, 15 and dependent claims 2, 6, 12, 16-17 to include new/old limitations in a form not previously presented necessitating new search and considerations.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112 (b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or joint inventor regards as the invention.
The following claim language is not clearly understood:
Claim 1 recites “a first tag from the second processor” and “a tag comprised in the first information stored in the memory”. It is unclear what constitutes these tags and if they contain same /different information, and what do the information within these tag indicate.
Claims 11 and 15 recite elements of claim 1 and have similar deficiency as claim 1. Therefore, they are rejected for the same rationales. Remaining dependent claims 2-10, 12-14 and 16-20 are also rejected due to similar deficiency inherited from the rejected independent claims.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more or integrating into practical application.
Claims 1-20 are determined to be directed to an abstract idea. Examples of abstract ideas include at least Mathematical concepts, Mental process and Certain Methods of organizing human activity. Independent claim 1 is directed to “matching tags in the received information and tags acquired by the second processor; transmitting the data to the processor in case of tags being matched” at a high level of generality.
Step 1
As described in MPEP § 2106, subsection III, Step 1 of the eligibility analysis asks: Is the claim to a process, machine, manufacture or composition of matter?
Claim 1 recites a network adapter comprising a processor and claim 11 recites computing device comprising processor, which falls within the “machine / manufacture” category of 35 U.S.C. § 101. Claim 15 recites a method, which falls within the “process” category of 35 U.S.C. § 101. Thus, the analysis determines whether the claims recite a judicial exception and fail to integrate the exception into practical application.
Step 2A Prong One
As described in MPEP § 2106, subsection III, Step 2A of the Office’s eligibility analysis is the first part of the Alice/Mayo test, i.e., the Supreme Court’s "framework for distinguishing patents that claim laws of nature, natural phenomena, and abstract ideas from those that claim patent-eligible applications of those concepts." Alice Corp. Pty. Ltd. v. CLS Bank Int'l, 573 U.S. 208, 217-18, 110 USPQ2d 1976, 1981 (2014) (citing Mayo, 566 U.S. at 77-78, 101 USPQ2d at 1967-68).
Step 2A is a two-prong inquiry, in which examiners determine in Prong One whether a claim recites a judicial exception, and if so, then determine in Prong Two if the recited judicial exception is integrated into a practical application of that exception.
claim elements
i
1. A network adapter, wherein a receiving node comprises the network adapter and a second processor, and the network adapter comprises: a first processor; and a memory, wherein the memory stores a computer-readable program and first information; and
generic computing components
ii
the first processor is configured to execute the computer-readable program in the memory, to enable the network adapter to perform operations comprising:
generic computing components
iii.
receiving a first send message sent by a sending node to the receiving node
information gathering / data collection
iv.
wherein the first send message comprises first data or information about the first data;
information about data
v.
receiving a first tag from second processor; and
information gathering
vi.
sending the first data to the second processor,
information transmission
vii.
based on the first tag received from the second processor matching a tag comprised in the first information stored in the memory.
mental process abstract idea
The process described by steps [vii] describes “concepts performed in the human mind” or “observation, evaluation, judgement, opinion.” Step [vii] recites “based on the first tag received from the second processor matching a tag comprised in the first information stored in the memory,”, which is a combination of observation, evaluation, judgement and opinion, and can be performed by human mind alone or with the aid of pen and paper. The courts consider a mental process (thinking) that "can be performed in the human mind, or by a human using a pen and paper" to be an abstract idea. CyberSource Corp. v. Retail Decisions, Inc., 654 F.3d 1366, 1372, 99 USPQ2d 1690, 1695 (Fed. Cir. 2011).
Thus, claim 1 recites a judicial exception. For these same reasons, claims 11 and 15 also recites judicial exception.
Step 2A, Prong Two
As described in MPEP § 2106, subsection III, Step 2A of the Office’s eligibility analysis is the first part of the Alice/Mayo test, i.e., the Supreme Court’s "framework for distinguishing patents that claim laws of nature, natural phenomena, and abstract ideas from those that claim patent-eligible applications of those concepts." Alice Corp. Pty. Ltd. v. CLS Bank Int'l, 573 U.S. 208, 217-18, 110 USPQ2d 1976, 1981 (2014) (citing Mayo, 566 U.S. at 77-78, 101 USPQ2d at 1967-68).
Step 2A is a two-prong inquiry, in which examiners determine in Prong One whether a claim recites a judicial exception, and if so, then determine in Prong Two if the recited judicial exception is integrated into a practical application of that exception.
Because claims 1, 11 and 15 recite a judicial exception, Analysis determines if the claims recites additional elements that integrate the judicial exception into practical application.
In addition to the limitations of claim 1 discussed above that recite the abstract concepts, claim 1 also recites additional steps [i]-[vi]. Claim 1 in steps [i] and [ii] recites conventional and generic computing components e.g. network adapter, processor, memory, program performing convention and generic computing method and therefore are neither inventive nor provide improvement to the technology and/or technical field. Therefore, these elements don’t integrate the abstract idea into practical application.
Claim 1 steps [iii] and [v] are directed to either information gathering/collection. Information gathering is considered insignificant extra solution activity and therefore do not integrate into practical application. Similarly, information transmission is commonly performed in the field of computing and therefore is neither inventive nor provide improvement to the technical or technological field. Claim 1 in steps [iv] recites “the first send message comprises first data or information about the first data”, which is directed to further describing the message, without further imposing meaningful limitations in such as a manner to integrate the abstract idea into practical application i.e. these are also neither inventive nor provide improvement to the technology or technical field. Claim 1 in step [vi] recites “sending the first data to the second processor”, which is directed to transmission of data. Transmitting data is common computing activity and is well-understood, routine and conventional, as recognized by one of ordinary skills in the art. The Specification doesn’t provide additional details that would distinguish the additional limitations recited in claim 1 from a generic implementation of the abstract idea. Thus, the additional claim elements recited in steps [i]-[vi] either alone or in combination, under broadest reasonable interpretation, do not integrate the judicial exception into a practical application.
Thus, claim 1 recites a judicial exception without integrating into practical application. For these same reasons and based on similar analysis as above, claims 11 and 15 also recites judicial exception without integrating into practical application.
Step 2B
As described in MPEP § 2106, subsection III, Step 2B of the Office’s eligibility analysis is the second part of the Alice/Mayo test, i.e., the Supreme Court’s "framework for distinguishing patents that claim laws of nature, natural phenomena, and abstract ideas from those that claim patent-eligible applications of those concepts." Alice Corp. Pty. Ltd. v. CLS Bank Int'l, 573 U.S. 208, 217, 110 USPQ2d 1976, 1981 (2014) (citing Mayo, 566 U.S. 66, 101 USPQ2d 1961 (2012)).
Step 2B asks: Does the claim recite additional elements that amount to significantly more than the judicial exception.
Because claims 1, 11 and 17 are directed to judicial exception, analysis must determine, according to Alice, whether these claims recite an element, or combination of elements that is enough to ensure that the claim is directed to significantly more than a judicial exception.
The Memorandum, Section III (B) (footnote 36) states:
In accordance with existing guidance, an Examiner’s conclusion that an additional element (or combination of elements) is well understood, routine, conventional activity must be supported with a factual determination. For more information concerning evaluation of well-understood, routine, convention activity, see MPEP 2106.05(d), as modified by the USPTO Berkheimer Memorandum.
The Berkheimer Memorandum, Section III(A)(1) states:
A Specification demonstrates the well-understood, routine, conventional nature of additional elements when it describes the additional elements as well-understood or routine or conventional (or an equivalent term), as a commercially available product, on in a manner that indicates that the additional elements are sufficiently well-known that the specification does not need to describe the particulars of such additional elements to satisfy 35 §U.S.C. 112(a). A finding that an element is well-understood, routine, or conventional cannot be based only on the fact that the specification is silent with respect to describing such element.
Regarding the network adaptor, processors, memories, program, receiving node as recited in claim 1 steps [i]-[ii], the conventional or generalized function terms by which the computer components are described reasonably indicate that Specification discloses conventional component, and describes the component in a manner that indicates that these elements are sufficient well-known that the Specification does not need to describe the particulars of such additional elements to satisfy 35 U.S.C. §112(a). Further, the Specification does not provide additional details that would distinguish the recited components from generic implementation in the combination. Claim 1 steps [iii], [v] and [vi] are directed to either information gathering/collection and/or information transmitting. Information gathering is considered insignificant extra solution activity. See Elec. Power, 830 F.3d at 1350. Similarly, information transmission is commonly performed in the field of computing and therefore is well-understood, routine and conventional as recognized by one of ordinary skills in the art. Claim 1 in step [iv] recites “the first send message comprises first data or information about the first data”, which is only informative and do not impose further limitations on the abstract idea in such a manner to make the abstract idea patent eligible and do not amount to significantly more. These limitations either alone or in combination simply append well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception. Further, the Specification doesn’t provide additional details that would distinguish the additional limitations as recited in the claim from a generic implementation of the abstract idea.
Thus, Claims 1 is directed to mental process abstract idea without integrating into practical application and also do not amount to significantly more than a patent ineligible concept. Based on similar rationale and analysis as above, claims 11 and 15 are directed to mental process abstract idea without integrating into practical application and also do not amount to significantly more.
Claim 2 recites “second information, the second information comprises a tag that is acquired from the second processor and that fails in tag matching performed by the network adapter, and the operations further comprising: in response to the first tag failing to match, storing the first tag in a storage space for storing the second information in the memory” which is directed to failed tag matching and further storing the first tag in memory. Failing tag matching is directed to mental process abstract idea. Storing information is basic computing activity.
Claim 3 recites wherein the second processor is connected to the network adapter through a bus, the network adapter is operable to receive, through the bus, the first tag sent by the second processor, and the network adapter is operable to send the first data to the second processor through the bus, which is directed to information gathering/ distribution using generic computing component. Information gathering / transmission is considered insignificant extra solution activity.
Claim 4 recites the first send message is transmitted, through a network, by a source process executed by the sending node to a destination process executed by the receiving node, which is directed to information transmission between nodes. Transmission of information is neither inventive nor amount to significantly more.
Claim 5 recites wherein the receiving node and the sending node are operable to communicate with each other through a message passing interface (MPI), which is directed to MPI communication is well-known in the art (See Background [0003]).
Claim 6 recites the operations further comprise: acquiring the first data from the first information based on the first tag, wherein the first information comprises the first data; or acquiring the first data based on the information about the first data associated with the first tag, wherein the information about the first data indicates information about an address at which the first data is stored, which is directed to successful tag matching and acquiring data. As explained above, tag matching is considered a mental process abstract idea. Acquiring information is considered insignificant extra solution activity.
Claim 7 recites wherein acquiring the first data based on the address associated with the first tag comprises: acquiring the first data from a storage space that is in the memory and that is indicated by the address associated with the first tag, which is associated with acquiring data associated with the first tag and is no more than insignificant information gathering activity. Tag matching is mental process abstract idea.
Claim 8 recites wherein acquiring the first data based on the address associated with the first tag comprises: acquiring the first data from a storage space that is in the sending node and that is indicated by the address associated with the first tag, which is also directed to gather information based on certain condition and is directed to mental process abstract idea and additional elements are directed to insignificant extra solution activity of information gathering.
Claim 9 recites wherein the first processor is configured to execute the computer-readable program in the memory to enable the network adapter to perform operations further comprising: deleting the first tag in the first information, which is directed to basic computing activity of deleting data, and therefore is neither inventive nor amount to significantly more.
Claim 10 recites elements similar to claim 1 but with second information, second tag and storing tag in response to the failed matching. Therefore, based on similar analysis / rationales, claim 10 also recites abstract idea and neither integrate into practical application nor amount to significantly more.
Based on similar analysis / rationales as above, dependent claims 12-14 and 16-20 recite claim elements that are either abstract idea or additional claim elements, that individually or in combination, are either generic computing methods/components or insignificant pre-post solution activity and neither integrate into practical application nor amount to significantly more.
Therefore, the claim(s) 1-20 are rejected under 35 U.S.C. 101 as being directed to judicial exception without integrating into practical application or significantly more.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rimmer et al. (US2020/0358721, hereafter Rimmer) in view of Shuler et al. (US 2016/0072906 A1, hereafter Shuler), and further in view of Raindel et al. (US 2016/0330301 A1, hereafter Raindel).
Rimmer was cited in the last office action.
As per claim 1, Rimmer teaches the invention substantially as claimed including a network adapter ([0100] fig. 14 network interface 1400), wherein a receiving node comprises the network adapter and a second processor ([0077] fig. 11 receiver node 1110 [0100] network interface 1400 may be embedded as part of system-on-a-chip that includes one or more processors [0031] receiver network interface [0033] node, host system computing platform 602, NIC 650, transmit and receive packets), and the network adapter comprises ([0100] fig. 14 network interface 1400):
a first processor (fig. 14 1404); and
a memory (fig. 14 1410), wherein the memory stores a computer-readable program and first information ([0105] memory 1410, store any instructions, data, packets); and
the first processor is configured to execute the computer-readable program in the memory ([0101] fig. 14 network interface 1400, processors 1404 memory 1410; processors 1404 can perform determination, packet processing capability), to enable the network adapter to perform operations comprising ([0101] processors 1404 can perform a determination of whether a received packet can be stored in a buffer selected by NIC 1400, packet processing capability):
receiving a first send message sent by a sending node to the receiving node ([0024] fig. 2 sender, message, sent, network, receiver, store data received from a sender to receiver [0036] receive operations of NIC 650), wherein the first send message comprises first data or information about the first data ([0024] sender, MPI_send, integer referred to as tag, source identifier, destination identifier, data in a message sent on the network to receiver);
receiving a first tag from the second processor; and
sending the first data to the second processor based on the first tag received from the second processor matching a tag comprised in the first information stored in the memory ([0024] tag matching, tag, network message, buffer on the receiver [0024] MPI_send, integer referred to as tag, receiver, data arriver from network, receiver stores data, receiver buffer, tag matching, use source and tag in the network message, associate with a buffer on the receiver i.e. tag in the message received and tag associated with the buffer is matched [0025] tag matching, offloaded, NIC [0027] NIC performs tag matching).
Rimmer doesn’t specifically teach receiving a first tag from the second processor; and sending the first data to the second processor based on the first tag received from the second processor matching a tag comprised in the first information stored in the memory.
Shuler, however, teaches receiving a first tag from the second processor ([0032] processes 34 pushes a part of their lists of tags 38 to tag matching logic 50 [0028] processes 34 run on CPU 26 i.e. tags are received from the processor [0032] NIC 30 tag matchings logic 50); and
sending the first data to the second processor ([0038] target NIC 64 writes the data from packets 76 to a buffer 40 in memory 28 [0032] rendezvous messages, tag matching logic 50 invokes RDMA engine 52 in NIC 30 to retrieve data send by peer processes running on host computer 22 to processes 34 [0028] processes 34 run on CPU 26 i.e. message are sent to the processor) based on the first tag received from the second processor matching a tag comprised in the first information stored in the memory ([0032] NIC 30 tag matching logic 50, tag matching operations [0037] RTS packet 70 tag parameter, tag matching logic 50 target NIC matches the tag in RTS packet against tags in head 56 of the list posted by target process 66, logic 50 finds a match [0032] processes 34 pushes a part of their lists of tags 38 to tag matching logic 50 [0028] processes 34 run on CPU 26 i.e. tags are received from the processor [0032] NIC 30 tag matchings logic 50 ).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Rimmer with the teachings by Shuler of processes running on the processor pushing the tags to the matching logic of the NIC, NIC writing the message to the buffer in the memory upon successful matching of the tags to improve efficiency and allow receiving a first tag from the second processor; and sending the first data to the memory accessible to the second processor based on the first tag received from the second processor matching a tag comprised in the first information stored in the memory to the method of Rimmer as in the instant invention.
The combination of analogous cited prior art would have been obvious because using the known method of matching the tag received from the sending node and tags received by the process of the local processor as taught by Shuler to the method of Rimmer to yield expected result and improved efficiency.
Rimmer and Shuler, in combination, do not specifically teach sending the first data to the second processor.
Raindel, however, teaches receiving a first tag from the second processor ([0055] tagging packets by NIC, tagging generated by software running on CPU 28 fig. 4 NIC 32 -CPU 28 -CPU memory 30);
sending the first data to the second processor (clam 8: host processor is coupled to the transmit and receive the data packets via network interface controller [0036] flow is transmitted to the host processor along with the received packet fig. 4 NIC 32 -CPU 28 -CPU memory 30).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Rimmer and Shuler with the teachings by Raindel of tagging generated by software running on CPU, and host processor coupled to NIC to receive the data packets to improve efficiency and allow sending the first data to the second processor instead of memory to the method of Rimmer and Shuler as in the instant invention.
The combination of analogous cited prior art would have been obvious because using the known method of host processor receiving the data from the NIC and tagging generated by the software running on the CPU taught by Raindel as taught by Shuler to the method of Rimmer and Shuler to yield expected result and improved efficiency.
As per claim 2, Rimmer teaches wherein the memory further stores second information in a storage space of the memory ([0105] fig. 14 memory 1410, store, any instructions), the second information fails in tag matching performed by the network adapter ([0025] tag matching, offloaded, NIC [0027] NIC performs tag matching - would succeed or fail), and the operations further comprise:
in response to the first tag failing to match any tag comprised in the first information (fig. 2 MPI_recev (tag, source, buffer) [0024] tag matching, tag in network message, bugger1, tag1 value, buffer2 , store, data, tag2 values, buffer associated with the sender [0025] perform tag matching i.e. both match and mismatch can be judged tag1 buffer1, tag2 buffer2), storing the first tag in the storage space of the memory ([0024] tag matching makes use of tag in then message to store in the desired buffer [0025] perform tag matching e.g. using software to identify the right buffer; fig. 2 tag2 buffer2).
Shuler remaining claim elements of a tag that is acquired from the second processor ([0032] processes 34 pushes a part of their lists of tags 38 to tag matching logic 50 [0028] processes 34 run on CPU 26 i.e. tags are received from the processor [0032] NIC 30 tag matchings logic 50).
As per claim 3, Rimmer teaches wherein the second processor is connected to the network adapter through a bus (fig. 11 receiver 1110 fig. 13 network interface 1350 processors 1310 fig. 14 processors 1404 [0092] one or more buses), the network adapter is operable to receive, through the bus, the first tag sent by the second processor ([0077] fig. 11 receiver node 1110 [0100] network interface 1400 may be embedded as part of system-on-a-chip that includes one or more processors [0031] receiver network interface [0033] node, host system computing platform 602, NIC 650, transmit and receive packets).
Shuler remaining claim elements of receive fist tag from the second processor ([0032] processes 34 pushes a part of their lists of tags 38 to tag matching logic 50 [0028] processes 34 run on CPU 26 i.e. tags are received from the processor [0032] NIC 30 tag matchings logic 50); and
As per claim 4, Rimmer teaches wherein the first send message is transmitted, through a network, by a source process executed by the sending node to a destination process executed by the receiving node (fig. 4A sender, MPI_send, receiver, MPI_recv ).
As per claim 5, Rimmer teaches wherein the receiving node and the sending node are operable to communicate with each other through a message passing interface (MPI) (fig. 4B sender-receiver [0027] MPI_Send, MPI_Recv).
As per claim 6, Rimmer teaches the wherein the operations further comprise ( fig. 14 network interface 1400 processor 1404 memory 1410 [0101] packet processing capabilities in the network interface using processors 1404 [0024] tag matching, use, tag, associate message with buffer on the receiver [0025] tag matching i.e. only possible outcome is success/fail):
acquiring the first data from the first information stored in the memory based on the first tag, wherein the first information stored in the memory comprises the first data ([0024] fig. 2 sender, message, sent, network, integer referred to as tag, source identifier, destination identifier, data in a message sent on the network to receiver, receiver, store data received from a sender to receiver [0036] receive operations of NIC 650 [0025] place data into bounce buffer, perform tag matching, copy data from the bounce buffer into the application requested buffer); or
acquiring the first data based on the information about the first data associated with the first tag ([0024] fig. 2 sender, message, sent, network, integer referred to as tag, source identifier, destination identifier, data in a message sent on the network to receiver, receiver, store data received from a sender to receiver [0036] receive operations of NIC 650 [0025] copy data from the bounce buffer into application requested buffer), wherein the information about the first data indicates information about an address at which the first data is stored ([0037] field data can indicate a memory address in which data to be transmitted is stored [0038]).
As per claim 7, Rimmer teaches wherein acquiring the first data based on the address associated with the first tag comprises:
acquiring the first data from a storage space that is in the memory and that is indicated by the address associated with the first tag ([0037] field data can indicate a memory address in which data to be transmitted is stored fig. 4B MPI_Send, additional transfers).
As per claim 8, Rimmer teaches wherein acquiring the first data based on the address associated with the first tag comprises:
acquiring the first data from a storage space that is in the sending node and that is indicated by the address associated with the first tag ([0037] field data can indicate a memory address in which data to be transmitted is stored fig. 4B MPI_Send, additional transfers).
As per claim 9, Rimmer teaches the first processor is configured to execute the computer-readable program in the memory to enable the network adapter to perform operations further comprising: deleting the first tag in the first information (fig. 14 network adapter 1400 processors 1404).
Raindel teaches remaining claim elements of deleting the first tag in the first information ([0056] strip the tag from the packet).
Claim 10 recites elements similar to claim 1 and 2 applied to a second tag and a second tag comprised in the second information. Therefore, it is rejected for the same rationale.
Claim 11 recites a computing device for elements similar to claim 1. Therefore, it is rejected for the same rationale.
Claim 12 recites a computing device for elements similar to claim 2. Therefore, it is rejected for the same rationale.
Claim 13 recites a computing device for elements similar to claim 3. Therefore, it is rejected for the same rationale.
Claim 14 recites a computing device for elements similar to claim 4. Therefore, it is rejected for the same rationale.
Claim 15 recites data acquisition method for elements similar to a combination of claim 1 and 5. Therefore, it is rejected for the same rationale.
Claim 16 recites data acquisition method for elements similar to a combination of claim 2. Therefore, it is rejected for the same rationale.
Claim 17 recites data acquisition method for elements similar to a combination of claim 10. Therefore, it is rejected for the same rationale.
Claim 18 recites elements similar to part of claim 6. Therefore, it is rejected for the same rationale.
Claim 19 recites elements similar to part of claim 6. Therefore, it is rejected for the same rationale.
Claim 20 recites elements similar to elements of claim 9. Therefore, it is rejected for the same rationale.
Examiners Note
Applicant is further reminded of that the cited paragraphs and in the references as applied to the claims above for the convenience of the applicant(s) and although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider all of the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Response to Arguments
The previous objections to the specification have been withdrawn.
The previous objections under 35 USC 112 (b) have been withdrawn. However, some new 112(b) objections have been made.
Applicant's arguments to overcome 35 USC 103 rejections filed on 07/20/2026 have been fully considered but they are moot in view of new grounds of rejections.
Applicant's arguments to overcome 35 USC 101 rejections filed on 07/20/2026 have been fully considered but they are not persuasive. In Applicant’s response filed on 07/20/2026, Applicant argues the following:
Claims do not recite the mental process.
Claim 1 recite (1) receive a first send message … (2) receive a first tag from a second processor, and (3) send the first data to the second processor … , and these operation require specific hardware, and can’t be practically performed by the human mind.
Claims are directed to an improvement in the high performance computing. uploading the tag matching operation to a network adapter result in improved utilization.
Additional claim elements here - the network communication system comprising a sending node and the receiving node;….; and the network adapter sending the first data to the second processor - are not individually well-understood, routine, or conventional, and their ordered combination is further removed from any alleged abstract idea. The specification describes this combination as a specific technical architecture that departs from the conventional tag matchings operations.
Examiner has thoroughly considered Applicant’s arguments, but respectfully, find them unpersuasive for at least the following reasons:
With respect to point a:) Examiner respectfully disagree. Claim 1 in step [vii] recites “based on the first tag received from the second processor matching a tag comprised in the first information stored in the memory”, which is directed to comparing two tags and is a combination of observation, evaluation, judgement and opinion, and can be performed by human mind alone or with the help of pen and paper. Therefore, at least limitation recited in step [vii] of claim 1 is directed to mental process abstract idea.
With respect to point b:) Applicant argues that limitations recited in claim 1 require specific hardware such as processors, and network adapters and memory and therefore, they can’t be performed in human mind. Examiner respectfully indicate that these hardware e.g. processor, network adapters and memory are common computing component and these are also coupled to each other in a way similar to a common computing system. Implementing an abstract idea using a generic/common computing system doesn’t make the claim patent eligible.
With respect to point c:) Applicant argues that Claims are directed to an improvement in the high performance computing. Uploading the tag matching operation to a network adapter result in improved utilization. Examiner respectfully indicate that the advantage sought by the Applicant’s invention has not been realized by the claim i.e. claim doesn’t tie the improvement as argued with the limitations recited in the claim, and current independent claims are directed to filter message based on matching the tags, which is abstract idea.
With respect to point d:) Examiner respectfully disagree because the claimed elements are very well-understood, routine and conventional and nature as illustrated by the cited applied / relevant prior arts ([See Shuler, Rimmer, Cherian, Graham]), and therefore don’t amount to significantly more.
Conclusion
Authorization for Internet Communication
Applicant is encouraged to submit an authorization to communicate with the Examiner via the internet by making the following statement (MPEP 502.03)
“Recognizing that internet communications are not secure, I hereby authorize the USPTO to communicate with the undersigned and practitioners in accordance with 37 CFR 1.33 and 37 CFR 1.34 concerning any subject matter of this application by video conferencing, instant messaging, or electronic mail. I understand that a copy of these communications will be made of record in the application file.”
Please note that the above statement can only by submitted via Central Fax (not Examiner’s Fax), Regular postal mail, or EFS Web using PTO/SB/439.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cherian et al. (US 2015/0381494 A1) teaches method to offload overlay network packet encapsulation to hardware including tagging by physical NIC
Graham et al. (US 2018/0219804 A1) teaches mechanism for distributing MPI tag matchings
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ABU ZAR GHAFFARI
Primary Examiner
Art Unit 2195
/ABU ZAR GHAFFARI/Primary Examiner, Art Unit 2195
