DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/24/2025 has been entered.
Response to Amendment
The Applicant’s Amendment, filed 10/24/2025 has been entered. Claims 1-20 are pending in the Application.
Response to Arguments
Applicant's arguments filed 10/24/2025 with respect to the prior art rejections have been fully considered but they are not persuasive.
Regarding claims 1, 12 and 16, the Applicant argues that the cited art Sinclair fails to teach the newly amended limitation “wherein the at least one functional component is coupled only to the one of the first lateral circular data path and the first longitudinal circular data path”. The Examiner respectfully disagrees. Contrary to the Applicant’s submission, Sinclair’s figure 12 shows functional components such as DRAM controller and/or encryption engine are located at a non-intersection and thus are only coupled to one data path. Therefore, the prior art discloses the argued limitation as recited in the claims.
Based on the reasoning above, the rejections have been modified to address the newly amended limitation. Please see below for the detailed rejections.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 7-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sinclair US 20160188502.
Regarding claim 1, Sinclair teaches a system (see figure 12), wherein the system comprises:
a plurality of circular data paths comprising a first lateral circular data path second lateral circular data path (ring buses 1204 and 1206), a first longitudinal circular data path, and a second longitudinal circular data path (ring bus 1202 and 1210);
a plurality of data routing components coupled to the plurality of circular data paths, wherein the plurality of data routing components comprise a first data routing component and a second data routing component the first data routing component is disposed at a first intersection of and is coupled to the first lateral circular data path and the first longitudinal circular data path (bus bridge 1212 at the intersection of 1204 and 1202), and the second data routing component is disposed at a second intersection of and is coupled to the second lateral circular data path and the second longitudinal circular data path (bus bridge 1218 at the intersection of 1206 and 1210); and
at least one functional component disposed at a non-intersection corresponding to one of the first lateral circular data path and the first longitudinal circular data path (functional component such as controller 1220 and/or NAND die 914), wherein the at least one functional component is configured to transmit data to a destination component on another one of the first lateral circular data path and the first longitudinal circular data path through the first data routing component (see para 0066, memory modules may perform concurrent data transfers between multiple source and destination nodes along the primary ring bus 702 and secondary ring busses 704), wherein the at least one functional component is coupled only to the one of the first lateral circular data path and the first longitudinal circular data path (see figure 2, functional components such as DRAM controller and/or encryption engine are coupled only to one of the data path).
Regarding claim 2, Sinclair further teaches the plurality of circular data paths are arranged in a mesh (see figure 12 shows that the ring buses are in a mesh).
Regarding claim 3, Sinclair further teaches the at least one functional component comprises a plurality of functional components disposed at a plurality of non-intersections on one of the plurality of circular data paths, and the plurality of functional components are arranged on a same side of the one of the plurality of circular data paths (see figure 12 shows multiple NAND dies on the same side of ring bus 1204).
Regarding claim 4, Sinclair further teaches the at least one functional component comprises at least one of a computing component (controller 708 in figure 7) and a storage component (NAND die in figure 7); and
the computing component is configured to process a computing task (see para 0094, Examples of concurrent operations that the bus controller may perform include… processing data with components on a primary or secondary ring bus), and the storage component is configured to process a storage task (see para 0087, store data at a non-volatile memory unit, such as a NAND memory die).
Regarding claim 5, Sinclair further teaches the at least one functional component comprises at least one computing component (controller 708 in figure 7) and at least one storage component (NAND die in figure 7);
each of the at least one computing component is coupled to a corresponding longitudinal circular data path (see figure 7 shows that controller 708 is coupled to ring bus 702); and
each of the at least one storage component is coupled to a corresponding lateral circular data path (see figure 7 shows that NAND die is coupled to ring bus 704).
Regarding claim 7, Sinclair further teaches each of the plurality of data routing component is one of a central processing unit (CPU), a network interface controller (NIC), a peripheral component interconnect express (PCIE), or a ring bridge (see para 0062, bus bridge 706).
Regarding claim 8, Sinclair further teaches the data carries a destination address, and the destination component receives the data in response to determining that the destination address carried in the data is consistent with an address of the destination component (see para 0050, the identification number is used during operation as an address for commands from the controller that are intended for the node… only the node or nodes addressed with their identification number will therefore respond to store and then execute the command).
Regarding claim 9, Sinclair further teaches the first data routing component is further configured to: store a first address set, wherein the first address set comprises an address of another component coupled to the first lateral circular data path and an address of another component coupled to the first longitudinal circular data path (see figure 10, operation for command from ring bus controller to NAND A1, the bus bridge A store an address set comprises a source address of primary ring bus (bus 702) and a destination address of secondary ring bus A (bus 704)).
Regarding claim 10, Sinclair further teaches the first data routing component is configured to: determine that the destination address carried in the data is consistent with an address in the first address set, receive the data, and forward the data to one of the plurality of circular data paths to which a component corresponding to the address in the first address set is coupled (see para 0079, for example, referring to example operation 3, a command needs to be sent from the ring bus controller 908 to NAND die A1 912 on secondary ring bus A 904. To conduct this operation, the ring bus controller 908 sends configuration commands to set bus bridge B 916 to bypass secondary ring bus B 906; to set bus bridge A 910 to route data and commands from the primary ring bus 902 to secondary ring bus A 904; and to route data from bus bridge A 910 to NAND die A1 912).
Regarding claim 11, Sinclair further teaches the data further carries one or more forwarding addresses of at least one forwarding component corresponding to the destination component, and the one or more forwarding addresses comprise an address of the first data routing component; and the first data routing component is further configured to: determine that one of the one or more forwarding addresses carried in the data is consistent with the address of the first data routing component, receive the data, and forward the data to another circular data path of the plurality of circular data paths to which the first data routing component is coupled (see para 0080, In another example, referring to example operation 10, a copy of data from NAND die Al 912 is sent to NAND die B1 918. Therefore, data must be sent from secondary ring bus A 940 to secondary ring bus B 906. To conduct this operation, the ring bus controller 908 sends configuration commands to set secondary ring bus A 904 to route data and commands from NAND die A1 912 to bus bridge A 910; to set bus bridge A 910 to route data and commands from secondary ring bus A 904 to the primary ring bus 902; to set bus bridge B 916 to route data and commands from the primary bus bridge 902 to secondary ring bus B 906; and to set secondary ring bus B 906 to route data and commands from bus bridge 916 to NAND die B1 918).
Regarding claim 12, Sinclair teaches a method for transmitting data in an interconnection system (see figure 12), wherein the interconnection system comprises:
a plurality of circular data paths comprising a first lateral circular data path, a second lateral circular data path (ring buses 1204 and 1206), a first longitudinal circular data path, and a second longitudinal circular data path (ring bus 1202 and 1210);
a plurality of data routing components coupled to the plurality of circular data paths, wherein the plurality of data routing components comprise a first data routing component and a second data routing component, the first data routing component is disposed at a first intersection of and is coupled to the first lateral circular data path and the first longitudinal circular data path (bus bridge 1212 at the intersection of 1204 and 1202), and the second data routing component is disposed at a second intersection of and is coupled to the second lateral circular data path and the second longitudinal circular data path (bus bridge 1218 at the intersection of 1206 and 1210); and
at least one functional component disposed at a non-intersection corresponding to one of the first lateral circular data path and the first longitudinal circular data path (functional component such as controller 1220 and/or NAND die 914), and wherein the method comprises:
transmitting, by the at least one functional component, data to another one of the first lateral circular data path and the first longitudinal circular data path; receiving the data by the first data routing component; and forwarding, by the first data routing component, the received data to a destination component on the other one of the first lateral circular data path and the first longitudinal circular data path (see para 0066, memory modules may perform concurrent data transfers between multiple source and destination nodes along the primary ring bus 702 and secondary ring busses 704, also see para 0079-0080), wherein the at least one functional component is coupled only to the one of the first lateral circular data path and the first longitudinal circular data path (see figure 2, functional components such as DRAM controller and/or encryption engine are coupled only to one of the data path).
Regarding claims 13-15, please refer to the rejection of claims 8-11 since the claimed limitation is substantially similar.
Regarding claim 16, Sinclair teaches A system on a chip (SoC) chip, comprising an interconnection system (see figure 12), wherein the interconnection system comprises:
a plurality of circular data paths comprising a first lateral circular data path, a second lateral circular data path (ring buses 1204 and 1206), a first longitudinal circular data path, and a second longitudinal circular data path (ring bus 1202 and 1210);
a plurality of data routing components coupled to the plurality of circular data paths, wherein the plurality of data routing components comprise a first data routing component and a second data routing component, the first data routing component is disposed at a first intersection of and is coupled to the at least one first lateral circular data path and the first longitudinal circular data path (bus bridge 1212 at the intersection of 1204 and 1202), and the second data routing component is disposed at a second intersection of and is coupled to the second lateral circular data path and the second longitudinal circular data path (bus bridge 1218 at the intersection of 1206 and 1210); and
at least one functional component disposed at a non-intersection corresponding to one of the first lateral circular data path and the first longitudinal circular data path functional component such as controller 1220 and/or NAND die 914), wherein the at least one functional component is configured to transmit data to a destination component on another one of the first lateral circular data path and the first longitudinal circular data path through the first data routing component (see para 0066, memory modules may perform concurrent data transfers between multiple source and destination nodes along the primary ring bus 702 and secondary ring busses 704), wherein the at least one functional component is coupled only to the one of the first lateral circular data path and the first longitudinal circular data path (see figure 2, functional components such as DRAM controller and/or encryption engine are coupled only to one of the data path).
Regarding claims 17-19, please refer to the rejection of claims 2-4 since the claimed subject matter is substantially similar.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sinclair as applied to claims above, and further in view of Qin et al US 20210406676.
Regarding claim 6, Sinclair teaches all the features with respect to claim 4 as outlined above.
Sinclair further teaches the storage component comprises a memory (see figure 7, NAND die).
But Sinclair fails to teach the computing component comprises a neural network processor.
However, Qin teaches a neural network processor as a computing component in a ring bus (see figure 7, processor 735, see para 0038, the one or more cores 735-750 can be coupled in a direction ring bus configuration).
Therefore, it would have been obvious to modify the computing component of Sinclair and further incorporate a neural network processor.
The motivation for doing so is improve the computing performance of the system using neural network model.
Regarding claim 20, please refer to the rejection of claim 6 since the claimed subject matter is substantially similar.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liu et al US 20150006776 discloses an on-chip mesh interconnect having a plurality of vertical and horizontal paths.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHONG H DANG whose telephone number is (571)272-0470. The examiner can normally be reached Monday-Friday 9:30AM - 6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached at (571)272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PHONG H DANG/Primary Examiner, Art Unit 2184