Prosecution Insights
Last updated: July 17, 2026
Application No. 18/453,808

AUTOMATED SIMULATION METHOD BASED ON DATABASE IN SEMICONDUCTOR DESIGN PROCESS, AUTOMATED SIMULATION GENERATION DEVICE AND SEMICONDUCTOR DESIGN AUTOMATION SYSTEM PERFORMING THE SAME, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING THE SAME

Final Rejection §101
Filed
Aug 22, 2023
Priority
Oct 27, 2022 — RE 10-2022-0139896
Examiner
LIN, JASON
Art Unit
2117
Tech Center
2100 — Computer Architecture & Software
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
73%
Grant Probability
Favorable
3-4
OA Rounds
2m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
549 granted / 754 resolved
+17.8% vs TC avg
Strong +24% interview lift
Without
With
+23.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
22 currently pending
Career history
777
Total Applications
across all art units

Statute-Specific Performance

§101
5.8%
-34.2% vs TC avg
§103
82.2%
+42.2% vs TC avg
§102
1.7%
-38.3% vs TC avg
§112
9.0%
-31.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 754 resolved cases

Office Action

§101
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments The applicant argues that the instant application does not recite abstract idea because “obtain the reference recipe set having a similarity within a threshold to the target recipe set", to "predict a probability of a defect occurring in the semiconductor device when manufactured using a manufacturing process based on the target recipe set", and to "determine the suitability of the target recipe set based on the probability of the defect" are not mere recitation of "a mathematical concept", the examiner respectfully disagrees, "determine the suitability of the target recipe set based on the probability of the defect" as described in [0042]-[0043] is recited in high level of generality constitutes as a mental process, such as an evaluation or judgement, that can be performed in the human mind, thus, it falls into “mental process group of abstract idea, “predict a probability of a defect occurring in the semiconductor device when manufactured using a manufacturing process based on the target recipe set" as described in [0084] constitutes details of mathematical calculations of the probability of the defect occurring in the semiconductor device, thus, it falls into the “mathematical concepts” group of abstract ideas, “obtain the reference recipe set having a similarity within a threshold to the target recipe set" as described in [0077]-[0079] constitutes details of mathematical calculations similarity of reference recipes within a threshold to the targe recipe set, thus, it falls into the “mathematical concepts” group of abstract ideas. The applicant further argues that the claims reflect the improvement such as the defects may be prevented more accurately and predictably, it is noted that the improvement could not be achieved based on the current claim languages, the current claim languages does not include anything regarding the actual semiconductor manufacturing process, how can the defects be prevented more accurately and predictably when the actual semiconductor manufacturing process never happened? The applicant further cited McRo , Inc. dba Planet Blue v. Bandai Namco Games America Inc., 120 USPQ2d 1091 (Fed. Cir. 2016) and argued that the present claims provide a particular solution to a problem or a particular way to achieve a desired outcome (outcome being “make it possible determine the suitability of a new proposed manufacturing process based on the probability of defects”), it is noted that determine the suitability of a new proposed manufacturing process based on the probability of defects as described in [0042]-[0043] is recited in high level of generality constitutes as a mental process, such as an evaluation or judgement, that can be performed in the human mind, thus, it falls into “mental process group of abstract idea, and an improvement in the abstract idea itself is not an improvement in technology (see MPEP 2106.05(a)). Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-12, 16-19 and 21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract idea without significantly more. The claim(s) recite(s) mental steps involving generate a target script set corresponding to the target recipe set by comparing the target recipe set with the reference recipe set; determine the suitability of the target recipe set based on the probability of the defect and a result of the simulate of the manufacturing process, select one of the plurality of recipe sets as the reference recipe set based on a result of the performing of the similarity analysis, obtain the target script set including a plurality of target scripts by performing at least one of a script copy, a script removal and a script generation based on a result of comparing the plurality of target recipes with the plurality of reference recipes, the plurality of target scripts corresponding to the plurality of target recipes, in response to a first target recipe being identical to a first reference recipe among the plurality of reference recipes being included in the plurality of target recipes, perform the script copy such that a first target script corresponding to the first target recipe is provided to the target script set, in response to a first target recipe identical to a first reference recipe among the plurality of reference recipes being not included in the plurality of target recipes, perform the script removal such that a first target script corresponding to the first target recipe is not provided to the target script set, in response to a first reference recipe identical to a first target recipe among the plurality of target recipes being not included in the plurality of reference recipes, performing the script generation such that a first target script corresponding to the first target recipe is provided to the target script set, the generate of the target script set includes extracting wafer information, process step information and unit process description information from the target recipe set, and by applying a rule deck based on the wafer information, the process step information and the unit process description information, the target script set includes at least one wafer-level script, the wafer-level script includes at least one process-step-level script, and the process-step-level script includes at least one unit-process-level script, the target recipe set is a recipe set that has not yet been applied to the manufacturing process of the semiconductor device, the target recipe set includes a plurality of target recipes, the reference recipe set includes a plurality of reference recipes, and mathematical concept of obtain a reference recipe set by searching a database based on the target recipe set, the reference recipe set having a similarity within a threshold to the target recipe set; predict a probability of a defect occurring in the semiconductor device when manufactured using a manufacturing process based on the target recipe set, simulate the manufacturing process of the semiconductor device using the target script set; perform a similarity analysis on the target recipe set with a plurality of recipe sets; generate target deep learning model corresponding to the target recipe set based on the target recipe set, the reference recipe set and the reference deep learning model; calculate the probability of the defect based on a result of performing the manufacturing process of the semiconductor device using the reference recipe set, the target deep learning model is generated by comparing conditions and an order of the plurality of target recipes with conditions and an order of the plurality of reference recipes, by identifying a difference between the target recipe set and the reference recipe set based on a result of comparing the plurality of target recipes with the plurality of reference recipes, compare conditions and an order of a plurality of target recipes with conditions and an order of a plurality of reference recipes, the plurality of target recipes being included in the target recipe set, the plurality of reference recipes being included in the reference recipe set; predict a condition for preventing the defect from occurring in the semiconductor device when the manufacturing process of the semiconductor device is performed using the target recipe set, see MPEP 2106.04(a)(2), (claims 1-11, 16, 18 and 21). This judicial exception is not integrated into a practical application because the additional limitations of stored in the database, the plurality of recipe sets and the reference recipe set that are stored in the database are recipe sets that have been previously been applied to the manufacturing process of the semiconductor device, load a reference deep learning model corresponding to the reference recipe set among a plurality of deep learning models from the database, a database; using the database, based on the database (claims 1-4, 16, 18 and 21) represent mere data storage/retrieval which is an insignificant extrasolution activity. “perform deep learning based on the database based on the database, the target recipe set and the reference recipe set to predict, the target recipe set and the reference recipe set”, “calculate…based on the target deep learning model”, “by performing a transfer learning or re-learning on the reference deep learning model”, “predicted by performing the deep learning based on the database, the target recipe set and the reference recipe set” and “present a result of the simulate of the manufacturing process on a display device” as recited in claims 1, 4, 5, 16-18 and 21 provide nothing more than mere instructions to implement an abstract idea on a generic computer. See MPEP2106.05(f). The non-transitory computer readable medium storing program code, a processor; a memory storing a computer program for execution by the processor, an automated simulation generation device (claims 1, 18 and 21) are recited at a high level of generality and are recited as performing generic computer functions routinely used in computer applications that they represent no more than mere instructions to apply the judicial exception on a computer. These limitations can also be viewed as nothing more than an attempt to generally link the use of the judicial exception to the technological environment of a computer. It should be noted that because the courts have made it clear that mere physicality or tangibility of an additional element or elements is not a relevant consideration in the eligibility analysis, the physical nature of these computer components does not affect this analysis. See MPEP 2106.05(I) for more information on this point, including explanations from judicial decisions including Alice Corp. Pty. Ltd. v. CLS Bank Int'l, 573 U.S. 208, 224-26 (2014). Generic computer components recited as performing generic computer functions that are well-understood, routine and conventional activities amount to no more than implementing the abstract idea with a computerized system (Alice Corp. Pty. Ltd. v. CLS Bank Int’l 573 U.S. __, 134 S. Ct. 2347, 110 U.S.P.Q.2d 1976 (2014)). “the target recipe set is received from an external system located outside the device” as recited in claim 19 represent mere data gathering which is an insignificant extrasolution activity. “in response to the probability of the defect being greater than a reference value, generating a failure signal representing that the target recipe set is not suitable for the manufacturing process; and in response to the probability of the defect being less than or equal to the reference value, generating a pass signal representing that the target recipe set is suitable for the manufacturing process“ and “a result of the determine of the suitability of the target recipe set is output to the external system” as recited in claims 12 and 19 represent mere data transmission which is an insignificant extrasolution activity. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the insignificant extra-solution activity of data gathering is considered well-understood, routine, and conventional, see mpep 2106.05(d), the insignificant extra-solution activity of data transmission is considered well-understood, routine, and conventional, see mpep 2106.05(d), the insignificant extra-solution activity of data storage/retrieval is considered well-understood, routine, and conventional, see MPEP 2106.05(d)(II). The non-transitory computer readable medium storing program code, a processor; a memory storing a computer program for execution by the processor, an automated simulation generation device are recited at a high level of generality and are recited as performing generic computer functions routinely used in computer applications, which cannot provide an inventive concept. Generic computer components recited as performing generic computer functions that are well-understood, routine and conventional activities amount to no more than implementing the abstract idea with a computerized system (Alice Corp. Pty. Ltd. v. CLS Bank Int’l 573 U.S. __, 134 S. Ct. 2347, 110 U.S.P.Q.2d 1976 (2014)). “perform deep learning based on the database based on the database, the target recipe set and the reference recipe set to predict, the target recipe set and the reference recipe set”, “calculate…based on the target deep learning model”, “by performing a transfer learning or re-learning on the reference deep learning model”, “predicted by performing the deep learning based on the database, the target recipe set and the reference recipe set” and “present a result of the simulate of the manufacturing process on a display device” are at best mere instruction to “apply” the abstract ideas, which cannot provide an inventive concept. See MPEP 2106.05(f). Allowable Subject Matter Claims 1, 18 and 21 would be allowable if the rejection(s) under 35 U.S.C. 101, set forth in this Office action, are overcome. Claims 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 1, the prior art of record, US20220066411 discloses systems for detecting and correcting substrate process drift using machine learning are provided. Data associated with processing each of a first set of substrates at a manufacturing system according to a process recipe is provided as input to a trained machine learning model. One or more outputs are obtained from the trained machine learning model. An amount of drift of a first set of metrology measurement values for the first set of substrates from a target metrology measurement value is determined from the one or more outputs. Process recipe modification identifying one or more modifications to the process recipe is also determined. For each modification, an indication of a level of confidence that a respective modification to the process recipe satisfies a drift criterion for a second set of substrates is determined. In response to an identification of the respective modification with a level of confidence that satisfies a level of confidence criterion, the process recipe is updated based on the respective modification. US11436392 discloses a substrate processing apparatus for processing a substrate includes a setting device that sets a plurality of recipe items including operation conditions of the substrate processing apparatus and a recipe generating device that acquires a plurality of recipe models obtained by changing values of the plurality of recipe items and experimenting or simulating a processing result of the substrate and analyzes the plurality of recipe models to generate a recipe, the recipe generating device combining a part or all of the plurality of recipe models to generate the recipe such that a calculation value of a processing result of the substrate by the recipe satisfies a predetermined condition. US20020197745 discloses a method of controlling surface non-uniformity of a wafer in a polishing operation includes (a) providing a model for a wafer polishing that defines a plurality of regions on a wafer and identifies a wafer material removal rate in a polishing step of a polishing process for each of the regions, wherein the polishing process comprises a plurality of polishing steps, (b) polishing a wafer using a first polishing recipe based upon an incoming wafer thickness profile, (c) determining a wafer thickness profile for the post-polished wafer of step (b), and (d)calculating an updated polishing recipe based upon the wafer thickness profile of step (c) and the model of step (a) to maintain a target wafer thickness profile. The model can information about the tool state to improve the model quality. The method can be used to provide feedback to a plurality of platen stations. However, regarding claim 1, the combination of prior arts does not describe: obtain a reference recipe set by searching a database based on the target recipe set, the reference recipe set having a similarity within a threshold to the target recipe set; perform deep learning based on the database, the target recipe set and the reference recipe set to predict a probability of a defect occurring in the semiconductor device when manufactured using a manufacturing process based on the target recipe set; generate a target script set corresponding to the target recipe set by comparing the target recipe set with the reference recipe set; simulate the manufacturing process of the semiconductor device using the target script set Regarding claim 18, the prior art of record, US20220066411 discloses systems for detecting and correcting substrate process drift using machine learning are provided. Data associated with processing each of a first set of substrates at a manufacturing system according to a process recipe is provided as input to a trained machine learning model. One or more outputs are obtained from the trained machine learning model. An amount of drift of a first set of metrology measurement values for the first set of substrates from a target metrology measurement value is determined from the one or more outputs. Process recipe modification identifying one or more modifications to the process recipe is also determined. For each modification, an indication of a level of confidence that a respective modification to the process recipe satisfies a drift criterion for a second set of substrates is determined. In response to an identification of the respective modification with a level of confidence that satisfies a level of confidence criterion, the process recipe is updated based on the respective modification. US11436392 discloses a substrate processing apparatus for processing a substrate includes a setting device that sets a plurality of recipe items including operation conditions of the substrate processing apparatus and a recipe generating device that acquires a plurality of recipe models obtained by changing values of the plurality of recipe items and experimenting or simulating a processing result of the substrate and analyzes the plurality of recipe models to generate a recipe, the recipe generating device combining a part or all of the plurality of recipe models to generate the recipe such that a calculation value of a processing result of the substrate by the recipe satisfies a predetermined condition. US20020197745 discloses a method of controlling surface non-uniformity of a wafer in a polishing operation includes (a) providing a model for a wafer polishing that defines a plurality of regions on a wafer and identifies a wafer material removal rate in a polishing step of a polishing process for each of the regions, wherein the polishing process comprises a plurality of polishing steps, (b) polishing a wafer using a first polishing recipe based upon an incoming wafer thickness profile, (c) determining a wafer thickness profile for the post-polished wafer of step (b), and (d)calculating an updated polishing recipe based upon the wafer thickness profile of step (c) and the model of step (a) to maintain a target wafer thickness profile. The model can information about the tool state to improve the model quality. The method can be used to provide feedback to a plurality of platen stations. However, regarding claim 18, the combination of prior arts does not describe: obtains a reference recipe set by searching a database based on the target recipe set, the reference recipe set having a similarity within a threshold to the target recipe set; performs a deep learning based on the database, the target recipe set and the reference recipe set to predict a probability of a defect occurring in the semiconductor device when manufactured using a manufacturing process based on the target recipe set; generates a target script set corresponding to the target recipe set by comparing the target recipe set with the reference recipe set; simulates the manufacturing process of the semiconductor device using the target script set Regarding claim 21, the prior art of record, US20220066411 discloses systems for detecting and correcting substrate process drift using machine learning are provided. Data associated with processing each of a first set of substrates at a manufacturing system according to a process recipe is provided as input to a trained machine learning model. One or more outputs are obtained from the trained machine learning model. An amount of drift of a first set of metrology measurement values for the first set of substrates from a target metrology measurement value is determined from the one or more outputs. Process recipe modification identifying one or more modifications to the process recipe is also determined. For each modification, an indication of a level of confidence that a respective modification to the process recipe satisfies a drift criterion for a second set of substrates is determined. In response to an identification of the respective modification with a level of confidence that satisfies a level of confidence criterion, the process recipe is updated based on the respective modification. US11436392 discloses a substrate processing apparatus for processing a substrate includes a setting device that sets a plurality of recipe items including operation conditions of the substrate processing apparatus and a recipe generating device that acquires a plurality of recipe models obtained by changing values of the plurality of recipe items and experimenting or simulating a processing result of the substrate and analyzes the plurality of recipe models to generate a recipe, the recipe generating device combining a part or all of the plurality of recipe models to generate the recipe such that a calculation value of a processing result of the substrate by the recipe satisfies a predetermined condition. US20020197745 discloses a method of controlling surface non-uniformity of a wafer in a polishing operation includes (a) providing a model for a wafer polishing that defines a plurality of regions on a wafer and identifies a wafer material removal rate in a polishing step of a polishing process for each of the regions, wherein the polishing process comprises a plurality of polishing steps, (b) polishing a wafer using a first polishing recipe based upon an incoming wafer thickness profile, (c) determining a wafer thickness profile for the post-polished wafer of step (b), and (d)calculating an updated polishing recipe based upon the wafer thickness profile of step (c) and the model of step (a) to maintain a target wafer thickness profile. The model can information about the tool state to improve the model quality. The method can be used to provide feedback to a plurality of platen stations. However, regarding claim 18, the combination of prior arts does not describe: obtains a reference recipe set by searching a database based on the target recipe set, the reference recipe set having a similarity within a threshold to the target recipe set; performs a deep learning based on the database, the target recipe set and the reference recipe set to predict a probability of a defect occurring in the semiconductor device when manufactured using a manufacturing process based on the target recipe set; generates a target script set corresponding to the target recipe set by comparing the target recipe set with the reference recipe set; simulates the manufacturing process of the semiconductor device using the target script set Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON LIN whose telephone number is (571)270-3175. The examiner can normally be reached on Monday-Friday 9:30 a.m. – 6:00 p.m. PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Robert E. Fennema can be reached on (571)272-2748. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JASON LIN/ Primary Examiner, Art Unit 2117
Read full office action

Prosecution Timeline

Aug 22, 2023
Application Filed
Oct 21, 2025
Non-Final Rejection mailed — §101
Nov 26, 2025
Interview Requested
Dec 04, 2025
Applicant Interview (Telephonic)
Dec 04, 2025
Examiner Interview Summary
Jan 21, 2026
Response Filed
Jun 03, 2026
Final Rejection mailed — §101 (current)

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Prosecution Projections

3-4
Expected OA Rounds
73%
Grant Probability
96%
With Interview (+23.7%)
3y 1m (~2m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 754 resolved cases by this examiner. Grant probability derived from career allowance rate.

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