Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 1-3, 7-12, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Cerny et al (US 2017/0123961, herein Cerny) in view of Tyrlik et al (US 2023/0305844, herein Tyrlik).
Regarding claim 17, Cerny teaches a graphics processing system comprising:
a memory device ([0026], memory);
a graphics processor including a graphics processing cluster coupled with the memory device, the graphics processing cluster including a plurality of processing resources ([0026], GPU, processing clusters), a processing resource of the plurality of processing resources including:
first circuitry configured to execute a decoded instruction ([0024], execution unit);
a register file coupled with the first circuitry ([0023-0024], register bank); and
second circuitry configured to decode an instruction into the decoded instruction ([0022], decoder stage), the second circuitry to:
determine a number of registers within the register file that are available to a thread of the processing resource ([0023], local register availability);
decode the instruction based on an encoding ([0022], decoding).
Cerny fails to teach the system being configured to select an encoding to apply to decode the instruction based on the number of registers and decode the instruction based on the encoding.
Tyrlik teaches a graphics processing system comprising a graphics processor ([0080], GPU) including circuitry configured to decode an instruction ([0109], decoder) to select an encoding to apply to decode the instruction based on the number of registers and decode the instruction based on the encoding ([0075-0076], thread and grid size of instruction threads determined based on resource availability including register pressure).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Cerny and Tyrlik to utilize register availability when determining how to decode and execute instructions. While Cerny discloses a variety of methods for altering the available resources for instructions executing on a GPU according to runtime conditions relating to memory, Cerny does not explicitly disclose that these conditions may also account for register file availability. However, as both Cerny and Tyrlik disclose methods of resource management for executing SIMD/SIMT instructions on GPU architectures, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Claim 1 refers to a processor embodiment of the system embodiment of claim 17. The above rejection for claim 17 is thus applicable to claim 1.
Regarding claim 2, the combination of Cerny and Tyrlik teaches the graphics processor of claim 1, the second circuitry configured to: select a first encoding in response to a determination that a first number of registers are available to the thread of the processing resource; and select a second encoding in response to a determination that a second number of registers are available to the thread of the processing resource, wherein the first number of registers is greater than the second number of registers (Tyrlik [0075-0076], modifying size of thread array based on register pressure).
Regarding claim 3, the combination of Cerny and Tyrlik teaches the graphics processor of claim 2, wherein the first encoding and the second encoding are 128-bit instruction encodings (Cerny [0024], 128-bit registers).
Regarding claim 7, the combination of Cerny and Tyrlik teaches the graphics processor of claim 1, the decoded instruction to cause the first circuitry to perform a matrix operation on data stored within the register file (Tyrlik [0242], matrix operations).
Regarding claim 8, the combination of Cerny and Tyrlik teaches the graphics processor of claim 7, wherein the first circuitry includes a matrix accelerator and the decoded instruction is to cause the matrix accelerator to perform the matrix operation (Tyrlik [0080], accelerator).
Regarding claim 9, the combination of Cerny and Tyrlik teaches the graphics processor of claim 1, wherein the thread of the processing resource is a single instruction multiple data thread (Tyrlik [0094], SIMD threads).
Claims 10-12 refer to a method embodiment of the processor embodiment of claims 1-3. Therefore, the above rejections for claims 1-3 are applicable to claims 10-12, respectively.
Claim 18 refers to a system embodiment of the processor embodiment of claim 3. Therefore, the above rejection for claim 3 is applicable to claim 18.
Allowable Subject Matter
2. Claims 4-6, 13-16, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Brier (US 2014/0149744) discloses a processor wherein an encoder determines a number of iterations to perform based on a number of registers available.
Junge (US 2003/0126397) discloses a processor wherein configuration bits of an instruction register are used to determine an offset and register availability.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183
