DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-4, 6-14, 17-18 and 20 in the reply filed on 12/22/25 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 20, there is insufficient antecedent basis for limitation “the product substrate” (last line) since a substrate not been previously defined. For purpose of examination, the claim is taken to mean: contacting a bonding surface of a product substrate (line 3); singulating the product substrate to produce the plurality of articles.
Appropriate correction is requested.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6, 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Onizuka (JP H10-321673-A, see attached document) in view of Kira (JP H08-97246-A, see attached document) & Gu et al. (US 9331045, hereafter “Gu”).
Regarding claim 1, Onizuka discloses a method for bonding plurality of chips, comprising: actuating a first bonding head 13 (pressing tool) to apply a first force to a first chip 3 while the first chip is contacting a bonding surface on a substrate 1, thereby at least partially bonding the first chip to the bonding surface (fig. 4, [0007]); actuating a second bonding head 13 to apply a second force to a second chip while the second chip is contacting the bonding surface, thereby at least partially bonding the second chip to the bonding surface; and collectively actuating the first bonding head and the second bonding head to apply force to the first chip and the second chip such that the first chip and the second chip are completely bonded to the bonding surface (fig. 4D, [0019-0020]).
Onizuka discloses collectively actuating the first bonding head and the second bonding head to apply force to the first chip and the second chip and recognizes that the magnitude of the pressing force varies depending on the chip size [0016], but does not mention a magnitude of third force being larger than magnitudes of the first force and the second force. However, such technique is known in the art. Analogous to Onizuka, Kira is also directed to bonding a plurality of semiconductor chips onto a substrate (abstract), wherein the chips are partially/temporarily bonded (fig. 1, [0010]) and then completely or permanently bonded using pressing heads (fig. 2). Kira teaches using a plurality of pressing heads 2, detecting pressing force and the servo motor then adjusts and provides specific pressing force to the chips 12, including increased pressurizing force, to achieve bonding (fig. 2, [0015, 0028-0034], claim 2). Similarly, Gu (also drawn to semiconductor die laminating device- abstract) discloses a plurality of lamination or pressing units 234-240 which operate independently of each other and a controller 270 provides the pressing units with different pressures to bond the semiconductor dies 220 to a substrate 200, including relaying pressure information using pressure sensor 283 (figs. 16-18; col. 6, line 64 thru col. 7, line 16). In this manner, Gu teaches that the controller provides target higher or lower force depending on the type of semiconductor dies (col. 7, lines 17-40; col. 8, lines 55-62).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate a pressure controller and apply a greater third force while collectively actuating the first bonding head and the second bonding head in the method of Onizuka with a motivation to achieve target force depending on the type of chip/die and complete bonding as suggested by teachings of Gu & Kira.
As to claims 2 and 4, Onizuka discloses that applying the first force at initial contact of the first chip and similarly, applying the second force at initial contact of the second chip [0019], wherein the magnitude of the first force is equal to the magnitude of the second force and the first force is insufficient to fully conform the first chip to the bonding surface, and wherein the second force is insufficient to fully conform the second chip to the bonding surface.
As to claim 3, Onizuka as modified by Gu & Kira in claim 1 above discloses applying an increased third force that is sufficient to fully conform the first chip and the second chip to the bonding surface.
As to claim 6, Kira teaches chips being partially or temporarily bonded on the substrate (fig. 1, [0010]). Onizuka as modified by Gu & Kira above teaches that the controller provides the independent pressing heads with different magnitudes of pressures based on the type(s) or size(s) of chips being bonded. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date to start with lower magnitude of the initial first force and the second force within about 5-10% of the magnitude of the third force in the combined method of Onizuka, Gu & Kira in order to ensure accurate positioning of the chips on the substrate prior to heating and permanent bonding.
As to claim 14, both Onizuka and Gu discloses the first and second bonding/pressing heads being independently driven to contact the chips and this encompasses actuating the first bonding head to apply the first force prior to actuating the second bonding head to apply the second force in accordance with different size or type of the first chip versus the second chip (Onizuka- fig. 4; Gu- fig. 16).
As to claim 17, Onizuka or Kira does not show the bonding surface being a surface of a chip. However, Gu teaches that a variety of packaging configurations are known for semiconductor devices, including a multi-chip module (MCM), which involves bonding one chip to another in a stacked arrangement (Background- col. 1, lines 21-25). Consequently, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to utilize a chip bonding surface in the combined method of Onizuka, Gu & Kira with a motivation to fabricate desired assembly such as multi-chip module (MCM) as suggested by Gu.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Onizuka (JP H10-231673-A) in view of Kira (JP H08-97246-A) & Gu et al. (US 9331045) as applied to claim 1 above, and further in view of Yu et al. (US 11189507, “Yu”).
As to claim 13, Onizuka does not disclose coupling the first chip with the first bonding head and coupling the second chip with the second bonding head prior to actuating any bonding head to apply force. However, such step is known in the art. Yu (also directed to chip packaging apparatus and method- abstract) discloses multiple bond heads 41 (six shown in figs. 6-7) mounted on a beam 42, wherein the multiple bond heads are disposed to be independently movable as well as rotatable around respective axis (col. 7, lines 5-27). The multiple bond heads are configured to pick up multiple chips 70 from the pick-up platform, thereby coupling the first chip with the first bonding head and coupling the second chip with the second bonding head prior to actuating any bonding head to apply force (fig. 8; col. 7, lines 27-39). In this manner, the bonding heads have sufficient freedom of movement to perform any fine movement to complete precise placement process and can greatly improve the production efficiency (col. 7, lines 21-39). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Onizuka to have flexible bonding heads pick up the chips prior to actuating any bonding head to apply the force similar to Yu because doing so would impart freedom of movement to perform fine & precise placement steps and can greatly improve the production efficiency.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Onizuka (JP H10-231673-A, see attached document) in view of Kira (JP H08-97246-A, see attached document) & Gu et al. (US 9331045), and further in view of Foong et al. (WO 02/01612 A2, see attached document).
Regarding claim 20, Onizuka discloses a method of manufacturing a semiconductor article or package by bonding plurality of chips, comprising: actuating a first bonding head 13 (pressing tool) to apply a first force to a first chip 3 while the first chip is contacting a bonding surface on a substrate 1, thereby at least partially bonding the first chip to the bonding surface (fig. 4, [0007]); actuating a second bonding head 13 to apply a second force to a second chip while the second chip is contacting the bonding surface, thereby at least partially bonding the second chip to the bonding surface; and collectively actuating the first bonding head and the second bonding head to apply force to the first chip and the second chip such that the first chip and the second chip are completely bonded to the bonding surface (fig. 4D, [0019-0020]).
Onizuka discloses collectively actuating the first bonding head and the second bonding head to apply force to the first chip and the second chip and recognizes that the magnitude of the pressing force varies depending on the chip size [0016], but does not mention a magnitude of third force being larger than magnitudes of the first force and the second force. However, such technique is known in the art. Analogous to Onizuka, Kira is also directed to bonding a plurality of semiconductor chips onto a substrate (abstract), wherein the chips are partially/temporarily bonded (fig. 1, [0010]) and then completely or permanently bonded using pressing heads (fig. 2). Kira teaches using a plurality of pressing heads 2, detecting pressing force and the servo motor then adjusts and provides specific pressing force to the chips 12, including increased pressurizing force, to achieve bonding (fig. 2, [0015, 0028-0034], claim 2). Similarly, Gu (also drawn to semiconductor die laminating device- abstract) discloses a plurality of lamination or pressing units 234-240 which operate independently of each other and a controller 270 provides the pressing units with different pressures to bond the semiconductor dies 220 to a substrate 200, including relaying pressure information using pressure sensor 283 (figs. 16-18; col. 6, line 64 thru col. 7, line 16). In this manner, Gu teaches that the controller provides target higher or lower force depending on the type of semiconductor dies (col. 7, lines 17-40; col. 8, lines 55-62).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate a pressure controller and apply a greater third force while collectively actuating the first bonding head and the second bonding head in the method of Onizuka with a motivation to achieve target force depending on the type of chip/die and complete bonding as suggested by teachings of Gu & Kira.
Concerning the singulation step, examiner notes it is common knowledge in the semiconductor manufacturing art to singulate a substrate to produce a plurality of devices or packages. As evidence, Foong teaches that conventional ball grid array (BGA) packaging scheme for semiconductor devices includes bonding dies to the substrate, encapsulating by molding and then singulating the substrate to produce packaged devices (pg. 1 Background- lines 8-15); some sort of sawing is typically employed for singulation. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to singulate the chip-bonded substrate in the combined method of Onizuka, Gu & Kira with a purpose to fabricate plurality of packaged devices, as taught by Foong.
Allowable Subject Matter
Claims 7-12 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including ALL of the limitations of the base claim and any intervening claims. None of prior art discloses or suggests bowing the first chip and bowing the second chip as recited.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/14/25, 8/22/23 complies with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Inquiry
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/DEVANG R PATEL/
Primary Examiner, AU 1735