DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Asahi et al. (WO 2018/110376 A1, hereafter “Asahi”, see attached document) in view of Onizuka (JP H10-321673-A, of record), and further in view of Kira (JP H08-97246-A, of record) & Gu et al. (US 9331045, hereafter “Gu”).
Regarding claim 1, Asahi discloses a method for bonding plurality of chips C (see fig. 14), comprising: actuating a first bonding head (e.g. bond head 204- fig. 12 or 304- fig. 13) to apply a first force to a first chip while the first chip is contacting a bonding surface on a substrate W (wafer- fig. 11, [0002-0003]), thereby at least partially bonding the first chip to the bonding surface without completely bonding the first chip to the bonding surface (fig. 11B- see diagram below); applying a second force to a second chip (another chip C) while the second chip is contacting the bonding surface, thereby at least partially bonding the second chip to the bonding surface without completely bonding the first chip to the bonding surface (fig. 11b- see diagram below); and then collectively bonding chips such that the first chip and the second chip are completely bonded to the bonding
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surface (fig. 11d, see diagram below). Examiner also notes that presence of any adhesive (R in Asahi) for bonding is not excluded by the claims.
Asahi shows bonding plurality of chips (fig. 14), but does not explicitly show a separate second bonding head and collectively actuating both the first bonding head and the second bonding head to apply force to the first chip and the second chip, thereby completely bonding both the first and second chips. However, using plurality of bonding heads is known in the art. Onizuka (also directed to bonding of chips with bumps- abstract) discloses a bonding block 12 , comprising a plurality of bonding heads 13 (pressing tools) to apply force to respective chips 3 while the chips are contacting a bonding surface on a substrate 1 (figs. 1, 4; [0007]). Onizuka also teaches collectively actuating the first & the second bonding heads 13 to apply force to the first chip and the second chip such that the first chip and the second chip are completely bonded to the bonding surface (fig. 4D, [0019-0020]). Accordingly, it would have been obvious to one of ordinary skill in the art to utilize a plurality of bonding heads similar to Onizuka in the method of Asahi since such tool is common knowledge and moreover, for the purpose of bonding a large number of chips, as desired by Asahi. Thus, Asahi as modified by Onizuka discloses a second bonding head to apply a second force to a second chip while the second chip is contacting the bonding surface, thereby partially bonding the second chip to the bonding surface without completely bonding the second chip; and then collectively actuating the first bonding head and the second bonding head to apply force to the first & second chips such that the chips are completely bonded to the bonding surface of the substrate/wafer.
Onizuka discloses collectively actuating the first bonding head and the second bonding head to apply force to the first chip and the second chip and recognizes that the magnitude of the pressing force varies depending on the chip size [0016], but does not mention a magnitude of third force being larger than magnitudes of the first force and the second force. Such technique is known in the art. Analogous to Onizuka, Kira is also directed to bonding a plurality of semiconductor chips onto a substrate (abstract), wherein the chips are partially/temporarily bonded (fig. 1, [0010]) and then completely or permanently bonded using pressing heads (fig. 2). Kira teaches using a plurality of pressing heads 2, detecting pressing force and the servo motor then adjusts and provides specific pressing force to the chips 12, including increased pressurizing force, to achieve bonding (fig. 2, [0015, 0028-0034], claim 2). Similarly, Gu (also drawn to semiconductor die laminating device- abstract) discloses a plurality of lamination or pressing units 234-240 which operate independently of each other and a controller 270 provides the pressing units with different pressures to bond the semiconductor dies 220 to a substrate 200, including relaying pressure information using pressure sensor 283 (figs. 16-18; col. 6, line 64 thru col. 7, line 16). In this manner, Gu teaches that the controller provides target higher or lower force depending on the type of semiconductor dies (col. 7, lines 17-40; col. 8, lines 55-62).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate a pressure controller and apply a greater third force while collectively actuating the first bonding head and the second bonding head in the method of Asahi & Onizuka with a motivation to achieve target force depending on the type of chip/die and complete bonding as suggested by teachings of Gu & Kira.
As to claims 2 and 4, Asahi shows that applying the first force at initial contact of the first chip and similarly, applying the second force at initial contact of the second chip (fig. 11b, c), wherein the magnitude of the first force is equal to the magnitude of the second force and the first force is insufficient to fully conform the first chip to the bonding surface, and wherein the second force is insufficient to fully conform the second chip to the bonding surface.
As to claim 3, the combination of Asahi, Onizuka, Gu & Kira in claim 1 above discloses applying an increased third force that is sufficient to fully conform the first chip and the second chip to the bonding surface.
As to claim 6, both Asahi (fig. 11) and Kira teaches chips being partially or temporarily bonded on the substrate (fig. 1, [0010]). Onizuka as modified by Gu & Kira above teaches that the controller provides the independent pressing heads with different magnitudes of pressures based on the type(s) or size(s) of chips being bonded. Accordingly, it would have been obvious to one of ordinary skill in the art to start with lower magnitude of the initial first force and the second force within about 5-10% of the magnitude of the third force in the combined method of Asahi, Onizuka, Gu & Kira in order to ensure accurate positioning of the chips on the substrate prior to heating and permanent bonding.
As to claim 14, both Onizuka and Gu discloses the first and second bonding/pressing heads being independently driven to contact the chips and this encompasses actuating the first bonding head to apply the first force prior to actuating the second bonding head to apply the second force in accordance with different size or type of the first chip versus the second chip (Onizuka- fig. 4; Gu- fig. 16).
As to claim 17, Onizuka or Kira does not show the bonding surface being a surface of a chip. However, Gu teaches that a variety of packaging configurations are known for semiconductor devices, including a multi-chip module (MCM), which involves bonding one chip to another in a stacked arrangement (Background- col. 1, lines 21-25). Consequently, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to utilize a chip bonding surface in the combined method of Asahi, Onizuka, Gu & Kira with a motivation to fabricate desired assembly such as multi-chip module (MCM) as suggested by Gu.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Asahi, Onizuka, in view of Kira & Gu as applied to claim 1 above, and further in view of Yu et al. (US 11189507, “Yu”).
As to claim 13, Asahi does not show coupling the first chip with the first bonding head and coupling the second chip with the second bonding head prior to actuating any bonding head to apply force. However, such step is known in the art. Yu (also directed to chip packaging apparatus and method- abstract) discloses multiple bond heads 41 (six shown in figs. 6-7) mounted on a beam 42, wherein the multiple bond heads are disposed to be independently movable as well as rotatable around respective axis (col. 7, lines 5-27). The multiple bond heads are configured to pick up multiple chips 70 from the pick-up platform, thereby coupling the first chip with the first bonding head and coupling the second chip with the second bonding head prior to actuating any bonding head to apply force (fig. 8; col. 7, lines 27-39). In this manner, the bonding heads have sufficient freedom of movement to perform any fine movement to complete precise placement process and can greatly improve the production efficiency (col. 7, lines 21-39). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Asahi to have flexible bonding heads pick up the chips prior to actuating any bonding head to apply the force similar to Yu because doing so would impart freedom of movement to perform fine & precise placement steps and can greatly improve the production efficiency.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Asahi et al. (WO 2018/110376 A1, “Asahi”, see attached document) in view of Onizuka (JP H10-321673-A, of record), Kira (JP H08-97246-A, of record) & Gu et al. (US 9331045), and further in view of Foong et al. (WO 02/01612 A2, of record).
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Regarding claim 20, Asahi discloses a method for bonding plurality of chips C (fig. 14), comprising: actuating a first bonding head (e.g. bond head 204- fig. 12 or 304- fig. 13) to apply a first force to a first chip while the first chip is contacting a bonding surface on a substrate W (wafer- fig. 11, [0002-0003]), thereby at least partially bonding the first chip to the bonding surface without completely bonding the first chip to the bonding surface (fig. 11B- see diagram below); applying a second force to a second chip (another chip C) while the second chip is contacting the bonding surface, thereby at least partially bonding the second chip to the bonding surface without completely bonding the first chip to the bonding surface (fig. 11b- see diagram); and then collectively bonding chips such that the first chip and the second chip are completely bonded to the bonding surface (fig. 11d, see diagram below). Examiner also notes that presence of any adhesive (R in Asahi) for bonding is not excluded by the claims.
Asahi shows bonding plurality of chips (fig. 14), but does not explicitly show a separate second bonding head and collectively actuating both the first bonding head and the second bonding head to apply force to the first chip and the second chip, thereby completely bonding both the first and second chips. However, using plurality of bonding heads is known in the art. Onizuka (also directed to bonding of chips with bumps- abstract) discloses a bonding block 12 , comprising a plurality of bonding heads 13 (pressing tools) to apply force to respective chips 3 while the chips are contacting a bonding surface on a substrate 1 (figs. 1, 4; [0007]). Onizuka also teaches collectively actuating the first & the second bonding heads 13 to apply force to the first chip and the second chip such that the first chip and the second chip are completely bonded to the bonding surface (fig. 4D, [0019-0020]). Accordingly, it would have been obvious to one of ordinary skill in the art to utilize a plurality of bonding heads similar to Onizuka in the method of Asahi since such tool is common knowledge and moreover, for the purpose of bonding a large number of chips, as desired by Asahi. Thus, Asahi as modified by Onizuka discloses a second bonding head to apply a second force to a second chip while the second chip is contacting the bonding surface, thereby partially bonding the second chip to the bonding surface without completely bonding the second chip; and then collectively actuating the first bonding head and the second bonding head to apply force to the first & second chips such that the chips are completely bonded to the bonding surface of the substrate/wafer.
Onizuka discloses collectively actuating the first bonding head and the second bonding head to apply force to the first chip and the second chip and recognizes that the magnitude of the pressing force varies depending on the chip size [0016], but does not mention a magnitude of third force being larger than magnitudes of the first force and the second force. Such technique is known in the art. Analogous to Onizuka, Kira is also directed to bonding a plurality of semiconductor chips onto a substrate (abstract), wherein the chips are partially/temporarily bonded (fig. 1, [0010]) and then completely or permanently bonded using pressing heads (fig. 2). Kira teaches using a plurality of pressing heads 2, detecting pressing force and the servo motor then adjusts and provides specific pressing force to the chips 12, including increased pressurizing force, to achieve bonding (fig. 2, [0015, 0028-0034], claim 2). Similarly, Gu (also drawn to semiconductor die laminating device- abstract) discloses a plurality of lamination or pressing units 234-240 which operate independently of each other and a controller 270 provides the pressing units with different pressures to bond the semiconductor dies 220 to a substrate 200, including relaying pressure information using pressure sensor 283 (figs. 16-18; col. 6, line 64 thru col. 7, line 16). In this manner, Gu teaches that the controller provides target higher or lower force depending on the type of semiconductor dies (col. 7, lines 17-40; col. 8, lines 55-62).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate a pressure controller and apply a greater third force while collectively actuating the first bonding head and the second bonding head in the method of Asahi & Onizuka with a motivation to achieve target force depending on the type of chip/die and complete bonding as suggested by teachings of Gu & Kira.
Concerning the singulation step, examiner notes this is common knowledge in the semiconductor manufacturing art to singulate a substrate to produce a plurality of devices or packages. As evidence, Foong teaches that conventional ball grid array (BGA) packaging scheme for semiconductor devices includes bonding dies to the substrate, encapsulating by molding and then singulating the substrate to produce packaged devices (pg. 1 Background- lines 8-15); some sort of sawing is typically employed for singulation. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to singulate the chip-bonded substrate in the combined method of Onizuka, Gu & Kira with a purpose to fabricate plurality of packaged devices, as taught by Foong.
Allowable Subject Matter
Claim 21 is allowed.
Claims 7-12 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including ALL of the limitations of the base claim and any intervening claims. None of prior art discloses or suggests bowing the first chip and bowing the second chip as recited.
Response to Amendment and Arguments
Applicant’s arguments with respect to amended claim(s) 1 and 20 have been considered but are moot in light of new grounds of rejection set forth above. Current 103 rejection now also includes new reference of Asahi and addresses the added matter specifically challenged in the arguments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/9/26 complies with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVANG R PATEL whose telephone number is (571) 270-3636. The examiner can normally be reached on Monday-Friday 8am-5pm, EST.
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/DEVANG R PATEL/
Primary Examiner, AU 1735
Prosecution Insights