Prosecution Insights
Last updated: October 02, 2026
Application No. 18/453,956

HYSTERIC CONTROL FOR RESONANT CONVERTERS

Non-Final OA §102
Filed
Aug 22, 2023
Examiner
TIKU, SISAY G
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
2 (Non-Final)
91%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
667 granted / 730 resolved
+23.4% vs TC avg
Moderate +9% lift
Without
With
+9.2%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
25 currently pending
Career history
741
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
50.3%
+10.3% vs TC avg
§102
31.4%
-8.6% vs TC avg
§112
12.1%
-27.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 730 resolved cases

Office Action

§102
Detailed Action Summary Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . 1. This office action is in response to the RCEX application filed on July 02, 2026. 2. Claims 1,3-13, and 15-23 are pending and has been examined. Continued Examination Under 37 CFR 1.114 3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 07/02/2026 has been entered. Drawings 4. Drawings submitted on 08/22/2023 and 01/26/2026 are acceptable. Claim Rejections - 35 USC § 102 5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 18-21 are rejected under 35 U.S.C. 102(a)(1) (a)(2) as being anticipated by Du “20240388200”. In re to claim 18, Du discloses a method (Figs. 1-10 shows resonant converter dynamic control system and a method ) comprising: receive a first voltage from an output of a resonant converter (Fig.1: output voltage controller configured to receive Vout) ; receive a second voltage across a capacitor of the resonant converter (the resonant tank charge sampling circuit is configured to acquiring and transmitting an output voltage signal based on the voltage across the CR terminals); receive a reference voltage (output voltage controller is configured to receive Vref); receive a current measurement signal from the output of the resonant converter (output current feedforward unit configured to receive Iout); and generate by a resonant controller (Fig. 1 excluding the inverter, rectifier circuit and resonant LLC are equivalent to controller) a switching signal of the resonant converter (PWM unit is configured to generate Vgs signal to the half or full bridges based on the) responsive to the first voltage (Vout) , the second voltage (voltage across the CR terminals), and the current measurement signal (Iout) to regulate the first voltage based on the reference voltage (Vref. Furthermore, see prag. 0014,0028,0033,0035,0056,0072), wherein, generating the switching signal (Vgs) comprises: generating a first signal based on the current measurement signal (Iout); generating a second signal representing a difference between the first voltage (Vout) and the reference voltage (Vref); generating a sum of the first signal and the second signal (judgement feed ward circuit is configured to sum the output from the output voltage control unit which compares Vref and Vout and Iout) and generating the switching signal (Vgs) based on the sum and the second voltage (comparator is configured to receive Vc and voltage across the CR terminals and generate signal to counter). In re to claim 19, Du as modified discloses (Figs. 1-10) wherein the first signal is a linear function of the current measurement signal (Examiner noted that the current output Iout direct proportion to the current measurement of the resonant converter output is equivalent to liner function of the current measurement signal). In re to claim 20, Du discloses a non-transitory computer readable medium storing instructions that, when executed by processor circuitry, cause the processor circuitry to (Figs. 1-10 shows resonant converter dynamic control system and a method. Furthermore, see Fig. 10 and parag.0089 and 0091) : receive a first voltage from an output of a resonant converter (output voltage controller configured to receive Vout) ; receive a second voltage across a capacitor of the resonant converter (the resonant tank charge sampling circuit is configured to acquiring and transmitting an output voltage signal based on the voltage across the CR terminals); receive a reference voltage (output voltage controller is configured to receive Vref); receive a current measurement signal from the output of the resonant converter (output current feedforward unit configured to receive Iout); and generate a switching signal of the resonant converter (PWM unit is configured to generate Vgs signal to the half or full bridges based on the) responsive to the first voltage (Vout) , the second voltage (voltage across the CR terminals), and the current measurement signal (Iout) to regulate the first voltage based on the reference voltage (Vref. Furthermore, see prag. 0014,0028,0033,0035,0056,0072), wherein, generating the switching signal (Vgs) comprises: generating a first signal based on the current measurement signal (Iout); generating a second signal representing a difference between the first voltage (vout) and the reference voltage (Vref); generating a sum of the first signal and the second signal (judgement feed ward circuit is configured to sum the output from the output voltage control unit which compares reference value and Vout, and Iout) and generating the switching signal (Vgs) based on the sum and the second voltage (comparator is configured to receive Vc and voltage across the CR terminals and generate signal to counter). In re to claim 21, Du as modified discloses wherein the instructions, when executed, cause the processor circuitry to (see prag.0089 and 0091 and Fig.10): wherein the first signal is a linear function of the current measurement signal (Examiner noted that the current output Iout direct proportion to the current measurement of the resonant converter output is equivalent to liner function of the current measurement signal). Allowable Subject Matter 7. Claims 1,3-13,15-17 and 22-23 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Claim 1 is allowed because the prior art of record fails to disclose or suggest an apparatus including the limitation of “a current feedforward circuit having a feedforward input and a feedforward output, the feedforward input coupled to the converter current sensing terminal; a compensator having a first compensator input, a second compensator input, and a compensator output, the first compensator input coupled to the converter voltage sensing terminal, the second compensator input coupled to the reference voltage terminal, a summation circuit having a first summation input, a second summation input, and a summation output, the first summation input coupled to the feedforward output, and the second summation input coupled to the compensator output; and a control signal generation circuit having a first control input, a second control input, and the first and second control outputs, the first control input coupled to the first and second converter capacitor terminals, and the second control input coupled to the summation output, and the control signal generation circuit configurable to generate first and second switching signals at the first and second control outputs.” Claim 13 is allowed because the prior art of record fails to disclose or suggest a power converter including the limitation of “a current feedforward circuit having a feedforward input and a feedforward output, the feedforward input coupled to the converter current sensing terminal; a compensator having a first input, a second input, and a compensator output, the first input coupled to the converter voltage sensing terminal, the second input coupled to the reference voltage terminal; a summation circuit having a first summation input, a second summation input, and a summation output, the first summation input coupled to the feedforward output, and the second summation input coupled to the compensator output; and a control signal generation circuit having a first control input, a second control input, and the first and second control outputs, the first control input of the control signal generation circuit coupled to the first and second converter capacitor terminals, and the second control input coupled to the summation output.” Claims 3-12 and 22 depends from claim 1, thus are also allowed because of their dependency. Claims 15-17 and 23 depends from claim 13, thus are also allowed because of their dependency. Conclusion 8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tran, Thienvu Vu can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SISAY G TIKU/ Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Aug 22, 2023
Application Filed
Sep 26, 2025
Non-Final Rejection mailed — §102
Jan 26, 2026
Response Filed
Feb 27, 2026
Examiner Interview (Telephonic)
Jul 02, 2026
Request for Continued Examination
Jul 08, 2026
Response after Non-Final Action
Jul 13, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12749986
ISOLATED POWER SUPPLY, CONTROL CIRCUIT AND METHOD THEREOF
2y 3m to grant Granted Sep 29, 2026
Patent 12747849
HYBRID LED / PHOTOLUMINESCENT SIGNS
1y 11m to grant Granted Sep 29, 2026
Patent 12738859
SWITCHING POWER SUPPLY AND POWER FACTOR CORRECTION CONTROLLER THEREFOR HAVING IMPROVED INPUT CURRENT SENSING
2y 5m to grant Granted Sep 15, 2026
Patent 12738844
CONVERSION UNIT
2y 5m to grant Granted Sep 15, 2026
Patent 12738846
POWER SUPPLY AND OPERATING METHOD THEREOF
2y 0m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

2-3
Expected OA Rounds
91%
Grant Probability
99%
With Interview (+9.2%)
1y 10m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 730 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month