Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-Final Office Action
DETAILED ACTION
Examiner’s Notes
(a) Claim date: 08/22/2023.
(b) Priority date: 04/20/2020.
Claim Rejections - 35 USC 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:A person shall be entitled to a patent unless:(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.Claims 1-6, 12-15 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Gofman (US9673612B2).
(As to claim 1, Gofman discloses)
1. (Original) A circuit, comprising:
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a first switch comprising a source, a gate, a drain, and a first diode, wherein the source of the first switch is connected to an anode of the first diode, wherein the gate of the first switch is connected to a positive terminal of a first battery, and wherein the drain of the first switch is connected to a cathode of the first diode and to the positive terminal of the
first battery [Fig. 9: the gate of P-channel MOSFET 932a is coupled to negative battery terminal connector 944a, and in Col. 9 Gofman discloses that "the drain of first P-channel MOSFET 932a can be coupled to a positive battery terminal connector 942a," disclosing a first switch with source, gate, drain, and body diode wherein the drain is connected to the cathode of the diode and to the positive terminal of the first battery];
and a second switch having an opposite polarity to the first switch, wherein the second switch comprises a source, a gate, a drain, and a second diode, wherein the source of the second switch is connected to an anode of the second diode and to the source of the first switch [Fig. 9: N-channel MOSFET 933a has an opposite polarity to P-channel MOSFET 932a, with a source (designated "S") coupled to negative load terminal 936, a gate (designated "G") coupled to positive battery terminal connector 942a, a drain (designated "D") coupled to the drain of P-channel MOSFET 932a, and an intrinsic body diode],
wherein the gate of the second switch is connected to the gate of the first switch, and wherein the drain of the second switch is connected to a cathode of the second diode and to a first side of a load [Fig. 9, Col. 9: the source of first N-channel MOSFET 933a can be coupled to a negative load terminal 936 and the drain of N-channel MOSFET 933a is coupled to the drain of P-channel MOSFET 932a and to positive load terminal 934 (first side of a load), disclosing the second switch of opposite polarity with the required source, gate, drain, and diode connections].
(As to claim 2, Gofman discloses)
2. (Original) The circuit of claim 1, further comprising a third switch comprising a source, a gate, a drain, and a third diode, wherein the source of the third switch is connected to an anode of the third diode, the positive terminal of a second battery via one or more resistors, the negative terminal of the second battery, and a second side of the load [Col. 9 that "resistive elements (e.g., resistors) can optionally be coupled in series between a battery terminal and a MOSFET gate," disclosing the third switch with source connected to the second battery positive terminal via resistors, to the negative terminal, and to the second side of the load].
(As to claim 3, Gofman discloses)
3. (Original) The circuit of claim 2, wherein the gate of the third switch is connected to the positive terminal of the second battery [Fig. 9: MOSFET 933a, the gate of the third switch connected to the positive terminal of the second battery].
(As to claim 4, Gofman discloses)
4. (Original) The circuit of claim 3, wherein the drain of the third switch is connected to the drain of the second switch and to the first side of a load [Fig. 9: drain of the third switch connected to the drain of the second switch and to the first side of the load].
(As to claim 5, Gofman discloses)
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5. (Original) The circuit of claim 1, wherein the second switch prevents electrical current from flowing into the first battery when the second switch is in an off state, which allows the first battery to be arranged in a parallel configuration with additional batteries with reduced risk of an internal fault from drawing the electrical current above a predetermined threshold into one of the additional batteries that has failed [Fig. 10: in the event of a reverse battery connection, "second P-channel MOSFET 932b can switch into a non-conductive state" and "second N-channel MOSFET 933b" also switches off, allowing parallel battery operation with reduced fault risk].
(As to claim 6, Gofman discloses)
6. (Original) A battery assembly, comprising:
NOTE: under claim 1 rejection, the first and the second switch functionality are fully described. Below, the rejection for only the third switch is added.
[Col. 9-10, Fig. 9: battery protection circuit 900 comprises P-channel MOSFET 932a (first switch), N-channel MOSFET 933a (second switch of opposite polarity), and battery protection cell 940b with P-channel MOSFET 932b and N-channel MOSFET 933b (third switch for second battery), all with the source, gate, drain, and diode connections as disclosed for claim 1, disclosing the complete battery assembly circuit].
(As to claim 12, 13, Gofman discloses)
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12. (Original) The battery assembly of claim 6, wherein the source of the third switch is connected to a positive terminal of the second battery via one or more resistors [Fig. 11, 1139a and 1139b].
(As to claim 14, Gofman discloses)
14. (Original) The battery assembly of claim 6, wherein the negative terminal of the second battery is connected to the second side of the load [Fig. 11, 1130].
(As to claim 15, Gofman discloses)
15. (Original) The battery assembly of claim 6, wherein the third switch is configured to bring the negative terminal of the first battery and negative terminals of additional batteries to a single reference voltage when the first battery and the additional batteries are connected in a series configuration [Claim 9, “third battery terminal”].
Allowable Subject Matter
The following claims would be allowable if all rejections/objections cited in this office action (if any) are overcome and rewritten to include all of the limitations of the base claim and any intervening claims.The reason for this allowance is: the claimed subject matter could not have been anticipated or obviated using any prior arts.Allowable claims are: 7-11, 16-20.
Conclusion
The prior art made of record in the form PTO-892 are not relied upon is considered pertinent to applicant's disclosure.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.Contact information:Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED ALAM whose telephone number is (571) 270-1507, email address: [mohammed.alam@uspto.gov] and fax number (571) 270-2507. The examiner can normally be reached on 10AM to 4PM (EST), Monday to Friday. If attempts to reach the examiner by telephone are unsuccessful, the Examiner's Supervisor, JACK CHIANG can be reached on (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300./Mohammed Alam/Primary Examiner, Art Unit 2851
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