DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 08/23/2023 has been considered and
placed in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (U.S. 6,696,894).
Regarding claim 1, Huang (hereinafter, Ref~894) discloses (please see Figs. 2-3 and related text for details) a differential input circuit (Figs. 2-3), comprising:
a P-channel field effect transistor (FET) differential input pair (MP1/PM2 of Fig. 3);
an N-channel FET differential input pair (MN1/MBN2 of Fig. 3);
a first power supply line (VDD line of Fig. 3), configured to receive a first voltage (VDD of Fig. 3);
a second power supply line (VSS line of Fig. 3), configured to receive a second voltage (VSS of Fig. 3) lower than the first voltage;
a first P-channel FET (MP3 of Fig. 3);
a constant current source (30 of Fig. 3), disposed between the first power supply line and the P-channel FET differential input pair, and between the first power supply line (VDD) and the first P-channel field effect transistor as seen;
a current mirror circuit (formed by MN3/MN4 of Fig. 3), disposed between the first P-channel FET and the second power supply line (VSS), and between the N-channel FET differential input pair and the second power supply line as seen; and
a logic circuit (not expressly shown, but a comparison feature/circuit would be needed to at least provide comparison between Vcm and Vth as described in col. 3, between lines 40-55 in order to turn on/off MP3, thus said feature/circuit can be read as the claimed feature OR at least it is functionally equivalent to the claimed one), configured to supply a binarized logic signal to a gate of the first P-channel FET, meeting claim 1.
Regarding claim 2, Ref~894 supports the claimed “wherein a high level of the logic signal is the first voltage, and a low level of the logic signal is the second voltage”, since said MP3 of Fig. 3 is being turned ON/OFF, thus obviating said low/high logic level claimed relative to the Vcm as described in col. 3, between lines 40-55, meeting claim 2.
Regarding claims 7-8, Ref~894 discloses an amplifier (see amplifier of Figs. 2-3), comprising the differential input circuit of Claim 1, meeting claim 7.
Regarding claim 8, Ref~894 discloses an amplifier (see amplifier of Figs. 2-3), comprising the differential input circuit of Claim 2, meeting claim 8.
Allowable Subject Matter
Claims 3-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/HIEU P NGUYEN/Primary Examiner, Art Unit 2843