DETAILED ACTION
This action is in response to the 03/09/2026 amendment.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claim(s) 1 – 5 and 9 – 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2014/0176091; (hereinafter Chiang) in view of US Pub. No. 2019/0229612; (hereinafter Chen).
Regarding claim 1, Chiang [e.g. Figs. 2 - 5] discloses a controller comprising a ramp generator [e.g. Fig. 2; 230] for generating a ramp signal [e.g. VRAMP]; a ramp adjuster [e.g. Fig. 2; 220] adapted to compare [e.g. 224] a feedback signal [e.g. at inverting input of 224] of the converter [e.g. 270, 280] with a threshold signal [e.g. TB] to obtain a comparison signal [e.g. VADJ; paragraph 032 recites “The comparator 224 compares the output voltage VOUT and the transient boost voltage TB to generate the adjusting signal VADJ”], and to adjust an amplitude of the ramp signal based on the comparison signal [e.g. Fig. 3 at t1; paragraph 038 recites “when the adjusting signal VADJ is generated, it indicates the transient of the output voltage VOUT occurs. The combination logic circuit 230 rapidly pulls the ram signal VRAMP to zero (or pulls down to the lowest) and maintains over the predetermined time t1”].
Chiang fails to disclose wherein the ramp generator comprises a capacitor coupled to a resistance circuit comprising a plurality of resistances, and wherein the comparison signal is configured to activate or de-activate one or more switches coupled to the plurality of resistances.
Chen [e.g. Figs. 2 and 5] teaches wherein the ramp generator [e.g. Fig. 2; 14] comprises a capacitor [e.g. Fig. 5; Ci] coupled to a resistance circuit comprising a plurality of resistances [e.g. Fig. 5; S3, S4, gm2], and wherein the comparison signal [e.g. EAO] is configured to activate or de-activate one or more switches [e.g. Fig. 5; switch in voltage-control current source (gm1) which is activated and de-activated in order to control the current flow of I1; paragraph 044 recites “the first slope control circuit gm1 can be a voltage-control current source. Examiner note: As it is well known in the art a voltage-control current source comprises a switch] coupled to the plurality of resistances [e.g. Fig. 5; gm1 using EAO to couple by current I1; paragraph 044].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Chiang by wherein the ramp generator comprises a capacitor coupled to a resistance circuit comprising a plurality of resistances, and wherein the comparison signal is configured to activate or de-activate one or more switches coupled to the plurality of resistances as taught by Chenin order of being able to provide high precision and fast response, paragraph 02.
Regarding claim 2, Chiang [e.g. Figs. 2 - 5] discloses wherein the comparison signal is a logic signal [e.g. See Vadj in Fig. 3].
Regarding claim 3, Chiang [e.g. Figs. 2 – 5] discloses wherein during steady state the ramp signal has a steady state amplitude [e.g. Fig. 3; before t1], and wherein the ramp adjuster [e.g. Fig. 2; 220] is configured so that when the feedback signal decreases to reach a value equal or lower than the threshold signal [e.g. TB], the logic signal changes state [e.g. Fig. 5] to reduce the amplitude of the ramp signal below the steady state amplitude [e.g. Fig. 3; at t1].
Regarding claim 4, Chiang [e.g. Figs. 2 – 5] discloses comprising a comparator [e.g. Fig. 2; 250] adapted to compare the ramp signal [e.g. VRAMP] with a first reference voltage [e.g. VCOMP] to generate a driver control signal [e.g. V1].
Regarding claim 5, Chiang fails to disclose comprising a voltage supply adapted to generate a second reference voltage, wherein the threshold signal is equal to the second reference voltage, and wherein the second reference voltage is less than the first reference signal.
It would have been obvious to one having ordinary skill in the art before the effective filing date to comprising a voltage supply adapted to generate a second reference voltage, wherein the threshold signal is equal to the second reference voltage, and wherein the second reference voltage is less than the first reference signal, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable value involves only routine skill in the art. In re Aller, 105 USPQ 233.
It should be noted that MPEP 2144.05 (II) states that it is not inventive to discover the optimum or workable value when the general conditions are disclosed in the prior art. Since Chiang, in general, discloses that parameters of TB and VCOMP and comparator 224 and 250 can be designed/selected as choice, it would have been obvious for one of ordinary skill in the art, through routine experimentation, to determine the optimal values of the reference and threshold values so to provide a proper transient response.
Regarding claim 9, Chiang [e.g. Figs. 2 – 5] discloses a power converter comprising a controller as claimed in claim 1, coupled to a power stage [e.g. 270 and inductor], the power stage comprising a high side power switch [e.g. 276] coupled to a low side power switch [e.g. 278] at a switching node [e.g. having SDRIVE]; an inductor [inductor in 280] and a driver [e.g. 272, 274] configured to drive the high side and low side power switches.
Regarding claim 10, Chiang [e.g. Figs. 2, 4 – 5 and 7] discloses wherein the power converter is a constant on time converter [e.g. Fig. 7; paragraph 040 recites “FIG. 7 is a schematic diagram illustrating waveforms under a constant on time (COT) structure according to an embodiment of the invention. Referring to FIG. 7, the waveform of the ramp signal VRAMP here is an inverted triangle as compared to the waveform depicted in FIG. 3. The DC-DC converter 200 is applied under the COT structure, so that when a load current ILOAD is increased, namely, the transient boost voltage TB occurs, the positive pulse of the adjusting signal VADJ is generated”].
Regarding claim 11, Chiang [e.g. Figs. 2 - 5] discloses a method of controlling a converter, the method comprising: generating a ramp signal [e.g. VRAMP]; comparing [e.g. 224] a feedback signal [e.g. at inverting input of 224] of the converter with a threshold signal [e.g. TB] to obtain a comparison signal [e.g. VADJ; paragraph 032 recites “The comparator 224 compares the output voltage VOUT and the transient boost voltage TB to generate the adjusting signal VADJ”]; and adjusting an amplitude of the ramp signal based on the comparison signal [e.g. Fig. 3 at t1; paragraph 038 recites “when the adjusting signal VADJ is generated, it indicates the transient of the output voltage VOUT occurs. The combination logic circuit 230 rapidly pulls the ram signal VRAMP to zero (or pulls down to the lowest) and maintains over the predetermined time t1”].
Chiang fails to disclose the ramp generator comprising a capacitor coupled to a resistance circuit comprising a plurality of resistances, and activating or deactivating one or more switches coupled to the plurality of resistances by the comparison signal.
Chen [e.g. Figs. 2 and 5] teaches the ramp generator [e.g. Fig. 2; 14] comprising a capacitor [e.g. Fig. 5; Ci] coupled to a resistance circuit comprising a plurality of resistances [e.g. Fig. 5; S3, S4, gm2], and activating or deactivating one or more switches [e.g. Fig. 5; switch in voltage-control current source (gm1) which is activated and de-activated in order to control the current flow of I1; paragraph 044 recites “the first slope control circuit gm1 can be a voltage-control current source. Examiner note: As it is well known in the art a voltage-control current source comprises a switch] coupled to the plurality of resistances by the comparison signal [e.g. EAO which control gm1 allowing current flow I1, paragraph 044].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Chiang by the ramp generator comprising a capacitor coupled to a resistance circuit comprising a plurality of resistances, and activating or deactivating one or more switches coupled to the plurality of resistances by the comparison signal as taught by Chenin order of being able to provide high precision and fast response, paragraph 02.
Regarding claim 12, Chiang [e.g. Figs. 2 - 5] discloses wherein the comparison signal is a logic signal [e.g. See Vadj in Fig. 3].
Regarding claim 13, Chiang [e.g. Figs. 2 – 5] discloses wherein during steady state the ramp signal has a steady state amplitude [e.g. Fig. 3; before t1], and wherein when the feedback signal decreases to reach a value equal or lower than the threshold signal, the logic signal changes state [e.g. Fig. 5] to reduce the amplitude of the ramp signal below the steady state amplitude [e.g. Fig. 3; at t1].
Regarding claim 14, Chiang [e.g. Figs. 2 – 5] discloses wherein the logic signal [e.g. VADJ] is a one-bit signal having a first state during steady state condition [e.g. Fig. 3; low before t1] and a second state during transient condition [e.g. Fig. 3; high during t1].
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang in view of Chen and further in view of US Patent No. 8,305,061; (hereinafter Zhang).
Regarding claim 15, Chiang fails to disclose wherein the logic signal is a multi-bit signal.
Zhang teaches wherein the logic signal [e.g. DVe] is a multi-bit signal [e.g. Abstract recites “The digital error amplifier provides a multi-bit digital error voltage signal that is based on the difference between the output voltage and the desired output voltage”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Chiang by wherein the logic signal is a multi-bit signal as taught by Zhang in order of being able to provide multiple states of operation.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Response to Arguments
Applicant's arguments filed 03/09/2026 have been fully considered but they are not persuasive.
Applicant(s) argue(s) with respect to claims 1 and 11:
“Chen does not disclose switches coupled to resistors for selectively connecting or disconnecting resistances within a resistance circuit. Instead, the switches shown in Chen (e.g., S3 and S4) control charging and discharging paths associated with the current sources used to generate the ramp signal. Chen therefore does not disclose activating or deactivating switches that are coupled to resistances in order to adjust the ramp signal. The Examiner's position appears to rely on the assertion that gm1 activates "inherent resistances of the switches." However, the claim requires a resistance circuit comprising a plurality of resistances, and switches coupled to those resistances.”
In response, the claim does not require a resistor, instead the claim requires a plurality of resistances. As it is well known in the art, conductors, switches and voltage-control current source gm2 (I2) have inherent resistances. The signal EAO is configured to activate or de-activate the switch in the voltage-controlled current source gm1 coupled to the plurality of resistances in S3, S4 and gm2 so as to control the ramp RMP. Therefore, the argument is not persuasive and the rejections in view of Chiang and Chen are maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Torres-Rivera whose telephone number is (571)272-5261. The examiner can normally be reached M-F 9:00-5:30 ET.
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838
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