DETAILED ACTION
Claims 1-8, 10-17 and 19-32 are pending in this application.
Claims 20-30 are withdrawn.
Claims 1-8,10-17 and 19-30 are rejected.
Claims 31-32 are objected to.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/16/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 10-11, 13-17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vogelsang et al. (U.S. PGPub 2021/0373811) in view of Hubbard et al. (U.S. PGPub 2020/0183622) in view of Woo et al. (U.S. PGPub 2022/0156204).
Claim 1
Vogelsang (2021/0373811) teaches:
An apparatus, comprising: a memory interface coupled to a first plurality of banks and a second plurality of banks, the memory interface configured to couple the first plurality of banks and the second plurality of banks to a host device through a first sub-channel and a second sub-channel, and the memory interface configured to perform operations comprising: FIG. 1 and P. 0022 command and data interface 115 provides access to either of the two dies 105 by via either of external channels BCh[8,4]; P. 0029 DRAM dies 105A and 105B include DRAM memory cells organized into banks [the banks on die 105A are the first plurality of banks, the banks on die 105B are the second plurality of banks]
communicating first data stored in the first plurality of banks to the host device through the first sub-channel in a first operating mode; FIG. 2B and P. 0029 external memory channels BCh(n) is coupled to DRAM die 105A via internal channel MCh(n); P. 0035 read data DQ from DRAM die 105A via memory channel MCh(n)
communicating second data stored in the second plurality of banks to the host device through the second sub-channel in the first operating mode; FIG. 2A and P. 0029 external memory channels BCh(n+4) is coupled to DRAM die 105B via internal channel MCh(n+4); P. 0036 DRAM die 105B may be accessed via internal memory channel MCh(n+4); P. 0026 in a normal state, muxes 120 are set to connect each of external channels BCh[8:1] to a corresponding one of internal channels MCh[8:1]
receiving a command to enter a second operating mode; and P. 0026 and FIG. 1 mode registers 130 on base die 110 can be loaded responsive to mode-register packets, and multiplexers 120 are set according to the loaded mode value
Vogelsang does not explicitly teach a second operating mode where data in the first plurality of banks and second plurality of banks are transmitted through the first channel.
Hubbard (2020/0183622) teaches:
communicating third data stored in the first plurality of banks to the host device through the first-sub-channel in the second operating mode in response to a third command […] P. 0041 and FIG. 4 all of the sub-pluralities of memory die 430A, 430B (1st plurality of banks), 430C, 430D (2nd plurality of banks) are accessible for data read via the current active memory channels; P. 0043 and FIG. 4 in one-channel mode, memory dies 430A and 430B (1st plurality of banks) are coupled to the external memory channel interface associated with memory channel 0; P. 0010 host system can request data (e.g. 3rd data) to be retrieved from memory via read requests (e.g. 3rd command)
communicating fourth data stored in the second plurality of banks to the host device through the first sub-channel in the second operating mode in response to a fourth command […] P. 0043 and FIG. 4 in one-channel mode, memory dies 430C and 430D (2nd plurality of banks) are coupled to the external memory channel interface associated with memory channel 0; P. 0010 host system can request data (e.g. 4th data) to be retrieved from memory via read requests (e.g. 4th command)
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Vogelsang with the second operating mode where data in the first plurality of banks and second plurality of banks are transmitted through the first channel taught by Hubbard
The motivation being to operate in a low power consumption mode (See Hubbard P. 0031)
The systems of Vogelsang and Hubbard do not explicitly teach the third and fourth commands indicating the first and second plurality of banks, respectively.
Woo (2022/0156204) teaches:
communicating third data stored in the first plurality of banks to the host device […] in response to a third command with a first indication selecting the first plurality of banks; and : P. 0093 in processing of a second read command (RD2), a second set of data bits (DATA2) from a channel A memory bank 874a-875a are output on bus E; P. 0073 and FIG. 7 the bank address [indication] of the command sequence determines which quadrant (e.g. Channel A) of memory cores is accessed
communicating fourth data stored in the second plurality of banks to the host device […] in response to a fourth command with a second indication selecting the second plurality of banks. P. 0092 and FIG. 8 in processing of a first read command (RD1), a first set of data bits (DATA1) are output from a channel B memory bank 874b-875b on bus D; P. 0073 and FIG. 7 the bank address [indication] of the command sequence determines which quadrant (e.g. Channel B) of memory cores is accessed
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Vogelsang and Hubbard with third and fourth commands indicating the first and second plurality of banks, respectively taught by Woo.
The motivation being to operate each channel independently of each other (see Woo P. 0023)
The systems of Vogelsang, Hubbard and Woo are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Vogelsang and Hubbard with Woo to obtain the invention as recited in claims 1-12.
Claim 2
Vogelsang (2021/0373811) teaches:
The apparatus of claim 1, wherein the memory interface comprises: a first multiplexer configured to couple the first sub-channel to the first plurality of banks in the first operating mode; and a second multiplexer configured to couple the second sub-channel to the second plurality of banks in the first operating mode, P. 0023 Interface 115 provides access to the addressable memory on either of the two dies 105 by via either of external channels BCh[8,4] through multiplexers 120; P. 0026 muxes 120 are set to connect each of external channels BCh[8:1] to a corresponding one of internal channels MCh[8:1]
wherein the first multiplexer is further configured to couple the first sub-channel to the first plurality of banks or the second multiplexer in the second operating mode based at least in part on control information received from the first sub-channel, and wherein the second multiplexer is further configured to couple the first multiplexer to the second plurality of banks in the second operating mode. P. 0030 Depending on the settings of each multiplexer 210, external memory channel BCh(n) can communicate command/address signals CA(n) and data signals DQ(n) to either of DRAM dies 105A and 105B via cross-channel connections XC; P. 0036 although not shown, DRAM die 105B may be accessed through memory channel BCh(n); P. 0032 and FIG. 2A each multiplexer 210 receives a two-bit control signal to direct command/address signals CA and write and read data
Claim 3
Vogelsang (2021/0373811) teaches:
The apparatus of claim 2, wherein the memory interface further comprises control circuitry configured to control the first multiplexer and the second multiplexer such that the first multiplexer couples the second plurality of banks to the first sub-channel based on a mode register and the control information. P. 0026 mode registers 130 can be loaded responsive to mode-register packets and the multiplexers 120 set according to the loaded mode value; P. 0026 in a normal state, muxes 120 are set to connect each of external channels BCh[8:1] to a corresponding one of internal channels MCh[8:1], other states are shown in FIGs. 2A-I; P. 0030 Depending on the settings of each multiplexer 210, external memory channel BCh(n) can communicate command/address signals CA(n) and data signals DQ(n) to either of DRAM dies 105A and 105B via cross-channel connections XC; P. 0032 and FIG. 2A each multiplexer 210 receives a two-bit control signal to direct command/address signals CA and write and read data
Claim 4
Vogelsang (2021/0373811) teaches:
The apparatus of claim 3, wherein the control circuitry comprises a mode register configured to store a first value corresponding to the first operating mode or a second value corresponding to the second operating mode. P. 0026 multiplexers 120 are set according to the loaded mode value, mode registers can be initialized to a normal operating state where muxes 120 are set to connect each of external channels BCh[8:1] to a corresponding one of internal channels MCh[8:1], other states are shown in FIGs. 2A-I; P. 0036 and FIG. 2D although not shown, DRAM die 105B may be accessed through memory channel BCh(n)
Claim 5
Vogelsang (2021/0373811) teaches:
The apparatus of claim 4, wherein receiving the command to enter the second operating mode comprises receiving a mode register write command setting the mode register to the second value corresponding to the second operating mode. P. 0027 MRS bits load the mode register to determine the state of multiplexers 120, and are included in command packets
Claim 6
Vogelsang (2021/0373811) teaches:
The apparatus of claim 4, wherein the control circuitry further comprises logic circuitry configured to receive the control information and a stored value from the mode register for controlling the first multiplexer. P. 0026 multiplexers 120 are set according to the loaded mode value, in a normal operation muxes 120 are set to connect each of external channels BCh[8:1] to a corresponding one of internal channels MCh[8:1], other states are shown in FIGs. 2A-I; P. 0036 and FIG. 2D although not shown, DRAM die 105B may be accessed through memory channel BCh(n); P. 0032 and FIG. 2B each multiplexer 210 receives a two-bit control signal to direct command/address signals CA and write and read data
Claim 7
Vogelsang (2021/0373811) teaches:
The apparatus of claim 2, wherein: the first sub-channel comprises a first data bus, […] and a first command and address bus, and the second sub-channel comprises a second data bus, […] and a second command and address bus, FIG. 1 and P. 0030 each external memory channel BCh(n) and BCh(n+4) has a respective command/address signal CA(n) and CA(n+4), and data signal DQ(n) and DQ(n+4)
wherein the control information is received from the first command and address bus. P. 0032 and FIG. 2B each multiplexer 210 receives a two-bit control signal to direct command/address signals CA and write and read data, select signals CS1/CS2n control the multiplexers 210 corresponding to the command/address bus CA(n) of channel BCh(n)
The systems of Vogelsang and Hubbard do not explicitly teach each sub-channel comprising its own clock signal.
Woo (2022/0156204) teaches:
the first sub-channel comprises […] a first clock signal […] and the second sub-channel comprises […] a second clock signal […] P. 0033 each channel A-D 110a-110d may each receive independent clocking signal(s) that drive the operations of that respective channel A-D 110a-110d
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Vogelsang and Hubbard with each sub-channel comprising its own clock signal taught by Woo
The motivation being to operate each channel independently of each other (see Woo P. 0023)
The systems of Vogelsang, Hubbard and Woo are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Vogelsang and Hubbard with Woo to obtain the invention as recited in claim 7.
Claim 8
Hubbard (2020/0183622) teaches:
The apparatus of claim 1, wherein a bandwidth of the first sub-channel is shared by the first plurality of banks and the second plurality of banks in the second operating mode. P. 0039 and FIG. 3 memory channel 0 is shared by memory die 330A and memory die 330C
Claim 10
Woo (2022/0156204) teaches:
The apparatus of claim 9, wherein the bank-specific command comprises at least one of a bank activate command, a bank precharge command, a write command, a read command, or a refresh command. P. 0084 a first activate command (ACT1) includes a first bank address (BA1)
Claim 11
Vogelsang (2021/0373811) teaches:
The apparatus of claim 1, wherein the apparatus comprises a semiconductor die comprising the memory interface, the first plurality of banks, and the second plurality of banks. FIG. 1 and P. 0004 stacked memory device 100 includes interface 115 on a base die 110, and four memory dies 105; P. 0029 DRAM dies 105A and 105B include DRAM memory cells organized into banks [the banks on die 105A are the first plurality of banks, the banks on die 105B are the second plurality of banks]
Claim 13
Vogelsang (2021/0373811) teaches:
A method, comprising: communicating, by a memory module through a memory interface, first data stored in a first plurality of banks to a host device through a first sub-channel in a first operating mode; FIG. 1 and P. 0022 command and data interface 115 provides access to either of the two dies 105 by via either of external channels BCh[8,4]; P. 0029 DRAM dies 105A and 105B include DRAM memory cells organized into banks [the banks on die 105A are the first plurality of banks, the banks on die 105B are the second plurality of banks]; FIG. 2B and P. 0029 external memory channels BCh(n) is coupled to DRAM die 105A via internal channel MCh(n); P. 0035 read data DQ from DRAM die 105A via memory channel MCh(n)
communicating, by the memory module through the memory interface, second data stored in a second plurality of banks to the host device through a second sub-channel in the first operating mode; FIG. 2A and P. 0029 external memory channels BCh(n+4) is coupled to DRAM die 105B via internal channel MCh(n+4); P. 0036 DRAM die 105B may be accessed via internal memory channel MCh(n+4); P. 0026 in a normal state, muxes 120 are set to connect each of external channels BCh[8:1] to a corresponding one of internal channels MCh[8:1]
receiving, by the memory module through the memory interface, a command to enter a second operating mode; and P. 0026 and FIG. 1 mode registers 130 on base die 110 can be loaded responsive to mode-register packets, and multiplexers 120 are set according to the loaded mode value
Vogelsang does not explicitly teach a second operating mode where data in the first plurality of banks and second plurality of banks are transmitted through the first channel.
Hubbard (2020/0183622) teaches:
communicating, by the memory module through the memory interface, third data stored in the first plurality of banks to the host device through the first sub-channel in the second operating mode in response to a third command […] P. 0041 and FIG. 4 all of the sub-pluralities of memory die 430A, 430B (1st plurality of banks), 430C, 430D (2nd plurality of banks) are accessible for data read via the current active memory channels; P. 0043 and FIG. 4 in one-channel mode, memory dies 430A and 430B (1st plurality of banks) are coupled to the external memory channel interface associated with memory channel 0; P. 0010 host system can request data (e.g. 3rd data) to be retrieved from memory via read requests (e.g. 3rd command)
communicating, by the memory module through the memory interface, fourth data stored in the second plurality of banks to the host device through the first sub-channel in the second operating mode in response to a fourth command […] P. 0043 and FIG. 4 in one-channel mode, memory dies 430C and 430D (2nd plurality of banks) are coupled to the external memory channel interface associated with memory channel 0; P. 0010 host system can request data (e.g. 4th data) to be retrieved from memory via read requests (e.g. 4th command)
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Vogelsang with the second operating mode where data in the first plurality of banks and second plurality of banks are transmitted through the first channel taught by Hubbard
The motivation being to operate in a low power consumption mode (See Hubbard P. 0031)
The systems of Vogelsang and Hubbard do not explicitly teach the third and fourth commands indicating the first and second plurality of banks, respectively.
Woo (2022/0156204) teaches:
communicating, by the memory module through the memory interface, third data stored in the first plurality of banks to the host device […] in response to a third command with a first indication selecting the first plurality of banks; and P. 0093 in processing of a second read command (RD2), a second set of data bits (DATA2) from a channel A memory bank 874a-875a are output on bus E; P. 0073 and FIG. 7 the bank address [indication] of the command sequence determines which quadrant (e.g. Channel A) of memory cores is accessed
communicating, by the memory module through the memory interface, fourth data stored in the second plurality of banks to the host device […] in response to a fourth command with a second indication selecting the second plurality of banks. P. 0092 and FIG. 8 in processing of a first read command (RD1), a first set of data bits (DATA1) are output from a channel B memory bank 874b-875b on bus D; P. 0073 and FIG. 7 the bank address [indication] of the command sequence determines which quadrant (e.g. Channel B) of memory cores is accessed
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Vogelsang and Hubbard with third and fourth commands indicating the first and second plurality of banks, respectively taught by Woo.
The motivation being to operate each channel independently of each other (see Woo P. 0023)
The systems of Vogelsang, Hubbard and Woo are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Vogelsang and Hubbard with Woo to obtain the invention as recited in claims 13-19.
Claim 14
Vogelsang (2021/0373811) teaches:
The method of claim 13, wherein receiving the command to enter the second operating mode comprises receiving a mode register write command setting a mode register of the memory interface to a value corresponding to the second operating mode. P. 0027 MRS bits load the mode register to determine the state of multiplexers 120, and are included in command packets
Claim 15
Vogelsang (2021/0373811) teaches:
The method of claim 13, wherein: communicating the first data comprises communicating the first data through a first multiplexer configured to couple the first sub-channel to the first plurality of banks in the first operating mode; FIG. 2B and P. 0029 external memory channels BCh(n) is coupled to DRAM die 105A via internal channel MCh(n); P. 0035 read data DQ from DRAM die 105A via memory channel MCh(n)
communicating the second data comprises communicating the second data through a second multiplexer configured to couple the second sub-channel to the second plurality of banks in the first operating mode; […] FIG. 2A and P. 0029 external memory channels BCh(n+4) is coupled to DRAM die 105B via internal channel MCh(n+4); P. 0036 DRAM die 105B may be accessed via internal memory channel MCh(n+4); P. 0026 in a normal state, muxes 120 are set to connect each of external channels BCh[8:1] to a corresponding one of internal channels MCh[8:1]
[…] communicating the fourth data comprises communicating the fourth data through the second multiplexer. P. 0023 cross-channel connections XC allow external command, address, and data signals on either of external channels BCh[8,4] to be communicated with either of internal channels MCh[8,4]
Hubbard (2020/0183622) teaches:
[…] communicating the third data and the fourth data in the second operating mode comprises communicating the third data through the first multiplexer in the second operating mode; and […] P. 0028 and FIG. 3 the multiplexer circuit couples the second set of memory die to the first external memory channel interface, both the first set of memory die and the second set of memory die are accessible via the first external memory channel interface; P. 0039 in two-channel mode, multiplexer 320 couples memory die 330C to the interface associated with memory channel 0, which is shared with memory die 330A
Claim 16
Vogelsang (2021/0373811) teaches:
The method of claim 15, further comprising: receiving control information from the first sub-channel; and controlling the first multiplexer and the second multiplexer by a mode register of the memory interface such that the first multiplexer couples the second plurality of banks to the first sub-channel based on the mode register and the control information. P. 0023 cross-channel connections XC allow external command, address, and data signals on either of external channels BCh[8,4] to be communicated with either of internal channels MCh[8,4]; P. 0030 Depending on the settings of each multiplexer 210, external memory channel BCh(n) can communicate command/address signals CA(n) and data signals DQ(n) to either of DRAM dies 105A and 105B via cross-channel connections XC; P. 0032 and FIG. 2A each multiplexer 210 receives a two-bit control signal to direct command/address signals CA and write and read data
Claim 17
Hubbard (2020/0183622) teaches:
The method of claim 13, wherein a bandwidth of the first sub-channel is shared by the first plurality of banks and the second plurality of banks in the second operating mode. P. 0039 and FIG. 3 memory channel 0 is shared by memory die 330A and memory die 330C in 2-channel mode
Claim 19
Woo (2022/0156204) teaches:
The method of claim 18, wherein the bank-specific command comprises at least one of a bank activate command, a bank precharge command, a write command, a read command, or a refresh command. P. 0084 a first activate command (ACT1) includes a first bank address (BA1)
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vogelsang et al. (U.S. PGPub 2021/0373811) in view of Hubbard et al. (U.S. PGPub 2020/0183622) in view of Woo et al. (U.S. PGPub 2022/0156204) in view of Lo et al. (U.S. PGPub 2015/0089112)
Claim 12
The systems of Vogelsang, Hubbard and Woo do not explicitly teach a LPDDR interface (although Vogelsang teaches channels operating at DDR in P. 0040, and Hubbard teaches a low-power consumption mode in P. 0018).
Lo (2015/0089112) teaches:
The apparatus of claim 11, wherein the memory interface is configured to communicate with the host device according to a low power double data rate (LPDDR) interface. P. 0027 DRAM memory system 104 comprises a LPDDR2 memory device and the memory bus 106 comprises a 32-bit bus
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Vogelsang, Hubbard and Woo with each sub-channel comprising its own clock signal taught by Lo
The motivation being it is a well-known DRAM configuration.
The systems of Vogelsang, Hubbard, Woo and Lo are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Vogelsang, Hubbard and Woo with Lo to obtain the invention as recited in claim 12.
Allowable Subject Matter
Claims 31-32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 31 recites the limitation “wherein communicating first data stored in the first plurality of banks to the host device through the first sub-channel in the first operating mode is in response to a first command with the first indication or the second indication, where communicating second data stored in the second plurality of banks to the host device through the second sub-channel in the first operating mode is in response to a second command with the first indication or the second indication, and wherein the first or second indication is ignored in the first operating mode”
Said limitation is taught by the specification of the instant application as originally filed at least at [P. 0049 and 0055]. Said limitations, in combination with the other recited limitations of claim 31, are not taught or suggested by the prior art of record.
The closest prior art of record includes: Vogelsang (2021/0373811), Hubbard (2020/0183622), Woo (2022/0156204), and Howe (2019/0156871) which teaches sending commands with corresponding indications on chip select terminals, which indicate which channel is not targeted by the read command and should enter on-die termination mode. None of the references teach an apparatus in a first operating mode ignoring first and second indicators in a command and sending data stored in first or second plurality of banks to the host through its respective sub-channel, and while when in a second operating mode: receiving a command with the first indicator and sending data stored in the first plurality of banks through the first sub-channel, and receiving a command with the second indicator and sending data stored in the second plurality of banks through the first sub-channel.
Claim 32 contains similar limitations to claim 31, and is considered allowable for at least the same reasons as claim 31.
Response to Arguments
Applicant's arguments filed 1/6/2026 have been fully considered but they are not persuasive.
The applicant argues “The Official Action cites Woo at para. [0084] teaching “first activate command (ACT1) includes a first bank address (BA1), which determines which memory bank(s) an access is directed to.” As the text of Woo shows, BA1 is a bank address, while “indication” by the present application is to instruct memory to couple a specific group of banks to the first sub-channel”
The examiner respectfully notes the claim is open ended (“the memory interface configured to perform operations comprising”). The claim does not require the indication to be the sole mechanism that determines how a plurality of banks is selected for communicating data. Even the claim states the indication in combination with the second operating mode determines whether data in either of the plurality of banks is communicated through the first sub-channel. The examiner also notes that the indication is not claimed to cause the apparatus to enter the second operating mode, merely that it selects a first or second plurality of banks. So while Woo may teach the routing of data to channel A or channel B to be based on a mode setting and the MSB of the bank address in the request, it still reads on the claim in its current form.
The applicant also argues on page 13 that the MSB of the row address indicates whether to memory cores will be the shorter or longer access latency path, and does not select either of the memory cores 714a/714b. Woo P. 0073 describes access latencies for channel A 710a as being shorter when access is directed to memory core 714a, and longer when directed to memory core 714b. Functionally, the MSB determines whether the access on channel A 710a is directed to memory core 714a or 714b. The fact that the MSB has an additional purpose of indicating whether the shorter or longer access latency path is used for a memory access does not preclude it from also selecting a memory core 714a/714b. Looking at the applicant’s specification P. 0049 and FIG. 2, the indication of a plurality of banks (e.g. 175A-1) attached to a Read command allows circuitry corresponding to the plurality of banks (e.g. multiplexer 262A-1) to receive control inputs via shared circuitry (mode register 264A). This is analogous to the MSB of Woo.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhao et al. (U.S. PGPub 2021/0335393) a memory package connected to a host chip through two channels, each channel connected to a half of each of the memory chips.
Schaefer et al. (U.S. PGPub 2024/0303158) teaches two MUXes, the first output of one MUX being connected to the input of the other MUX, and the second output of another MUX bypassing the other MUX
Mcilvain et al. (U.S. PGPub 2019/0033952) teaches reducing a number of active channels in a multi-channel stacked DRAM
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHANIE WU whose telephone number is (571)272-0257. The examiner can normally be reached 1pm to 6pm, and 10pm to 1am Eastern time (10am to 3pm, and 7pm to 10pm Pacific time).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio Del Mar Perez-Velez can be reached on (571) 270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEPHANIE WU/Primary Examiner, Art Unit 2133
Prosecution Insights