DETAILED ACTION
Response to Amendment
The amendment filed on 7/29/2026 under 37 CFR 1.312 has been entered. Claims 1-15 remain pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-7, 10-12, 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh (US 20210305802 A1) in view of Eklund (US 4874714 A)
Regarding claim 1, Yeh discloses (Fig. 3A) An integrated circuit device comprising:
a backside power distribution network structure (BSPDNS) (conductive structures 340, 344, 346);
a logic device region (Clamp 310) and a passive device region (D1 (302) on the BSPDNS;
a backside insulating layer (321) comprising a first portion extending between the BSPDNS and the logic device region and a second portion extending between the BSPDNS and the passive device region,
the passive device region comprising a semiconductor layer (well 322) that is in the backside insulating layer; and
a dam (STI 328b, 328c) separating the first portion of the backside insulating layer from the semiconductor layer of the passive device region.
wherein the semiconductor layer comprises a first semiconductor material, (heavily doped n-region or p-region, ¶ [0074]).
Yeh is silent regarding the dam comprises a second semiconductor material.
Eklund discloses (Fig. 6, col. 3, lines 30-37) an isolation well region (28) between the two n-wells (22, 24).
Yeh discloses the STI region 328c between two n-type regions 310a (¶ [0094]) and 302c (¶ [0076]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the STI region of Yeh with the isolation well region of Eklund for a diversity of application.
Regarding claim 2, Yeh in view of Eklund discloses (Fig. 3A) the integrated circuit device of Claim 1. Yeh further discloses comprising a first backside contact (344) in the backside insulating layer, wherein the first backside contact is electrically connected to a source/drain region (310a, [0121]) of the logic device region.
Regarding claim 4, Yeh in view of Eklund discloses the integrated circuit device of Claim 2. Yeh further discloses comprising a second backside contact (340) in the backside insulating layer, wherein the semiconductor layer comprises a region including impurities (324), and wherein the second backside contact is electrically connected to the region including the impurities ([0125]).
Regarding claim 5, Yeh in view of Eklund discloses the integrated circuit device of Claim 4. Yeh further discloses wherein a lower surface of the first backside contact is coplanar with a lower surface of the second backside contact (Fig. 3A).
Regarding claim 6, Yeh in view of Eklund discloses the integrated circuit device of Claim 4, Yeh further discloses wherein a thickness of the first backside contact is greater than a thickness of the second backside contact (Fig. 3A).
Regarding claim 7, Yeh in view of Eklund discloses the integrated circuit device of Claim 1, Yeh further discloses wherein a portion of the dam is in the backside insulating layer, and wherein a thickness of the dam is thinner than a thickness of the first portion of the backside insulating layer (Fig. 3A).
Regarding claim 10, Yeh in view of Eklund discloses the integrated circuit device of Claim 1. The modified device of Yeh-Eklund would result in the second semiconductor material of the dam comprising a material (p-type) different from the first semiconductor material of the semiconductor layer (n-type).
Regarding claim 11, Yeh discloses (Fig. 3A) An integrated circuit device comprising:
a backside power distribution network structure (BSPDNS) (conductive structure 340, 344, 346);
a first device region (clamp 310) and a second device region (D1 (302)) on the BSPDNS;
a backside insulating layer (321) extending between the BSPDNS and the first device region and between the BSPDNS and the second device region,
the second device region comprising a semiconductor layer (well 322) that is in the backside insulating layer; and
a dam (STI 328c) that is at least partially in the backside insulating layer, wherein the dam extends between the backside insulating layer and a side surface of the semiconductor layer (Fig. 3A),
wherein the semiconductor layer comprises a first semiconductor material (heavily doped n-region or p-region, ¶ [0074]). Yeh is silent regarding the dam comprises a second semiconductor material.
Eklund discloses (Fig. 6, col. 3, lines 30-37) an isolation well region (28) between the two n-wells (22, 24).
Yeh discloses the STI region 328c between two n-type regions 310a (¶ [0094]) and 302c (¶ [0076]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the STI region of Yeh with the isolation well region of Eklund for a diversity of application.
Regarding claim 12, Yeh in view of Eklund discloses the integrated circuit device of Claim 11. Yeh further discloses (Fig. 3A) wherein a thickness of a portion of the backside insulating layer, which extends between the BSPDNS and the first device region (distance from lower end of 310 to lower end of 344), is thicker than a thickness of a portion of the backside insulating layer, which extends between the BSPDNS and the second device region (distance from lower end of 322 to lower end of 340).
Regarding claim 14, Yeh in view of Eklund discloses the integrated circuit device of Claim 11. Yeh further discloses (Fig. 3A) comprising:
a first backside contact (344) electrically connected to the BSPDNS and a source/drain region of the first device region; and
a second backside contact (340) electrically connected to the BSPDNS and the semiconductor layer.
Regarding claim 15, Yeh in view of Eklund discloses the integrated circuit device of Claim 14. Yeh further discloses (Fig. 3A) wherein a lower surface (lower end of 344) of the first backside contact is coplanar with a lower surface (lower end of 340) of the second backside contact, and
wherein a distance between an upper surface (lower end of contacts) of the BSPDNS and a lower surface of the semiconductor layer is longer than or equal to a distance between the upper surface of the BSPDNS and a lower surface of the dam.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh (US 20210305802 A1) in view of Eklund (US 4874714 A) and Orr (US 20220415877 A1)
Regarding claim 8, Yeh in view of Eklund discloses the device of claim 7. Yeh further discloses (Fig. 3A) the semiconductor layer extends between the diode 302 with cathode and anode terminals. Yeh does not disclose the diode having source/drain layer.
Orr discloses (Fig. 1A) an analogous art of diode 101 facilitating ESD protection to transistors formed above the diode 101 (¶ [0068]). Orr discloses in ¶ [0038] disclosing “integration schemes that can co-fabricate transistors alongside an ESD protection device by utilizing fin structures as source and drain for respective transistors and doped fin structures as terminals of diodes can provide significant process advantages and offer cost benefits. Cost savings can stem from a lack of a need to implement separate masks for forming terminals of the diode by utilizing fin patterning to simultaneously form fins and terminals for transistors and one or more diodes, respectively, for example.”
Thus, one of ordinary skill in the art before the filling date of the invention would have substitute the diode of Yeh for the Finfet diode of Orr for cost saving.
The modified diode of Yeh by Orr would result for the semiconductor layer being between the source/drain layer and the second portion of the insulating layer.
Claim(s) 3, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh (US 20210305802 A1) in view of Eklund (US 4874714 A), Orr (US 20220415877 A1) and Wang (US 20210391320 A1)
Regarding claim 3, Yeh in view of Eklund discloses the integrated circuit device of Claim 2. Yeh further discloses (Fig. 3A) wherein the dam is between the first portion of the backside insulating layer and the semiconductor layer in a direction parallel to an upper surface of the BSPDNS.
Yeh is silent regarding an upper surface of the dam is coplanar with an upper surface of the first backside contact.
Yeh discloses the diode formed in the backside insulating layer to be connected to a diode with cathode and anode. Orr discloses (Fig. 1A and ¶ [0068]) such a diode can be formed by a FinFet diode where source/drain of the transistors are utilized for diode terminals for cost saving. Thus, one of ordinary skills in the art before the filling date of the invention would have substituted the diode of Yeh for the Finfet diode of Orr for cost saving.
The modification of the Yeh diode by Orr would result for the circuit and diode regions of the device being under multiple fins of transistors. Yeh’s device modified by Orr would result for the STI trench being realized by using one of the trenches between the fins as revealed by Wang below.
Wang discloses (Fig. 10A, ¶ [0038]) forming the bottom source/drain layer (252) by extending downwardly a source trench (246) between fins (232) to reserve a space for backside source/drain contact. Thus, one of ordinary skill in the art before the time of the invention would have realized the source/drain trench extension for backside contact can be used to separate the circuit region and the diode region. The STI trench in Yeh device can be realized by the existing source/drain trench extension for cost saving. The modification to the STI trench of Yeh would result in the trench upper surface being below the fins, in other words, co-planar with the upper surface of the fist backside contact.
Regarding claim 13, Yeh in view of Eklund discloses the integrated circuit device of Claim 11. Yeh is silent regarding the dam has a round lower surface. Similarly presented in claim 3, the dam (trench realized from the source/drain trench downward extension as disclosed by Wang) has a round lower surface.
Response to Arguments
Applicant’s arguments have been considered but are moot in view of new grounds of rejection.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hutter (US 5614755 A0) discloses isolation region (p-type 163) between two n-wells.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T HOANG whose telephone number is (571)272-5622. The examiner can normally be reached M-F 8:00 - 5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DTH/ Examiner, Art Unit 2898
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898
