DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figures 9 – 12 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated (see para. [0059] of the specification). (See also MPEP § 608.02(g).)
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign mentioned in the description: “1071” in paragraph [0061] of the specification. (It is believed that this was intended to be “1701”.)
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For example, the title should at least generally refer to the configuration of the “lead” as this is a feature pertinent to all pending claims.
The disclosure is objected to because of the following minor informality: The first sentence of paragraph [0054] should be rewritten in a more understandable manner. As best as the examiner can understand, the subject of this sentence is “a rising portion 712”, and the predicate of this sentence is “is displaced in a direction….” Between the subject and the predicate are multiple descriptive clauses regarding the subject, which makes the sentence difficult to understand. It is suggested that the sentence be re-written as two sentences, with the first sentence including only the subject and its descriptive clauses, and the second sentence including only the subject and the predicate. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 8 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 8 recites the limitation “wherein a distance from the first side surface of the first bonding portion to the insulating layer is substantially the same as a distance from at least one of side surfaces of the first bonding portion including the second side surface to the insulating layer.” It is unclear whether “at least one of side surfaces of the first bonding portion including the second side surface” refers to the second side surface, either the first or second side surfaces, or some other side surface (e.g., a lateral side surface). For purposes of examination herein, “at least one of side surfaces of the first bonding portion including the second side surface” will be interpreted as either the first side surface, the second side surface, or one of the two lateral side surfaces. (See MPEP 2173.06(II).)
Claim Rejections - 35 USC § 102
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
PNG
media_image1.png
285
384
media_image1.png
Greyscale
Claims 1, 4, and 9 – 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Asai, Tatsuhiko, US 2018/0076149 A1 (hereinafter “Asai”; cited in IDS). FIGS. 1 and 3A of Asai are reproduced herein for reference.
Regarding claim 1, Asai discloses a semiconductor module (see FIG. 1 and paras. [0029] – [0030], “power semiconductor module”), comprising:
a semiconductor element (see FIG. 1 and paras. [0030] – [0031], power semiconductor chip 1);
a circuit board on which the semiconductor element is mounted (see FIG. 1 and paras. [0030] – [0032], insulating substrate 2 and electrode pattern 4 formed thereover);
a lead bonded to an electrode on an upper surface of the semiconductor element with a bonding material (see id., lead frame interconnection 6, “the lead frame interconnection 6 is bonded to the upper surface (surface on side opposite a side adjacent to the bonding member 3b) of the power semiconductor chip 1 by the bonding member 3a of solder, etc.”); and
PNG
media_image2.png
198
351
media_image2.png
Greyscale
a sealing material that seals the semiconductor element and the lead (see FIG. 1 and paras. [0030] and [0033], sealing resin 8), wherein
the lead includes a first bonding portion having an upper surface and a lower surface that is opposite to the upper surface and is bonded to the electrode (see FIGS. 1 and 3A, and paras. [0032] and [0034] – [0036], first bonding portion 6a), and a wiring portion connected to the first bonding portion (see FIG. 3A and paras. [0034] – [0036]), interconnect portion 6c), the first bonding portion having a first side surface and a second side surface that face each other between the upper surface and the lower surface (referring to FIG. 3B and para. [0036], the first side surface is the left side of first bonding portion 6a and the second side surface is the right side of the first bonding portion 6a), the wiring portion having a bent portion that is connected to the first bonding portion at a side of the first bonding portion at which the first side surface is located (see FIG. 3A and para. [0034], raised portion 6d being the “bent portion” as illustrated, and noting by reference to FIG. 3B that the “bent portion” is clearly at the left half (“side”) of the first bonding portion 6a, i.e., “connected to the first bonding portion at a side of the first bonding portion at which the first side surface is located”), and
the bent portion is bent at a border between the first bonding portion and the bent portion (i.e., as seen in FIG. 3A, raised portion 6d begins bending substantially at the point where portions 6a and 6d meet, “a border”) in a direction away from the lower surface of the first bonding portion (as illustrated in FIG. 3A), the border being located between the first side surface (referring again to FIG. 3B, the left side of bonding portion 6a) and the second side surface of the first bonding portion (FIG. 3B, the right side of the bonding portion 6a) in a plan view of the lead (as shown in FIG. 3B).
PNG
media_image3.png
203
308
media_image3.png
Greyscale
[AltContent: connector][AltContent: connector][AltContent: textbox (Non-Connection)][AltContent: textbox (Non-Connection)][AltContent: textbox (Connection)]Regarding claim 4, Asai is relied on for the semiconductor module accordingly to claim 1 as above, and further discloses wherein the first side surface of the first bonding portion (referring to FIG. 3B, the left side of bonding portion (6a) has a connection section and two non-connection sections that sandwich the connection section, the connection section being connected to the wiring portion (6c), the non-connection sections being not connected to the wiring portion (see annotated FIG. 3B, above right).
Regarding claim 9, Asai discloses the semiconductor module according to claim 1 as above, and further discloses wherein the circuit board further having a conductor pattern thereon (see FIGS. 1 and 2A, and paras. [0031] and [0034] – [0035], electrode pattern 4 (right side in FIG. 1), and the lead includes a second bonding portion bonded to the conductor pattern (see id., second bonding portion 6b), and being connected to the wiring portion (6c) at a side of the wiring portion opposite to a side of the wiring portion where the first bonding portion (6a) is connected (as illustrated in FIG. 1).
Regarding claim 10, Asai discloses the semiconductor module according to claim 1 as above, and further discloses a semiconductor device that includes a cooler (radiator fin) disposed on a surface of the circuit board (4) at a side of the circuit board that is opposite to a side where the semiconductor element (1) is mounted (see FIG. 1 and para. [0031], “[o]n the rear surface of the electrode pattern 4, the metal substrate 5 having a radiator fin (not depicted) is bonded by the bonding member 3c of solder, etc.”).
Regarding claim 11, Asai discloses the semiconductor module according to claim 1 as above, and further discloses its use in a vehicle (see paras. [0003] and [0054], “automotive inverters”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Asai as applied to claim 1 above, and further in view of Kato, Ryoichi, et al., US 2018/0166549 A1 (hereinafter “Kato”; cited in IDS).
Regarding claim 2, Asai discloses the semiconductor module accordingly to claim 1 as above, but does not explicitly disclose further comprising an insulating layer extending along an outer periphery of the electrode on the upper surface of the semiconductor element (1), wherein the bonding material (3a), the insulating layer and the sealing material (8) are connected to one another at the same point.
In a closely related art, Kato discloses semiconductor device 100 of the present example includes a cooling portion 10, a case 12, a solder portion 14, a metal plate 26, an insulating substrate 16, a circuit portion 18, a circuit portion 20, sealing resin 22, a solder portion 24, a solder portion 25, a semiconductor element 30, a metal connecting plate 60, and a solder portion 80 (see FIGS. 1 – 2 and para. [0037]). Kato further discloses a guard ring 34 provided along the periphery of an upper-surface electrode 82 (see FIGS. 4 and 8, and paras. [0052], [0060] – [0063], and [0087]). The guard ring 34 may include an insulating material, such as polyimide (see para. [0087]), wherein the polyimide guard ring 34, solder portion 80, and sealing resin 22 are connected to one another at the same point (see FIG. 8).
It is prima facie obvious to combine prior art elements according to known methods to yield predictable results. (See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 415 – 21 (2007); MPEP 2143(I)(A).) Both Asai and Kato have very similar designs and may be used for the same purposes, as discussed above. Kato includes the polyimide guard ring 34 for purposes of insulating around the upper surface electrode 82 of the semiconductor element 30. It would therefore have been readily predictable that placing such a guard ring about the semiconductor element 1 of Asai would provide a similar configuration and effect. Accordingly, it would have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application to have combined the guard ring of Kato with the semiconductor element upper surface of Asai in the same / similar manner as the guard ring is provided in Asai.
Regarding claim 8, Asai discloses the semiconductor module accordingly to claim 1 as above, but does not explicitly disclose further comprising an insulating layer extending around the electrode on the upper surface of the semiconductor element (1), wherein a distance from the first side surface of the first bonding portion (referring to FIG. 3B and para. [0036], the first side surface is the left side of first bonding portion 6a) to the insulating layer is substantially the same as a distance from at least one of side surfaces of the first bonding portion including the second side surface to the insulating layer. (As best as this claim limitation can be understood in view of the rejection of claim 8 pursuant to 35 USC § 112(b), above, this limitation could be understood as equating the exact same distance, i.e., “at least one of side surfaces of the first bonding portion including the second side surface” could be understood as the first side surface; as such, the claim equates the distance therefrom to the insulating layer with itself, i.e., “substantially the same”).
Also, in a closely related art, as noted above in connection with claim 2, Kato discloses semiconductor device 100 of the present example includes a cooling portion 10, a case 12, a solder portion 14, a metal plate 26, an insulating substrate 16, a circuit portion 18, a circuit portion 20, sealing resin 22, a solder portion 24, a solder portion 25, a semiconductor element 30, a metal connecting plate 60, and a solder portion 80 (see FIGS. 1 – 2 and para. [0037]). Kato further discloses a guard ring 34 provided along the periphery of an upper-surface electrode 82 (see FIGS. 4 and 8, and paras. [0052], [0060] – [0063], and [0087]). The guard ring 34 may include an insulating material, such as polyimide (see para. [0087]), wherein the polyimide guard ring 34, solder portion 80, and sealing resin 22 are connected to one another at the same point (see FIG. 8).
Again, it is prima facie obvious to combine prior art elements according to known methods to yield predictable results. (See KSR v. Teleflex, supra; MPEP 2143(I)(A).) Both Asai and Kato have very similar designs and may be used for the same purposes, as discussed above. Kato includes the polyimide guard ring 34 for purposes of insulating around the upper surface electrode 82 of the semiconductor element 30. It would therefore have been readily predictable that placing such a guard ring about the semiconductor element 1 of Asai would provide a similar configuration and effect. Accordingly, it would have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application to have combined the guard ring of Kato with the semiconductor element upper surface of Asai in the same / similar manner as the guard ring is provided in Asai. This, in combination with the interpretation of the claimed distances being the same, all limitations of claim 8 would have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Asai.
Regarding claim 3, Asai discloses the semiconductor module according to claim 1 as above, but does not explicitly disclose wherein a distance from the first side surface (referring to FIG. 3B, left side of first bonding portion 6a) to the border (referring to FIG. 3A, the point where portions 6a and 6d meet) on the lower surface of the first bonding portion (6a) is greater than a thickness of the first bonding portion. While comparing FIG. 1 to FIG. 3A does appear to imply this relationship, it is duly noted from MPEP 2125(II) that the drawings may not be to scale, and thus Asai does not explicitly provide disclosure for the further limitation recited in claim 1.
MPEP 2144.04(IV)(A) does, however, note that where the only difference between the prior art (Asai) and the claims is a recitation of relative dimensions of the claimed device, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device. Paragraphs [0041] – [0043] of Asai do note several patently-relevant width dimensions, but no emphasis is placed on the specific distance / thickness relationship as recited in claim 3, and thus a person having ordinary skill in the art, based on the disclosure in Asai, would have any reason to believe that any variations in this distance / thickness relationship would cause any difference in performance. Moreover, as a matter of routine optimization (see MPEP 2144.05(II)), it would be within the level of skill of a person having ordinary skill in the art to select dimensions to suit a particular implementation, as is commonly done in the semiconductor arts. Accordingly, it would have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application to have selected dimensions within the scope of claim 3.
Allowable Subject Matter
Claims 5 – 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims (as to claim 5, claims 1 is the base claim and claim 4 is intervening; as to claims 6 and 7, claim 1 is the base claim and claims 4 and 5 are intervening).
The following is a statement of reasons for the indication of allowable subject matter: Claim 5 recites that the first bonding portion of the lead has two cuts respectively formed from the first side surface toward the second side surface of the first bonding portion between the connection section and respective ones of the two non-connection sections. Claims 6 and 7 recite specific configurations of the two cuts. No prior art of record includes any form of cuts as claimed in the first bonding portion, and thus claims 5 – 7 would appear at present to recite allowable subject matter if re-written in independent form.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Yamada, Takafumi, et al., US 2020/0294953 A1, disclosing semiconductor module is provided, including: a semiconductor chip having an upper surface electrode and a lower surface electrode opposite to the upper surface electrode; a metal wiring plate electrically connected to the upper surface electrode of the semiconductor chip; and a sheet-like low elastic sheet provided on the metal wiring plate, the low elastic sheet having elastic modulus lower than that of the metal wiring plate (see FIGS. 1A – 1B and paras. [0050] – [0071]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ryan Fortin whose telephone number is 703-756-5649. The examiner can normally be reached on Monday – Friday from 8:30 AM to 12:30 PM and from 2:30 PM to 6:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo, can be reached at telephone number 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Center system. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center to authorized users only. Should you have questions about access to the Patent Center system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via telephone and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated-interview-request-air-form.
/R.T.F./
Examiner, Art Unit 2897
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897