Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is a responsive to the application filed on 08/24/2023.
Claims 1-20 are pending.
Claims 1-20 are rejected.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “likely” in claims 1 and 19-20 is a relative term which renders the claim indefinite. The term “likely” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
The dependent claims 2-18 are also subsequently rejected due to their dependency.
Claims 1, 9-10, 12, and 19-20 recite analogous issues stating “would be determined”, “detected” or “predicted”, but it is unclear if the action is performed given the conditions. Applicant can optionally overcome these rejections by amending the claims to state “is detected” or “predicted”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sato (“A SIMULATION STUDY OF COMBINING LOAD VALUE AND ADDRESS PREDICTORS”, 1999), in view of Zouzias et al (“Identifying and Exploiting Sparse Branch Correlations for Optimizing Branch Prediction”, 2022) hereinafter Zouzias.
Regarding claims 1 and 19-20, Sato teaches Prediction circuitry to generate a prediction associated with a prediction input address for controlling a speculative action by a processor; a non-transitory computer-readable medium to store computer-readable code for fabrication of prediction circuitry to generate a prediction associated with a prediction input address for controlling a speculative action by a processor, the prediction circuitry comprising; a method for generating a prediction associated with a prediction input address for controlling a speculative action by a processor (sections 3.2, 3.5, and 4.1 teach determining the processor’s and memory’s performances when executing cooperative predictor functions of load and address predicting), the method comprising:
combiner circuitry to generate a combined prediction associated with a given address based on combining respective sets of prediction information generated by a plurality of predictors comprising at least a first predictor and a second predictor (section 3.5 teaches measuring processor (combiner circuitry) performance when executing a “cooperative predictor [that] is a load value (first) predictor supported by a load address (second) predictor [13]. Whenever a load instruction is encountered both the value and the address predictors initiate (generate) prediction (combined prediction). The predicted address (associated with a given address) is used only when the value predictor is unable to predict a load value”), wherein the combiner circuitry is configured to generate the combined prediction using combiner prediction state information obtained in a lookup of at least one combiner table structure based on the given address and the respective sets of prediction information (sections 3.2 and 3.5 teach the processor’s load address predictor using a “reference prediction table (RPT) (lookup…table structure)… An entry of the RPT is indexed by the instruction (given) address and holds the previous data address (prev addr), the stride value (stride), and the state information (state) (combiner prediction state information). The stride is the difference between last two data addresses generated by an instruction. The state information encodes the past history and indicates whether next prefetching is initiated”); and
predictor control circuitry to: determine, based on a lookup of the prediction input address in a combiner hint data structure, whether a second predictor lookup suppression condition is satisfied for the prediction input address indicating that the combined prediction that would be determined by the combiner circuitry for the prediction input address is likely to be derivable from a prediction outcome predicted by the first predictor for the prediction input address without looking up the second predictor (section 3.5 teaches measuring processor (combiner circuitry) performance when executing “[t]he comparison of the predicted address with the actual one can be done in parallel with the address calculation [4], and thus the data fetching using the actual address is suppressed when two addresses match (suppression condition is satisfied…indicating that the combined prediction…is likely to be derivable from a prediction outcome predicted by the first predictor)”); and
in response to determining that the second predictor lookup suppression condition is satisfied:
suppress a lookup of the second predictor based on the prediction input address (section 3.5 teaches measuring processor (combiner circuitry) performance when executing “[t]he comparison of the predicted address (based on the prediction input address) with the actual one can be done in parallel with the address calculation [4], and thus the data fetching using the actual address is suppressed when two addresses match”); and
generate the prediction associated with the prediction input address based on the prediction outcome predicted by the first predictor for the prediction input address (sections 3.5 teach outputting a load value prediction based on the address results).
Kurutach at least implies combiner circuitry to generate a combined prediction associated with a given address based on combining respective sets of prediction information generated by a plurality of predictors comprising at least a first predictor and a second predictor (see mappings above); however, Zouzias teaches combiner circuitry to generate a combined prediction associated with a given address based on combining respective sets of prediction information generated by a plurality of predictors comprising at least a first predictor and a second predictor (Zouzias, sections 2-3 and 5.1-5.2 teach “we employ the latest TAGE-SC-L models [28] for our study (first predictor and a second predictor)” in tandem (combined prediction) on a “circuit”, wherein “TAGE predictors are based on the PPM data compression scheme [5]. They employ a plurality of tables that are indexed using overlapping history slices of increasing lengths, hashed (XOR-ed) with the branch address. Table entries contain (partially) tagged saturating counters that model the prediction”).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to implement Zouzias’ teachings of different tandem TAGE predictors employing tagged tables for model predictions into Sato‘s teaching of load value and load address predictors utilizing tables and suppression functions in order to “improve prediction accuracy” while staying in “power limitations” (Zouzias, sections 1-3 and 5.1-5.2).
Regarding claim 2, the combination of Sato and Zouzias teach all the claim limitations of claim 1 above; and further teach comprising a combiner cache structure comprising a plurality of combiner cache entries, where a given combiner cache entry is associated with a corresponding address indication and is indicative of a plurality of items of combined prediction information determined by the combiner circuitry for an address corresponding to the address indication and a plurality of different combinations of possible values for the respective sets of prediction information (Sato, sections 3.2 and 3.5 teach “The RPT, which has a similar structure with the instruction cache (combiner cache structure), is…[applied]…to predict the data address (entry) because of its simplicity.” The processor’s load address predictor of the cooperative predictor uses the “reference prediction table (RPT) (lookup…table structure)…An entry of the RPT is indexed by the instruction (given) address and holds the previous data address (prev addr), the stride value (stride), and the state information (state) (different combinations of possible values for the respective sets of prediction information). The stride is the difference between last two data addresses generated by an instruction. The state information encodes the past history and indicates whether next prefetching is initiated”).
Regarding claim 3, the combination of Sato and Zouzias teach all the claim limitations of claim 2 above; and further teach in which, when the second predictor lookup suppression condition is not satisfied, the predictor control circuitry is configured to select the prediction associated with the prediction input address based on a selected item of combined prediction information obtained from a selected combiner cache entry for which the address indication corresponds to the prediction input address (Sato, sections 3.2 and 3.5 teach the load address predictor accounting “The previous data address and the stride value are supplied from an entry of the RPT indexed by the program counter (PC), if the tag field is matched. The predicted address is the sum of prev_addr and stride. The state information is also provided. If the state is ‘predict’ or ‘weakly predict’, the predicted address is valid. Otherwise, the prediction is not initiated (not satisfied)”, and “The comparison of the predicted address with the actual one can be done in parallel with the address calculation [4], and thus the data fetching using the actual address is suppressed when two addresses match”. If they do no match (not satisfied), “Otherwise, I1 fetches data again using the actual address (select the prediction associated with the prediction input address based on a selected item of combined prediction information) and I2 is invalidated and reissued as shown in Fig. 9”),
the selected item of combined prediction information comprising the item of combined prediction information which corresponds to values of the respective sets of prediction information determined by the plurality of predictors corresponding to the prediction input address (Sato, sections 3.2 and 3.5 teach the load address predictor accounting “The previous data address and the stride value are supplied from an entry of the RPT indexed by the program counter (PC), if the tag field is matched. The predicted address is the sum of prev_addr and stride. The state information is also provided. If the state is ‘predict’ or ‘weakly predict’, the predicted address is valid. Otherwise, the prediction is not initiated”, and “The comparison of the predicted address with the actual one can be done in parallel with the address calculation [4], and thus the data fetching using the actual address is suppressed when two addresses match”. If they do no match, “Otherwise, I1 fetches data again using the actual address (item of combined prediction information which corresponds to values of the respective sets of prediction information) and I2 is invalidated and reissued as shown in Fig. 9”).
Regarding claim 4, the combination of Sato and Zouzias teach all the claim limitations of claim 2 above; and further teach in which the predictor control circuitry is configured to determine whether the second predictor lookup suppression condition is satisfied for the prediction input address depending on analysis of at least a subset of the items of combined prediction information specified by the selected combiner cache entry (Sato, sections 3.2 and 3.5 teach measuring processor (predictor control circuitry) performance when executing “[t]he comparison of the predicted address with the actual one can be done in parallel with the address calculation [4], and thus the data fetching using the actual address is suppressed when two addresses match (suppression condition is satisfied…indicating that the combined prediction…is likely to be derivable from a prediction outcome predicted by the first predictor)” from the RPT data including “the previous data address (prev addr), the stride value (stride), and the state information (state) (subset).”).
Regarding claim 5, the combination of Sato and Zouzias teach all the claim limitations of claim 2 above; and further teach in which the combiner hint data structure comprises the combiner cache structure (Sato, sections 3.2 and 3.5 teach “The RPT, which has a similar structure with the instruction cache (combiner cache structure), is…[applied]…to predict the data address (entry) because of its simplicity.”).
Regarding claim 6, the combination of Sato and Zouzias teach all the claim limitations of claim 2 above; and further teach in which the combiner hint data structure is separate from the combiner cache structure and is configured to store combiner hint information providing a summary of information derivable from the combiner cache structure (Sato, sections 3.2, 3.5, and 4.1 teach “The RPT (combiner cache structure), which has a similar structure with the instruction cache (combiner hint data structure), is…[applied]…to predict the data address (entry) because of its simplicity”; wherein the instruction memory cache is used for instruction supply including an input address).
Regarding claim 7, the combination of Sato and Zouzias teach all the claim limitations of claim 2 above; and further teach in which: in response to resolution of an actual outcome associated with a prediction for a previous prediction input address, the combiner circuitry is configured to:
update the combiner prediction state information of the at least one combiner table structure corresponding to the previous prediction input address (Sato, sections 3.2-3.3 and 3.5 teach “the state transition of the RPT. If a prediction is correct, the counter is incremented (update). Otherwise, it is decremented (update). When the most significant bit is 1, the state is ‘(weakly) predict’ and thus the predicted address is valid”); and
update a corresponding combiner cache entry of the combiner cache structure corresponding to the previous prediction input address, based on an updated combined prediction generated from the updated combiner prediction state information (Sato, sections 3.2-3.3 and 3.5 teach from the prediction, “An entry of the RPT is indexed (update) by the instruction address and holds the previous data address (prev addr), the stride value (stride), and the state information (state).”).
Regarding claim 8, the combination of Sato and Zouzias teach all the claim limitations of claim 2 above; and further teach in which the combiner circuitry is configured to suppress allocation of a new combiner cache entry to the combiner cache structure in response to a determination that each valid item of combined prediction information to be specified in the new combiner cache entry based on the updated combined prediction satisfies a redundant allocation condition (Sato, sections 3.2 and 3.5 teach measuring processor (combiner circuitry) performance when executing “[t]he comparison of the predicted address with the actual one can be done in parallel with the address calculation [4], and thus the data fetching using the actual address is suppressed when two addresses match (suppress allocation of a new combiner cache entry…in response to a determination that each valid item of combined prediction information to be specified in the new combiner cache entry based on the updated combined prediction satisfies a redundant allocation condition)” from the RPT data including “the previous data address (prev addr), the stride value (stride), and the state information (state).”);
wherein a given item of combined prediction information, for which selection of the given item of combined prediction information as a selected item of combined prediction information to be used for generating the prediction would depend on first prediction information generated by the first predictor corresponding to a given prediction outcome, satisfies the redundant allocation condition when the updated combined prediction to be specified in the given item of combined prediction information specifies the same prediction outcome as the given prediction outcome (Sato, sections 3.2 and 3.5 teach the “predicted address is used only when the value predictor is unable to predict a load value and the load address predictor accounting (depend on first prediction information generated by the first predictor corresponding to a given prediction outcome)”; and “[t]he comparison of the predicted address with the actual one can be done in parallel with the address calculation [4], and thus the data fetching using the actual address is suppressed when two addresses match (satisfies the redundant allocation condition)”).
Regarding claim 9, the combination of Sato and Zouzias teach all the claim limitations of claim 2 above; and further teach in which the predictor control circuitry is configured to determine that the second predictor lookup suppression condition is satisfied in response to determining, based on the lookup of the prediction input address in the combiner hint data structure, that a miss would be detected in a lookup of the prediction input address in the combiner cache structure (sections 3.2 and 3.5 teach measuring processor (predictor control circuitry) performance when executing “The comparison of the predicted address with the actual one can be done in parallel with the address calculation [4], and thus the data fetching using the actual address is suppressed when two addresses match (suppression condition is satisfied). I2 speculates data dependence (determining) using the load value which is read using the predicted address, and when the prediction is correct the speculation finishes as shown in Fig. 8. Otherwise (a miss would be detected), I1 fetches data again using the actual address and I2 is invalidated and reissued as shown in Fig. 9”).
Regarding claim 10, the combination of Sato and Zouzias teach all the claim limitations of claim 2 above; and further teach in which the predictor control circuitry is configured to determine that the second predictor lookup suppression condition is satisfied in response to determining, based on the lookup of the prediction input address in the combiner hint data structure, that all valid items of combined prediction information indicated by a combiner cache entry corresponding to the prediction input address satisfy a derivable condition (Sato, sections 3.2 and 3.5 teach measuring processor (predictor control circuitry) performance when executing “[t]he comparison of the predicted address with the actual one can be done in parallel with the address calculation [4], and thus the data fetching using the actual address is suppressed when two addresses match (suppression condition is satisfied… all valid items of combined prediction information indicated by a combiner cache entry corresponding to the prediction input address satisfy a derivable condition)” from the RPT data (lookup) including “the previous data address (prev addr), the stride value (stride), and the state information (state).”),
where a given valid item of combined prediction information, that is associated with a given possible value for first prediction information generated by the first predictor, satisfies the derivable condition when the given valid item of combined prediction information indicates a combined prediction which is derivable from the prediction outcome that would be predicted by the first predictor for the prediction input address when the first prediction information generated by the first predictor has the given possible value (Sato, sections 3.2 and 3.5 teach measuring processor (predictor control circuitry) performance when executing cooperative predictor outputs including a load value predictor computing an output for an input address instruction and “The predicted address is used only when the value predictor is unable to predict a load value (independent)”; thus, a predicted load is interpreted as satisfying the suppression condition).
Regarding claim 11, the combination of Sato and Zouzias teach all the claim limitations of claim 2 above; and further teach in which the predictor control circuitry is configured to determine that the second predictor lookup suppression condition is satisfied in response to determining, based on the lookup of the prediction input address in the combiner hint data structure, that all valid items of combined prediction information in a selected subset of items of combined prediction information indicated by a combiner cache entry corresponding to the prediction input address satisfy a derivable condition (Sato, sections 3.2 and 3.5 teach measuring processor (predictor control circuitry) performance when executing “[t]he comparison of the predicted address with the actual one can be done in parallel with the address calculation [4], and thus the data fetching using the actual address is suppressed when two addresses match (suppression condition is satisfied in response to determining…items…satisfy a derivable condition)” from the RPT data (lookup) including “the previous data address (prev addr), the stride value (stride), and the state information (state) (valid items…subset).”),
where a given valid item of combined prediction information, that is associated with a given possible value for first prediction information generated by the first predictor, satisfies the derivable condition when the given valid item of combined prediction information indicates a combined prediction which is derivable from the prediction outcome that would be predicted by the first predictor for the prediction input address when the first prediction information generated by the first predictor has the given possible value (Sato, sections 3.2 and 3.5 teach a load value predictor computing an output and “The predicted address is used only when the value predictor is unable to predict a load value”; thus, a predicted load is interpreted as satisfying the suppression condition (given valid item of combined prediction information, that is associated with a given possible value for first prediction information generated by the first predictor, satisfies the derivable condition)), and
the selected subset of items comprises the items of combined prediction information which correspond to a specific value of first prediction information generated by the first predictor for the prediction input address and a plurality of different possible values one or more other sets of prediction information generated by one or more of the plurality of predictors other than the first predictor (Sato, sections 3.2 and 3.5 teach a load value predictor computing an output for the input address data (correspond to a specific value of first prediction information generated by the first predictor for the prediction input address) and “The predicted address is used (and a plurality of different possible values one or more other sets of prediction information generated by one or more of the plurality of predictors other than the first predictor) only when the value predictor is unable to predict a load value”; thus, a predicted load is interpreted as satisfying the suppression condition (subset of items comprises the items)).
Regarding claim 12, the combination of Sato and Zouzias teach all the claim limitations of claim 2 above; and further teach in which at least when a predetermined second predictor lookup suppression mode is enabled, the predictor control circuitry is configured to determine that the second predictor lookup suppression condition is satisfied in response to determining, based on the lookup of the prediction input address in the combiner hint data structure, that less than a predetermined fraction of valid items of combined prediction information indicated by a combiner cache entry corresponding to the prediction input address do not satisfy a derivable condition (Examiner note: this is interpreted as a double negative limitation; thus, under BRI and interpreting in the positive: if one valid item satisfies the derivable condition, then the suppression condition is satisfied.
Sato, sections 3.2 and 3.5 teach measuring processor (predictor control circuitry) performance when executing “[t]he comparison of the predicted address with the actual one can be done in parallel with the address calculation [4], and thus the data fetching using the actual address is suppressed when two addresses match (suppression mode is enabled…suppression condition is satisfied in response to determining…items…satisfy a derivable condition)” from the RPT data (lookup) including “the previous data address (prev addr), the stride value (stride), and the state information (state) (valid items).”),
where a given valid item of combined prediction information, that is associated with a given possible value for first prediction information generated by the first predictor, satisfies the derivable condition when the given valid item of combined prediction information indicates a combined prediction which is derivable from the prediction outcome that would be predicted by the first predictor for the prediction input address when the first prediction information generated by the first predictor has the given possible value (Sato, sections 3.2 and 3.5 teach measuring processor (predictor control circuitry) performance when executing cooperative predictor outputs including a load value predictor computing an output for an input address instruction and “The predicted address is used only when the value predictor is unable to predict a load value (independent)”; thus, a predicted load is interpreted as satisfying the suppression condition).
Regarding claim 13, the combination of Sato and Zouzias teach all the claim limitations of claim 12 above; and further teach in which the predictor control circuitry is configured to control whether the predetermined second predictor lookup suppression mode is enabled or disabled based on monitoring of a misprediction heuristic (Sato, sections 3.2 and 3.5 teach “Whenever a load instruction is encountered both the value and the address predictors initiate prediction. The predicted address is used only when the value predictor is unable to predict a load value (suppression mode is enabled or disabled based on monitoring of a misprediction heuristic)”).
Regarding claim 14, the combination of Sato and Zouzias teach all the claim limitations of claim 1 above; and further teach in which the second predictor is configured to generate second prediction information based on a lookup of a second predictor structure based on local history information tracking history for a specific subset of addresses including the prediction target address (Sato, sections 3.2 and 3.5 teach load address predictor using a “reference prediction table (RPT) (lookup…table structure)… An entry of the RPT is indexed by the instruction (given) address and holds the previous data address (prev addr) (local history information), the stride value (stride) (alternative local history information), and the state information (state). The stride is the difference between last two data addresses generated by an instruction (subset of addresses). The state information encodes the past history and indicates whether next prefetching is initiated”); and
the first predictor is configured to generate first prediction information based on a lookup of a first predictor structure independent of the local history information (Sato, sections 3.2 and 3.5 teach a load value predictor computing an output and “The predicted address is used only when the value predictor is unable to predict a load value (independent)”).
Regarding claim 15, the combination of Sato and Zouzias teach all the claim limitations of claim 1 above; and further teach in which the first predictor comprises a first TAGE (tagged-geometric) predictor comprising a first set of tagged-geometric tables looked up based on different lengths of first history information (Zouzias, sections 2-3 and 5.1 teach “we employ the latest TAGE-SC-L models [28] for our study (first predictor comprises a first TAGE (tagged-geometric) predictor)”, wherein “TAGE predictors are based on the PPM data compression scheme [5]. They employ a plurality of tables that are indexed using overlapping history slices of increasing lengths, hashed (XOR-ed) with the branch address. Table entries contain (partially) tagged saturating counters that model the prediction”); and
the second predictor comprises a second TAGE predictor comprising a second set of tagged-geometric tables looked up based on different lengths of second history information (Zouzias, sections 2-3 and 5.1 teach “we employ the latest TAGE-SC-L models [28] for our study (first predictor comprises a first TAGE (tagged-geometric) predictor)”, wherein “TAGE predictors are based on the PPM data compression scheme [5]. They employ a plurality of tables that are indexed using overlapping history slices of increasing lengths, hashed (XOR-ed) with the branch address. Table entries contain (partially) tagged saturating counters that model the prediction”).
Sato and Zouzias are combinable for the same rationale as set forth above with respect to claims 1 and 19-20.
Regarding claim 16, the combination of Sato and Zouzias teach all the claim limitations of claim 1 above; and further teach in which the prediction comprises a branch prediction (Sato, sections 3.2 and 4.1 teach utilizing branch predictors).
Regarding claim 17, the combination of Sato and Zouzias teach all the claim limitations of claim 1 above; and further teach A system comprising: the prediction circuitry of claim 1, implemented in at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board (Sato, sections 3.1, 3.5, and 4.1 teach measuring processor performance and utilizing memory performing the embodiments of the disclosure).
Regarding claim 18, the combination of Sato and Zouzias teach all the claim limitations of claim 1 above; and further teach A chip-containing product comprising the system of claim 17 assembled on a further board with at least one other product component (Sato, sections 3.1, 3.5, and 4.1 teach measuring processor performance and utilizing memory performing the embodiments of the disclosure).
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Schoeler et al (US Pub 20220383146) teach utilizing geometric tagging and machine learning algorithms.
Conclusion
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/C.M./Examiner, Art Unit 2123
/ALEXEY SHMATOV/Supervisory Patent Examiner, Art Unit 2123
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