DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-5, 7-9 have been considered but are moot because the new ground of rejection relies on a new reference for teaching matters specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 4, 5, 8, 9, 23-29, 33-35 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2006/0076694 (Chen), cited by Applicant, in view of U.S. Patent Application Publication No. 2022/0238422 (Nikitin), U.S. Patent Application Publication No. 2009/0311087 (Na), and WO Publication No. 2007/017945 (Ogushi).
Chen discloses
1. (Currently Amended) A chip package structure, comprising:
a bare chip carrier 20/42/64 comprising a first side (top);
a bare chip 10/48/62 located on the first side (top);
a package body 22/52/70 comprising an outer surface and configured to cover the bare chip 10/48/64 to package the bare chip 10/48/62 on the bare chip carrier 20/42/64; and
a recess structure 24/54/72 located on the outer surface, configured to increase a heat dissipation area of the package body 22/52/70, and comprising:
at least one groove 24b.
Chen fails to disclose
wherein each groove of the at least one groove is connected end- to-end and forms a closed pattern, and
wherein the closed pattern is configured to allow a vacuum chuck covering a first groove of the at least one groove to separate a region inside the first groove from an atmosphere; and
a plurality of holes distributed around the at least one groove.
Nitikin teaches
A chip package structure comprising:
a package body 106 having an outer surface;
a recess structure 130/120/108 located on the outer surface, and having:
at least one groove 130,
wherein each groove 130 of the at least one groove 130 is connected end-to-end and forms a closed pattern.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a recess structure having at least one groove, wherein the groove is connected end-to-end to form a closed pattern in Chen. The motivation would be to provide a cooling solution with higher thermal conductivity while maintaining acceptable levels of electrical isolation, and to prevent lateral movement of a conduction plate as taught by Nitikin ([0004], [0059]).
Na teaches
A chip package structure comprising:
wherein the closed pattern 100 is configured to allow a vacuum chuck (through 120a/120b, 130a/130b, 201a/210b, 310a/310b) covering a first groove of the at least one groove 140a/140b (146a/146b) to separate a region inside the first groove from an atmosphere ([0064], [0079]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a vacuum chuck to separate the groove from an atmosphere to in Chen. The motivation would be to enable vacuum adsorption and automated handling of the package as taught by Na ([0025]-[0028]).
Ogushi teaches
A chip package structure comprising:
a recess structure 2 comprising:
at least one groove 6;
a plurality of holes 8 distributed around the at least one groove 6.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of holes around the groove in Takaishi. The motivation would be to improve cooling capacity as taught by Ogushi ([0017]).
Nitikin teaches
4. (Currently Amended) The chip package structure of claim 1, wherein the at least one groove 130 forms at least one of a polygon, a rounded polygon, a circle, or an ellipse.
Nitikin teaches
5. (Currently Amended) The chip package structure of claim 1, wherein a cross section of the at least one groove 130 is in at least one of a rectangular shape, a trapezoidal shape, a semicircular shape, a U shape, or a V shape.
Ogushi teaches ([0016], obvious design choice, see MPEP 2144.04)
8. (Previously Presented) The chip package structure of claim 1, wherein the holes 8 are in at least one of a prism shape, a pyramid shape, a frustum shape, a cylindrical shape, a conical shape, a conical frustum shape, or a hemispherical shape.
Chen discloses
9. (Previously Presented) The chip package structure of claim 1, wherein the package body 22/52/70 comprises a top surface away from the bare chip carrier 10/48/62, and wherein the recess structure 24/54/72 is located on the top surface.
Na teaches
23. (New) The chip package structure of claim 1, wherein the closed pattern 100 is configured such that, after the region is vacuumed by the vacuum chuck (through 120a/120b, 130a/130b, 201a/210b, 310a/310b),
Na teaches
24. (New) The chip package structure of claim 1, wherein the closed pattern 100 is configured to facilitate automated transfer of
Nitikin teaches
25. (New) The chip package structure of claim 1, wherein each groove of the at least one groove 130 is configured to define a closed region on the outer surface of the package body 106, and wherein the closed region is configured to be isolated from the atmosphere by the vacuum chuck (Na) covering the first groove 130.
Chen discloses
26. (New) The chip package structure of claim 1, wherein the package body 22/52/70 is made of an electrically insulating material.
Chen discloses
27. (New) The chip package structure of claim 1, wherein the recess structure 24/54/72 is integrally formed on the outer surface of the package body 22/52/70.
Ogushi teaches
28. (New) The chip package structure of claim 1, wherein the plurality of holes 8 are disposed outside the closed pattern formed by the first groove (Nitikin).
Nitikin teaches
29. (New) The chip package structure of claim 1, wherein a shape formed by the at least one groove 130 is consistent with a shape of a top surface of the package body 106.
Chen discloses
33. (New) The chip package structure of claim 1, wherein a material of the package body 22/52/70 comprises an epoxy resin.
Chen discloses
34. (New) The chip package structure of claim 1, wherein a material of the package body 22/52/70 comprises a ceramic ([0026]).
Chen discloses
35. (New) The chip package structure of claim 1, wherein a heat conduction path from the bare chip 10/48/62 to an inner side wall of the first groove 24b is shorter than a heat conduction path from the bare chip 10/48/62 to a top surface of the package body 22/52/70.
Claim(s) 3, 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Nitikin, Na and Ogushi as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2004/0232545 (Takaishi).
The combination of references fails to teach
3. (Previously Presented) The chip package structure of claim 1, wherein the at least one groove comprises a plurality of grooves distributed concentrically.
The combination of references fails to teach
31. (New) The chip package structure of claim 1, wherein the bare chip carrier is a lead frame comprising a plurality of pins bent toward a same side, and wherein the recess structure is provided on a top surface of the package body away from the pins of the lead frame.
Takaishi discloses (Fig. 8(a)-(c))
A chip package structure comprising:
wherein the at least one groove 26p comprises a plurality of grooves distributed concentrically;
wherein the bare chip carrier 3, 8, 9 is a lead frame comprising a plurality of pins 3D, 3S, 3G bent toward a same side 4B, and wherein the recess structure is provided on a top surface of the package body (Chen) away from the pins 3D, 3S, 3G of the lead frame 3, 8, 9.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to distribute the plurality of grooves in a desired manner and to provide grooves having a desired shape in the modified package of Chen. The motivation would be to mere duplication of parts and based on routine engineering design considerations such as thermal management, mechanical reliability, and adhesion as taught by Takaishi ([0008], [0023], [0030], [0031]). Further, providing a lead frame with a recess which maintains access to the pins would have merely been an arrangement of known package features according to their established functions as taught by Takaishi. See MPEP 2144.04.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Nitikin, Na, and Ogushi as applied to claim 1 above, and further in view of JP Publication No. 4688526 (Noguchi).
The combination of references fails to teach
7. (Previously Presented) The chip package structure of claim 1, wherein the holes are further distributed in an array.
Noguchi teaches
A chip package structure comprising:
wherein the holes 32 are further distributed in an array.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of holes around the groove in the modified device of Chen. The motivation would be to improve heat dissipation as taught by Noguchi.
Claim(s) 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Nitikin, Na and Ogushi as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2010/0059865 (Low).
The combination of references fails to teach
30. (New) The chip package structure of claim 1, wherein the bare chip carrier is a package substrate comprising a first pin on one side of the package substrate and a second pin on another side of the package substrate, wherein the first pin and the second pin are connected to each other inside the package substrate, and wherein the bare chip is connected to the package substrate through a lead.
Low teaches
A chip package structure comprising:
wherein the bare chip carrier 12 is a package substrate comprising a first pin 24 on one side of the package substrate and a second pin 40 on another side of the package substrate (not depicted, [0024]), wherein the first pin 24 and the second pin 40 are connected to each other inside the package substrate (38), and wherein the bare chip 14 is connected to the package substrate through a lead 30.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide pins and a lead in the modified package of Chen. The motivation would be to provide a well-known electrical interconnection between a chip and external circuitry through opposite sides of a package substrate as taught by Low. See MPEP 2144.03.
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Nitikin, Na and Ogushi as applied to claim 1 above, and further in view of DE Publication No. 10-2006/007303 (Dobritz, counterpart of U.S. Patent Application Publication No. 2007/0230115, cited by Applicant).
The combination of references fails to teach
32. (New) The chip package structure of claim 31, wherein the recess structure is further provided on a bottom surface of the package body opposite to the top surface.
Dobritz teaches
A chip package structure comprising:
wherein the recess structure 41 is further provided on a bottom surface of the package body 4 opposite to the top surface.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a recess structure on both the top and bottom surfaces of the package body in the modified package of Chen. The motivation would be optimal heat dissipation as taught by Dobritz.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent No. 5,195,023 (Manzione), 5,342,068 (Large), 8,304,285 (Gerber), JP Publication No. 2002-334944 (Shoji), WO Publication No. 2004/073029 (Sheydayi) teach recess structures on the outer surface of a package body to provide a larger air-contact area without reducing the overall thickness.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893
