DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant's response of 03/05/2026 has been acknowledged. No claims have been amended. No new matter has been added.
This office action considers claims 1-30 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant’s arguments filed 03/05/2026 with respect to the rejection of claims 1, 3, 5, 16, 18, and 28-30 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Wu et al. (US 20210366877 A1 – hereinafter Wu).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1 and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210366877 A1 – hereinafter Wu) in view of Ting et al. (US 20240088048 A1 – hereinafter Ting).
Regarding independent claim 1, Wu teaches
(Original) A device ([0070] – “By utilizing the embodiments described
herein, the performance of a device package may be improved, and the reliability of a device package may be improved” – this pertains to a device) comprising:
a substrate (Fig. 1 annotated, see below – hereinafter ‘SUB’) comprising:
first conductors (Fig. 1 annotated, see below – [0019] – “Conductive pillars
105” – hereinafter ‘105a’) electrically connecting first contacts (105 – Fig. 1 – these are contacts) on a first side of the substrate (Fig. 1 annotated, see below – hereinafter ‘TOP’) to second contacts (Fig. 1 annotated, see below – hereinafter ‘105BOT’) on a second side of the substrate (Fig. 1 annotated, see below – hereinafter ‘BOT’), the first conductors (105a) including:
a first set of metal lines (108 – Fig. 1 – [0017] – “routing layers 108/109 and/or through vias 110 may comprise one or more layers of copper, nickel, aluminum, other conductive materials” – these are metal lines) arranged in a first set of metal layers (Fig. 1 annotated, see below – hereinafter ‘ML’) separated from one another by a first set of dielectric layers (118 – Fig. 1 – [0017] – “dielectric layers 118/119”); and
a first set of conductive vias (110 – fig. 1 – [0017] – “vias 110”)
interconnecting the first set of metal lines (108) through the first set of dielectric layers (118 – Fig. 1 shows this); and
second conductors electrically connecting third contacts on the first side of the substrate to fourth contacts on the first side of the substrate (TOP) to define conductive paths between a first die and a second die, wherein the second conductors include:
a second set of metal lines arranged in a second set of metal layers that are separated from one another by a second set of dielectric; and
a second set of conductive vias interconnecting the second set of metal lines, and
wherein at least one metal layer of the second set of metal layers is devoid
of metal lines of the first set of metal lines.
PNG
media_image1.png
680
1135
media_image1.png
Greyscale
Wu does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Ting teaches
second conductors (62B – Fig. 1G – [0026] – “the bonding conductors 62B”) electrically connecting third contacts (132B – Fig. 1G – [0026] – “the bonding conductors 132B”) on the first side of the substrate to fourth contacts (62B – Fig. 1G – [0021] – “bonding conductors 62B”) on the first side of the substrate to define conductive paths between a first die (100 – Fig. 1G – [0036] – “semiconductor dies 100” – this is the left 100) and a second die (100 – Fig. 1G – [0036] – “semiconductor dies 100” – this is the right 100), wherein the second conductors (62B) include:
a second set of metal lines (16 – Fig. 1G – [0035] – “interconnect wirings 16”) arranged in a second set of metal layers that are separated from one another by a second set of dielectric (18A – Fig, 1A – [0041] – “interlayer dielectric layer 18A”); and
a second set of conductive vias (52 – Fig. 1G – [0029] – “vias 52”) interconnecting the second set of metal lines (16 – Fig. 1G shows this), and
wherein at least one metal layer of the second set of metal layers is devoid
of metal lines of the first set of metal lines (42 – Fig. 1E – [0019] – “dielectric layer 42” – this is devoid of metal lines as shown).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second conductor structure as taught by Ting into Wu.
An ordinary artisan would have been motivated to use the known technique of Ting in the manner set forth above to produce the predictable result [0003] – “The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. Multiple electronic components such as integrated circuit dies may also require to be packaged integrally, in some applications.”
Regarding claim 10, Wu, as modified by Ting, teaches claim 1 from which claim 10 depends. Wu further teaches
(Original) The device of claim 1, wherein the first set of metal lines
(402 – Fig. 18 – [0056] – “first redistribution structure 402 may be wider or thicker than the conductive lines and/or vias of the metallization patterns of the second redistribution structure 408”) have a first characteristic line width and the second set of metal lines (402 – Fig. 18 – [0056] – “first redistribution structure 402 may be wider or thicker than the conductive lines and/or vias of the metallization patterns of the second redistribution structure 408”) have a second characteristic line width, and wherein the first characteristic line width is greater than the second characteristic line width ([0056] – “first redistribution structure 402 may be wider or thicker than the conductive lines and/or vias of the metallization patterns of the second redistribution structure 408”).
Regarding claim 11, Wu, as modified by Ting, teaches claim 1 from which claim 11 depends. Wu further teaches
(Original) The device of claim 1, wherein the first set of metal layers
(402 – Fig. 18 – [0056] – “first redistribution structure 402 may be wider or thicker than the conductive lines and/or vias of the metallization patterns of the second redistribution structure 408”) have a first characteristic layer thickness and the second set of metal layers (402 – Fig. 18 – [0056] – “first redistribution structure 402 may be wider or thicker than the conductive lines and/or vias of the metallization patterns of the second redistribution structure 408”) have a second characteristic layer thickness, and wherein the first characteristic layer thickness is greater than the second characteristic layer thickness ([0056] – “first redistribution structure 402 may be wider or thicker than the conductive lines and/or vias of the metallization patterns of the second redistribution structure 408”).
Regarding claim 12, Wu, as modified by Ting, teaches claim 1 from which claim 12 depends. Wu further teaches
(Original) The device of claim 1, wherein the first set of dielectric
layers have a first characteristic thickness and the second set of dielectric layers have a second characteristic thickness, and wherein the first characteristic thickness is greater than the second characteristic thickness ([0055] – “one or more of the dielectric layers of the second redistribution structure 408 may have a different thickness than other dielectric layers of the second redistribution structure 408”).
Regarding claim 13, Wu, as modified by Ting, teaches claim 1 from which claim 13 depends. Wu further teaches
(Original) The device of claim 1, further comprising a plurality of
solder balls electrically connected to the second contacts (205F – Fig. 8 – [0036] –“conductive lines 205F” – this is a contact) to form a ball grid array ([0038] – “conductive connectors 212 may be ball grid array (BGA) connectors, solder balls”).
Regarding independent claim 14, Wu teaches
(Original) A device comprising:
a first die (252A – Fig. 19 – [0067] – “I/O die 252A”) comprising first circuitry (wu (I/O has a specific circuitry, hereinafter ‘I/O’);
a second die (252B – Fig. 19 – [0067] – “logic die 252B”) comprising second circuitry (I/O die and logic die have different circuitry – hereinafter ‘logic’); and
a substrate (Fig. 1 annotated, see below – hereinafter ‘SUB’) configured to electrically connect the first circuitry (I/O) to the second circuitry (logic) and to electrically connect the first circuitry (I/O), the second circuitry (logic), or both, to one or more off-package devices (500 – Fig. 19 – [0067] – “integrated circuit packages 550 may be similar or may be different from each other” – these are off-package devices), first conductors (wu (Fig. 1 annotated, see below – [0019] – “Conductive pillars 105” – hereinafter ‘105a’) electrically connecting first contacts (105 – Fig. 1 – these are contacts) on a first side of the (Fig. 1 annotated, see below – hereinafter ‘TOP’) to second contacts (Fig. 1 annotated, see below – hereinafter ‘105BOT’) on a second side of the substrate (Fig. 1 annotated, see below – hereinafter ‘BOT’), the first conductors (105a) including:
a first set of metal lines (108 – Fig. 1 – [0017] – “routing layers 108/109 and/or through vias 110 may comprise one or more layers of copper, nickel, aluminum, other conductive materials” – these are metal lines) arranged in a first set of metal layers (Fig. 1 annotated, see below – hereinafter ‘ML’) separated from one another by a first set of dielectric layers (118 – Fig. 1 – [0017] – “dielectric layers 118/119”); and
a first set of conductive vias (110 – fig. 1 – [0017] – “vias 110”) interconnecting the first set of metal lines (108) through the first set of dielectric layers (118 – Fig. 1 shows this); and
second conductors electrically connecting third contacts on the first side of the substrate to fourth contacts on the first side of the substrate and the second die, wherein the second conductors include:
a second set of metal lines arranged in a second set of metal layers that are separated from one another by a second set of dielectric layers; and
a second set of conductive vias interconnecting the second set of metal lines, and
wherein at least one metal layer of the second set of metal layers is devoid
of metal lines of the first set of metal lines.
PNG
media_image1.png
680
1135
media_image1.png
Greyscale
Wu does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Ting teaches
second conductors (62B – Fig. 1G – [0026] – “the bonding conductors 62B”) electrically connecting third contacts (132B – Fig. 1G – [0026] – “the bonding conductors 132B”) on the first side of the substrate to fourth contacts (62B – Fig. 1G – [0021] – “bonding conductors 62B”) on the first side of the substrate (100 – Fig. 1G – [0036] – “semiconductor dies 100” – this is the left 100) and the second die (100 – Fig. 1G – [0036] – “semiconductor dies 100” – this is the right 100), wherein the second conductors (62B) include:
a second set of metal lines (16 – Fig. 1G – [0035] – “interconnect wirings 16”) arranged in a second set of metal layers that are separated from one another by a second set of dielectric layers (18A – Fig, 1A – [0041] – “interlayer dielectric layer 18A”); and
a second set of conductive vias (52 – Fig. 1G – [0029] – “vias 52”) interconnecting the second set of metal lines (16 – Fig. 1G shows this), and
wherein at least one metal layer of the second set of metal layers is devoid
PNG
media_image1.png
680
1135
media_image1.png
Greyscale
of metal lines of the first set of metal lines (42 – Fig. 1E – [0019] – “dielectric layer 42” – this is devoid of metal lines as shown).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second conductor structure as taught by Ting into Wu.
An ordinary artisan would have been motivated to use the known technique of Ting in the manner set forth above to produce the predictable result as stated above in claim 1.
Claims 2, 4, 6-9, 15, 17, and 19-25 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Ting and Lin et al. (US 20210202394 A1 – hereinafter Lin).
Regarding claim 2, Wu as modified by Ting, teaches claim 1 from which claim 2 depends. Wu and Ting do not expressly disclose the limitations of claim 2.
However, in an analogous art, Lin teaches
(Original) The device of claim 1, wherein the first set of metal layers and the second set of metal layers are distinct and non-overlapping ([0027] – “a first substrate 110 has a recessed region 111 configured to receive a second substrate 120” – since 120 and 110 are formed separately the metal layers are distinct and not overlapping, Fig. 1D shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer structure as taught by Lin into Wu and Ting.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable results [0002] – “to provide a higher density of die-to-die interconnections in a package process.”
Regarding claim 4, Wu as modified by Ting, teaches claim 1 from which claim 4 depends. Wu and Ting do not expressly disclose the limitations of claim 4.
However, in an analogous art, Lin teaches
(Original) The device of claim 1, wherein a cross-section of a post structure of each of the first contacts (140 – Fig. 1D – [0031] – “first conductive elements 140”) is different from a cross-section of a post structure of each of the third contacts (125) and each of the fourth contacts (125-4 - Lin shows this in Fig. 1D where the first contacts 140 are round shaped while third contact 125 and fourth contacts 125-4 are rectangular shapes).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the post structure as taught by Lin into Wu.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable results as stated above in claim 2.
Regarding claim 6, Wu as modified by Ting, teaches claim 1 from which claim 6 depends. Wu and Ting do not expressly disclose the limitations of claim 6.
However, in an analogous art, Lin teaches
(Original) The device of claim 1, further comprising: the first die (130b) coupled to the third contacts (125) and to a first subset of the first contacts; and the second die (130a) coupled to the fourth contacts (125-4) and to a second subset of the first contacts (Fig. 1D shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the die structure as taught by Lin into Wu.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable results as stated above in claim 2.
Regarding claim 7, Wu as modified by Ting, teaches claim 1 from which claim 7 depends. Wu and Ting do not expressly disclose the limitations of claim 7.
However, in an analogous art, Lin teaches
(Original) The device of claim 1, wherein the second set of conductors (150 – Fig. 1D – [0031] – “second conductive elements 150”) are disposed within a die-to-die interconnect region (120), and wherein no metal line of the first set of metal lines (115 – Fig. 1D – [0028] – “pads 115” – these are metal lines) traverses the die-to-die interconnect region (120 – Fig. 1D shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the die structure as taught by Lin into Wu.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable results as stated above in claim 2.
Regarding claim 8, Wu as modified by Ting, teaches claim 1 from which claim 8 depends. Wu and Ting do not expressly disclose the limitations of claim 8.
However, in an analogous art, Lin teaches
(Original) The device of claim 1, wherein no metal line of the first set of metal lines (115) is coplanar with
any metal line of the second set of metal lines (125 – Fig. 1D shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal line structure as taught by Lin into Wu.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable results as stated above in claim 2.
Regarding claim 9, Wu as modified by Ting, teaches claim 1 from which claim 9 depends. Wu and Ting do not expressly disclose the limitations of claim 9.
However, in an analogous art, Lin teaches
(Original) The device of claim 1, wherein the first set of metal lines (140) have first characteristic
dimensions and the second set of metal lines (150) have second characteristic dimensions, and wherein the first characteristic dimensions are greater than the second characteristic dimensions ([0036] – “the height of each of the second conductive elements 150 is smaller than the height of each of the first conductive elements 140”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal line structure as taught by Lin into Wu.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable results as stated above in claim 2.
Regarding claim 15, Wu as modified by Ting, teaches claim 14 from which claim 15 depends. Wu and Ting do not expressly disclose the limitations of claim 15.
However, in an analogous art, Lin teaches
(Original) The device of claim 14, wherein the first set of metal layers and
the second set of metal layers are distinct and non-overlapping ([0027] – “a first substrate 110 has a recessed region 111 configured to receive a second substrate 120” – since 120 and 110 are formed separately the metal layers are distinct and not overlapping, Fig. 1D shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer structure as taught by Lin into Wu.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable results as stated in claim 2.
Regarding claim 17, Wu as modified by Ting, teaches claim 14 from which claim 17 depends. Wu and Ting do not expressly disclose the limitations of claim 17.
However, in an analogous art, Lin teaches
(Original) The device of claim 14, wherein a cross-section of a post structure of each of the first contacts (140 – Fig. 1D – [0031] – “first conductive elements 140”) is different from a cross-section of a post structure of each of the third contacts (125) and each of the fourth contacts (125-4 - Lin shows this in Fig. 1D where the first contacts 140 are round shaped while third contact 125 and fourth contacts 125-4 are rectangular shapes).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the post structure as taught by Lin into Wu.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable results as stated in claim 2.
Regarding claim 19, Wu as modified by Ting, teaches claim 14 from which claim 19 depends. Wu and Ting do not expressly disclose the limitations of claim 19.
However, in an analogous art, Lin teaches
(Original) The device of claim 14, wherein the second set of conductors
(150 – fig. 1D – [0031] – “second conductive elements 150”) are disposed within a die-to-die interconnect region (120), and wherein no metal line of the first set of metal lines (115 – Fig. 1D – [0028] – “pads 115” – these are metal lines) traverses the die-to-die interconnect region (120 – Fig. 1D shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second conductors structure as taught by Lin into Wu.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable results as stated in claim 2.
Regarding claim 20, Wu as modified by Ting, teaches claim 14 from which claim 20 depends. Wu and Ting do not expressly disclose the limitations of claim 20.
However, in an analogous art, Lin teaches
(Original) The device of claim 14, wherein no metal line of the first set of
metal lines (115) is coplanar with any metal line of the second set of metal lines (125 – Fig. 1D shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal line structure as taught by Lin into Wu.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable results as stated in claim 2.
Regarding claim 21, Wu as modified by Ting, teaches claim 14 from which claim 21 depends. Wu and Ting do not expressly disclose the limitations of claim 21.
However, in an analogous art, Lin teaches
(Original) The device of claim 14, wherein the first set of metal lines (140)
have first characteristic dimensions and the second set of metal lines (150) have second characteristic dimensions, and wherein the first characteristic dimensions are greater than the second characteristic dimensions ([0036] – “the height of each of the second conductive elements 150 is smaller than the height of each of the first conductive elements 140”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal line structure as taught by Lin into Wu.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable results as stated in claim 2.
Regarding claim 22, Wu as modified by Ting, teaches claim 14 from which claim 22 depends. Wu and Ting do not expressly disclose the limitations of claim 22.
(Original) The device of claim 14, wherein the first set of metal lines
(402 – Fig. 18 – [0056] – “first redistribution structure 402 may be wider or thicker than the conductive lines and/or vias of the metallization patterns of the second redistribution structure 408”) have a first characteristic line width and the second set of metal lines (402 – Fig. 18 – [0056] – “first redistribution structure 402 may be wider or thicker than the conductive lines and/or vias of the metallization patterns of the second redistribution structure 408”) have a second characteristic line width, and wherein the first characteristic line width is greater than the second characteristic line width ([0056] – “first redistribution structure 402 may be wider or thicker than the conductive lines and/or vias of the metallization patterns of the second redistribution structure 408”).
Regarding claim 23, Wu as modified by Ting, teaches claim 14 from which claim 23 depends. Wu further teaches
(Original) The device of claim 14, wherein the first set of metal layers
(402 – Fig. 18 – [0056] – “first redistribution structure 402 may be wider or thicker than the conductive lines and/or vias of the metallization patterns of the second redistribution structure 408”) have a first characteristic layer thickness and the second set of metal layers (402 – Fig. 18 – [0056] – “first redistribution structure 402 may be wider or thicker than the conductive lines and/or vias of the metallization patterns of the second redistribution structure 408”) have a second characteristic layer thickness, and wherein the first characteristic layer thickness is greater than the second characteristic layer thickness ([0056] – “first redistribution structure 402 may be wider or thicker than the conductive lines and/or vias of the metallization patterns of the second redistribution structure 408”).
Regarding claim 24, Wu as modified by Ting, teaches claim 14 from which claim 24 depends. Wu further teaches
(Original) The device of claim 14, wherein the first set of dielectric
layers have a first characteristic thickness and the second set of dielectric layers have a second characteristic thickness, and wherein the first characteristic thickness is greater than the second characteristic thickness ([0055] – “one or more of the dielectric layers of the second redistribution structure 408 may have a different thickness than other dielectric layers of the second redistribution structure 408”).
Regarding claim 25, Wu as modified by Ting, teaches claim 14 from which claim 25 depends. Wu further teaches
(Original) The device of claim 14, further comprising a plurality of
solder balls electrically connected to the second contacts (205F – Fig. 8 – [0036] –“conductive lines 205F” – this is a contact) to form a ball grid array ([0038] – “conductive connectors 212 may be ball grid array (BGA) connectors, solder balls”) configured to be coupled to the one or more off-package devices (500).
Claims 3, 5,16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Ting and Liu et al. (US 20150028486 A1 – hereinafter Liu).
Regarding claim 3, Wu as modified by Ting, teaches claim 1 from which claim 3 depends. Wu and Ting do not expressly disclose the limitations of claim 3.
However, in an analogous art, Liu teaches
(Original) The device of claim 1, wherein two or more dielectric layers (104a
– {Fig. 3a – [0032] – “electrically insulative material (hereinafter "dielectric 104a") of a build-up layer (e.g., N-2 layer)”}, {104a – Fig. 3i – [0041] – “build-up layer (e.g., N-1 layer) composed of dielectric 104a”} – this is two dielectric layers) of the second
set of dielectric layers are disposed between the first side of the substrate (S1 – Fig. 1 – [0019] – “first side S1 of the package substrate 104”) and the first set of metal layers (104b – Fig. 1 – [0022] – “conductive layer 104b” – this corresponds to a metal layer).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the dielectric layer structure as taught by Liu into Wu and Ting.
An ordinary artisan would have been motivated to use the known technique of Liu in the manner set forth above to produce the predictable results [0001] - to interconnect structures for embedded bridge, in integrated circuit (IC) package assemblies.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 5, Wu as modified by Ting, teaches claim 1 from which claim 5 depends. Wu and Ting do not expressly disclose the limitations of claim 5.
However, in an analogous art, Liu teaches
(Original) The device of claim 1, further comprising a two-layer post structure (Fig. 1 annotated, see below, shows this – hereinafter ‘2LP’) that
includes one of the first contacts (104b – Fig. 1 – [0022] – “conductive layer 104b” – this corresponds to a contact) and a one-layer post structure (Fig. 1 annotated, see below, shows this – hereinafter ‘1LP’) that includes a via structure (103a – Fig. 1 – [0021] – “pillars 103a” – this corresponds to a via structure) and one of the third contacts (105a – Fig. 1 – [0021] – “contacts 105a”).
PNG
media_image2.png
478
866
media_image2.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the layer post structure as taught by Liu into Wu and Ting.
An ordinary artisan would have been motivated to use the known technique of Liu in the manner set forth above to produce the predictable results as stated above in claim 3.
Regarding claim 16, Wu as modified by Ting, teaches claim 14 from which claim 16 depends. Wu and Ting do not expressly disclose the limitations of claim 16.
However, in an analogous art, Liu teaches
(Original) The device of claim 14, wherein two or more dielectric layers
(104a – {Fig. 3a – [0032] – “electrically insulative material (hereinafter "dielectric 104a") of a build-up layer (e.g., N-2 layer)”}, {104a – Fig. 3i – [0041] – “build-up layer (e.g., N-1 layer) composed of dielectric 104a”} – this is two dielectric layers) of the second
set of dielectric layers are disposed between the first side of the substrate (S1 – Fig. 1 – [0019] – “first side S1 of the package substrate 104”) and the first set of metal layers (104b – Fig. 1 – [0022] – “conductive layer 104b” – this corresponds to a metal layer).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the dielectric layer structure as taught by Liu into Wu and Ting.
An ordinary artisan would have been motivated to use the known technique of Liu in the manner set forth above to produce the predictable results as stated above in claim 3.
Regarding claim 18, Wu as modified by Ting, teaches claim 14 from which claim 18 depends. Wu and Ting do not expressly disclose the limitations of claim 18.
However, in an analogous art, Liu teaches
(Original) The device of claim 14, further comprising a two-layer post
structure (Fig. 1 annotated, see below, shows this – hereinafter ‘2LP’) that
includes one of the first contacts (104b – Fig. 1 – [0022] – “conductive layer 104b” – this corresponds to a contact) and a one-layer post structure (Fig. 1 annotated, see below, shows this – hereinafter ‘1LP’) that includes a via structure (103a – Fig. 1 – [0021] – “pillars 103a” – this corresponds to a via structure) and one of the third contacts (105a – Fig. 1 – [0021] – “contacts 105a”).
PNG
media_image2.png
478
866
media_image2.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the layer post structure as taught by Liu into Wu and Ting.
An ordinary artisan would have been motivated to use the known technique of Liu in the manner set forth above to produce the predictable results as stated above in claim 3.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Ting and Cheng et al. (US 20230026676 A1 – hereinafter Cheng).
Regarding claim 26, Wu as modified by Ting, teaches claim 14 from which claim 26 depends. Wu and Ting do not expressly disclose the limitations of claim 26.
However, in an analogous art, Cheng teaches
(Original) The device of claim 14, wherein the first die is a first chiplet (104
– Fig. 1 – [0023] – “chiplet 104”) and the second die is a second chiplet (106 – Fig. 1 – [0023] – “chiplet 106”) designed to operate in conjunction ([0026] – “The one or more inter-chiplet connectors 110 are configured to allow the different types of integrated chip devices to operate together to perform a function”) with the first chiplet (104).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the chiplet operating structure as taught by Cheng into Wu and Ting.
An ordinary artisan would have been motivated to use the known technique of Cheng in the manner set forth above to produce the predictable results [0002] – “By reducing the minimum feature size on an integrated chip, the performance of individual devices on the integrated chip (e.g., the power consumption, speed, etc.) can be improved.”
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Ting, Cheng, and Black et al. (US 20050127490 A1 – hereinafter Black).
Regarding claim 27, Wu as modified by Ting and Cheng, teaches claim 26 from which claim 27 depends. Wu and Ting do not expressly disclose the limitations of claim 27.
However, in an analogous art, Cheng teaches
(Original) The device of claim 26, wherein the first circuitry of the first
chiplet includes one or more first functional circuit blocks (104 – [0024] – “chiplet 104 may predominantly comprise a second plurality of integrated chip devices that are a second type of integrated chip device (e.g., a PMOS transistor)”) and the second circuitry of the second chiplet includes one or more second functional circuit blocks (106 – [0025] – “chiplet 106 may predominately comprise passive devices (e.g., inductors, capacitors, resistors, or the like)”), and wherein the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent upon one.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the chiplet operating structure as taught by Cheng into Wu and Ting.
An ordinary artisan would have been motivated to use the known technique of Cheng in the manner set forth above to produce the predictable results as stated above in claim 26.
Wu, Ting, and Cheng do not expressly disclose the limitations of claim 27.
However, in an analogous art, Black teaches
wherein the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent upon one another ([0063] – “The logic portions may be allocated among the multiple dice such that certain functions are split. That is, address generation unit logic may be split into a first portion and a second portion, with the first portion being allocated to a first die and a second portion being allocated to a second die. The first and second logic portions may at least partially overlap and may act together to cooperatively perform the operations of an address generation unit” – this describes dependency on one another).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the chiplet dependent operating structure as taught by Black into Wu, Ting, and Cheng.
An ordinary artisan would have been motivated to use the known technique of Black in the manner set forth above to produce the predictable results of [0005] – “Multichip modules (MCM) are IC packages that can contain two or more "bare" or unpackaged integrated circuit dice interconnected on a common substrate. The size of the electronic device that uses MCMs can be reduced because MCMs typically have a number of individual IC dice mounted within a single package in a laterally adjacent manner.”
Claim 28-30 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin et al. (US 20210202394 A1 – hereinafter Lin) in view of Ecton et al. (US 20240079334 A1 – hereinafter Ecton).
Regarding independent claim 28, Lin teaches:
(Original) A method of fabrication ([0026] – “the formation of a first
feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact” – this is fabrication) , the method comprising:
obtaining a first set of layers (110 – [0028] – “first substrate 110”), the first set of layers comprising:
a first set of metal layers (113 – [0028] – “first substrate 110 has dielectric layers 112, circuit layers 113 and conductive vias 114”) separated from one another by a first set of dielectric layers (112 – [0028] – “first substrate 110 has dielectric layers 112, circuit layers 113 and conductive vias 114”), the first set of metal layers (113) defining a first set of metal lines (Fig. 1D – 123 includes metal lines); and
a first set of conductive vias (114 – [0028] – “first substrate 110 has dielectric layers 112, circuit layers 113 and conductive vias 114”) through the first set of dielectric layers (112) to
interconnect the first set of metal lines ([0028] – “first substrate 110 has dielectric layers 112, circuit layers 113 and conductive vias 114” – this describes the limitations of the first set of layers);
forming an embedded interconnect structure on the first set of layers, the embedded interconnect structure comprising:
a second set of metal layers defining a second set of metal lines, wherein
at least one metal layer of the second set of metal layers is devoid of
metal lines of the first set of metal lines; and
a second set of dielectric layers including at least a bottom dielectric layer between the first set of metal layers and the second set of metal layers and a top dielectric layer on a top metal layer of the second set of metal layers;
forming first pads and first conductive vias, the first conductive vias extending through the embedded interconnect structure to the first set of metal layers; and
forming first contacts on the first pads and second contacts that include via portions that extend through the top dielectric layer of the embedded interconnect structure to the top metal layer of the second set of metal layers.
Lin do not expressly disclose the other limitations of claim 28.
However, in an analogous art, Ecton teaches
forming an embedded interconnect structure (322 – Fig. 3 – [0038] – “interconnect bridge 322 embedded”) on the first set of layers (307b – Fig. 3 – [0038] – “build-up layers 307a-307d”), the
embedded interconnect structure (322) comprising:
a second set of metal layers defining a second set of metal lines (350 – Fig. 3 – [0043] – “interconnect bridge 322 may include electrically conductive structures 350”), wherein
at least one metal layer (360a – Fig. 3 – [0047] – “Bridge sublayer 360a i
ncludes the interconnect bridge 322. Bridge 322 includes a non-conductive material 351 within which electrically conductive structures 350 and any bridge devices 352 are embedded”) of the second set of metal layers (360 – Fig. 3 – [0044] – “Interconnect bridge 322 is part of a bridge layer 360 which may include a first bridge sublayer 360a, and a second bridge sublayer 360b”) is devoid of metal lines ([0047] – “Bridge 322 includes a non-conductive material 351 within which electrically conductive structures 350 and any bridge devices 352 are embedded” – Fig. 3 shows this) of the first set of metal lines (336 – Fig. 3 – [0040] – “The buildup layers may further include a non-conductive material 311 within which the traces 336 and vias 340 may be embedded” – this corresponds to metal lines); and
a second set of dielectric layers (360b and 351 – Fig. 3 – {[0044] – “One or more of bridge sublayers 360a or 360b may include glass, such as a silicon oxide, a silicon dioxide or a borosilicate glass material”}, {[0047] – “Bridge 322 includes a non-conductive material 351”}) including at least a bottom dielectric layer (360b) between the first set of metal layers (307b) and the second set of metal layers (360a) and a top dielectric layer (351) on a top metal layer of the second set of metal layers (350);
forming first pads (210 – Fig. 2 – [0034] – “the substrate conductive contacts 210”) and first conductive vias (240 – Fig. 2 – [0034] – “vias 240”), the first conductive vias (362 – Fig. 3 – [0044] – “bridge layer 360 includes electrically conductive TGVs 362 extending therethrough, and in registration with vias 327”) extending through the embedded interconnect structure (322) to the first set of metal layers (307b); and
forming first contacts (256 – Fig. 2 – [0031] – “contact structures or joints 256 connecting”) on the first pads (210”) and second contacts (224 – Fig. 2 – [0034] – “conductive contacts 224”) that include via portions (232 – Fig. 2 – [0034] – “Bridge vias 232”) that extend through the top dielectric layer of the embedded interconnect structure (222 – Fig. 2 [0031] – “interconnect bridge 222 embedded within a package substrate 204”) to the top metal layer of the second set of metal layers (236 – Fig. 2 – [0034] – “bridge conductive traces 236”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the embedded interconnect structure as taught by Ecton into Lin.
An ordinary artisan would have been motivated to use the known technique of Ecton in the manner set forth above to produce the predictable results [0002] – “of a silicon bridge structure for an advanced package interconnect regime includes, for example, and embedded multi-die interconnect bridge (EMIB), or a chip-on-wafer-on-substrate (CoWoS).”
Regarding claim 29, Lin as modified by Ecton, teaches claim 28 from which claim 29 depends. Lin does not expressly disclose the limitations of claim 29.
However, in an analogous art, Ecton teaches
(Original) The method of claim 28, further comprising electrically
connecting a first die (308 – Fig. 5 – [0040] – “die 308”) to a second die (316 – Fig. 5 – [0040] – “die 316”) through the second contacts (326 – Fig. 5 – [0040] – “conductive contacts 326 coupled to die 306 to at least one conductive contact of the second set of conductive contacts 326 coupled to die 318” – this is interpreted as a typo and should be either 308 or 316) and the embedded interconnect (322).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the embedded interconnect structure as taught by Ecton into Lin.
An ordinary artisan would have been motivated to use the known technique of Ecton in the manner set forth above to produce the predictable results as stated above in claim 28.
Regarding claim 30, Lin as modified by Ecton, teaches claim 28 from which claim 30 depends. Lin does not expressly disclose the limitations of claim 30.
However, in an analogous art, Ecton teaches
(Original) The method of claim 28, wherein the embedded interconnect
structure (322) is disposed within a die-to-die interconnect region (360 – Fig. 5 – [0044] – “Interconnect bridge 322 is part of a bridge layer 360 which may include a first bridge sublayer 360a, and a second bridge sublayer 360b” – this corresponds to the interconnect region), and wherein no metal line ([0044] – “One or more of bridge sublayers 360a or 360b may include glass, such as a silicon oxide, a silicon dioxide or a borosilicate glass material”) of the first set of metal lines (336 – fig. 5 – [0048] – “electrically conductive structures such as traces 336” – these are metal lines) traverses the die-to-die interconnect region (360 – Fig. 5 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the embedded interconnect structure as taught by Ecton into Lin.
An ordinary artisan would have been motivated to use the known technique of Ecton in the manner set forth above to produce the predictable results as stated above in claim 28.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and ttps://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights