DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-7, 10-11, 14-17 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng (US 2021/0375698).
Re: independent claim 1, Cheng discloses in figs. 1A-1E an integrated circuit (IC) device, comprising: a substrate (106) ; an N-type field effect transistor (FET) (102N1) comprising an N-type vertical structure on the substrate and including an N-type gate region (112N) having a first normal-k oxide layer (127, [0029]) on a semiconductor layer (108N) of the N-type vertical structure, an N-type work-function metal (WFM) layer (130) on the first normal-k oxide layer (127) and sidewall spacers (114) of the N-type gate region, and a first metal gate (138N) on the N-type WFM layer; and a first P-type FET (102P1), comprising a first P-type vertical structure on the substrate and including a first P-type gate region (112P) having a second normal-k oxide layer (127, [0029]) on a first semiconductor layer of the first P-type vertical structure, a first P-type WFM layer (136P, [0035]) on the second normal-k oxide layer and sidewall spacers (114) of the first P-type gate region, and a second metal gate (138P) on the first P-type WFM layer.
Re: claim 4, Cheng discloses in figs. 1A-1E the IC device of claim 1, further comprising a second P-type FET (102P2), comprising a second P-type vertical structure on the substrate, and including a second P-type gate region having a high-k gate oxide layer (127, [0029]) on a second semiconductor layer (122P) of the second P-type vertical structure and sidewall spacers (116) of the second P-type gate region.
Re: claim 5, Cheng discloses in figs. 1A-1E the IC device of claim 4, in which the second P-type FET (102P2) further comprises a second P-type WFM layer (136P) on the high-k gate oxide layer (127), and a third metal gate (138P) on the second P-type WFM layer.
Re: claim 6, Cheng discloses in figs. 1A-1E the IC device of claim 4, in which the high-k gate oxide layer (127) is on a surface of the substrate (fig. 1E).
Re: claim 7, Cheng discloses in figs. 1A-1E the IC device of claim 1, in which the first normal-k oxide layer (127) and the second normal-k oxide layer (127) are on a surface of the substrate (106).
Re: claim 10, Cheng discloses in figs. 1A-1E the IC device of claim 1, further comprising an input/output (IO) pad (140) coupled to at least one of a source/drain region of the N-type FET and a drain/source region of the first P-type FET.
Re: independent claim 11, Cheng discloses in figs. 1A-1E a method for fabricating an integrated circuit device, comprising: forming an N-type vertical structure on a substrate (106) and including an N-type gate region (112N) and a first P-type vertical structure on the substrate and including a first P-type gate region (112P); growing a first normal-k oxide layer (127, [0029], [0054]) on a first semiconductor layer (108N) of the N-type vertical structure, and a second normal-k oxide layer (127, [0029] , [0054]) on a second semiconductor layer (108P) of the first P-type vertical structure; depositing an N-type work-function metal (WFM) layer (130) on the first normal-k oxide layer and sidewall spacers (114) of the N-type gate region; depositing a first P-type WFM layer (136P) on the second normal-k oxide layer and sidewall spacers (114) of the first P-type gate region; and forming a first metal gate (138N) on the N-type WFM layer and a second metal gate (138P) on the first P-type WFM layer to from an N-type field effect transistor (FET) (102N1) and a first P-type FET (102P1).
Re: claim 14, see claim 4 rejection above.
Re: claim 15, see claim 5 rejection above
Re: claim 16, see claim 6 rejection above.
Re: claim 17, see claim 7 rejection above.
Re: claim 20, see claim 10 rejection above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 8-9, 12-13 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US 2021/0375698) in view of Chanemougame et al. (US 2020/0083352) (hereinafter, “Chanemougame”).
Re: claim 2, Cheng discloses in figs. 1A-1E the IC device of claim 1.
Cheng does not expressly disclose wherein the N-type vertical structure comprises a P-type nanosheet structure.
Chanemougame discloses wherein an N-type vertical structure comprises a P-type nanosheet structure [0051].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the channels of the N-type vertical structure of P-type nanosheets since it is common and well known in the art that N-type transistors have P-type channel regions and N-type source/drain regions.
Re: claim 3, Cheng discloses in figs. 1A-1E the IC device of claim 1.
Cheng does not disclose expressly wherein the first P-type vertical structure comprises an N-type nanosheet structure.
Chanemougame discloses wherein a first P-type vertical structure comprises an N-type nanosheet structure [0051].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the channels of the P-type vertical structure of N-type nanosheets since it is common and well known in the art that P-type transistors have N-type channel regions and P-type source/drain regions.
Re: claim 8, Cheng discloses the IC device of claim 1.
Cheng does not disclose expressly wherein the N-type vertical structure comprises a lightly doped P-type channel region between a source/drain region and a drain/source region.
Chanemougame discloses wherein an N-type vertical structure comprises a P-type channel region between a source/drain region and a drain/source region [0051].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the channels of the N-type vertical structure of P-type nanosheets since it is common and well known in the art that N-type transistors have P-type channel regions and N-type source/drain regions.
Additionally, these limitations would have been obvious to one of ordinary skill in the art at the time of the invention since it has been held that claimed ranges of a result effective variable are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art. In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). These claims are prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA 1980) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious). See MPEP § 2144.05.
Re: claim 9, Cheng discloses the IC device of claim 1.
Cheng does not disclose expressly wherein the first P-type vertical structure comprises a lightly doped N-type channel region between a source/drain region and a drain/source region.
Chanemougame discloses wherein a first P-type vertical structure comprises an N-type channel region between a source/drain region and a drain/source region [0051].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the channels of the P-type vertical structure of N-type nanosheets since it is common and well known in the art that P-type transistors have N-type channel regions and P-type source/drain regions.
Additionally, these limitations would have been obvious to one of ordinary skill in the art at the time of the invention since it has been held that claimed ranges of a result effective variable are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art. In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). These claims are prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA 1980) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious). See MPEP § 2144.05.
Re: claim 12, see claim 2 rejection above.
Re: claim 13, see claim 3 rejection above.
Re: claim 18, see claim 8 rejection above.
Re: claim 19, see claim 9 rejection above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liaw US 2021/0057281 teaches a gate insulating layer that can be silicon oxide or a high-k material.
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 10/29/2025