Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on 20 May 2026, U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6, 11, 12, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over US20230267250A1 (Ma) in view of US20230195986A1 (Cao) and US20220230095A1 (Stergioudis).
In regards to claim 1 (Ma) shows A computer-implemented method for circuit generation, comprising:
generating a circuit design; Ma [0038] and [0039] teach generating a circuit design by using a reinforcement learning agent to generate device parameters for the circuit and outputting the resulting circuit design.
Ma differs from the claimed invention in that it does not explicitly disclose extracting paths from the circuit design, with the paths representing sequences of connected circuit components from one terminal of the circuit to another; embedding the extracted paths as respective vectors in a latent space; determining a property of the circuit design using a model that accepts a sequence of the vectors as input; wherein the property is determined using an ensemble of trained surrogate models;
Cao teaches extracting paths from the circuit design, with the paths representing sequences of connected circuit components from one terminal of the circuit to another; Cao [0033] teaches extracting topology information including a cell type, a cell size, and a corresponding load capacitance sequence of a path of the circuit, the path representing a sequence of connected cells from one terminal of the circuit to another.
Cao teaches embedding the extracted paths as respective vectors in a latent space; Cao [0042] teaches inputting padded path sequences into an embedding layer to obtain a vector representation of each element of the path.
Cao teaches determining a property of the circuit design using a model that accepts a sequence of the vectors as input; Cao [0045] teaches inputting the embedded sequence of vectors into a bi-directional long short-term memory neural network to determine a property of the path.
Cao differs from the claimed invention in that it does not explicitly disclose that the determining of the property uses an ensemble of trained surrogate models.
Stergioudis teaches wherein the property is determined using an ensemble of trained surrogate models; Stergioudis [0030] and [0101] teach determining a result using an ensemble of trained surrogate models in a query-by-committee arrangement in which a committee of models generates predictions.
The motivation to combine Ma and Cao at the effective filing date of the invention is to evaluate a generated circuit design without performing a full simulation.
The motivation to combine Ma, Cao, and Stergioudis at the effective filing date of the invention is to improve prediction accuracy and quantify uncertainty using an ensemble of models.
In regards to claim 4 (Ma) shows the method of claim 1:
wherein determining the property of the circuit design includes determining at least one of an efficiency and an output voltage; Ma [0039] and [0062] teach determining at least one of a power efficiency and an output power of the circuit.
In regards to claim 5 (Ma modified by Cao) does not show: determining that the circuit design is a new circuit design based on an uncertainty of the trained surrogate models;
Stergioudis teaches determining that the circuit design is a new circuit design based on an uncertainty of the trained surrogate models; Stergioudis [0029], [0097], and [0101] teach determining, based on an uncertainty of the trained models, that a sample is a new sample selected from an unlabeled pool for labeling.
The motivation to combine Ma, Cao, and Stergioudis at the effective filing date of the invention is to identify circuit designs about which the surrogate models are uncertain so that those designs may be selected for further evaluation.
In regards to claim 6 (Ma) shows the method of claim 5:
simulating the new circuit design to determine a ground truth property of the new circuit design; Ma [0051] teaches a circuit simulator that simulates a netlist of the circuit to obtain a ground truth specification of the circuit.
Ma and Cao differ from the claimed invention in that it does not explicitly disclose updating the surrogate models using the ground truth property;
Stergioudis teaches updating the surrogate models using the ground truth property; Stergioudis [0029] and [0122] teach providing the selected sample to an oracle to obtain ground truth data and retraining the models using the ground truth data.
The motivation to combine Ma, Cao, and Stergioudis at the effective filing date of the invention is to improve prediction accuracy and quantify uncertainty using an ensemble of models.
In regards to claim 11 (Ma) shows:
A computer program product for circuit generation, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions being executable by a hardware processor to cause the hardware processor to; Ma [0068] and [0069] teach a computer readable storage medium storing program instructions executable by a hardware processor to cause the hardware processor to perform the recited operations.
generate a circuit design; Ma [0038] and [0039] teach generating a circuit design by using a reinforcement learning agent to generate device parameters for the circuit and outputting the resulting circuit design.
Ma differs from the claimed invention in that it does not explicitly disclose extract paths from the circuit design, with the paths representing sequences of connected circuit components from one terminal of the circuit to another; embed the extracted paths as respective vectors in a latent space; determine a property of the circuit design using a model that accepts a sequence of the vectors as input; wherein the property is determined using an ensemble of trained surrogate models;
Cao teaches extract paths from the circuit design, with the paths representing sequences of connected circuit components from one terminal of the circuit to another; Cao [0033] teaches extracting topology information including a cell type, a cell size, and a corresponding load capacitance sequence of a path of the circuit, the path representing a sequence of connected cells from one terminal of the circuit to another.
Cao teaches embed the extracted paths as respective vectors in a latent space; Cao [0042] teaches inputting padded path sequences into an embedding layer to obtain a vector representation of each element of the path.
Cao teaches determine a property of the circuit design using a model that accepts a sequence of the vectors as input; Cao [0045] teaches inputting the embedded sequence of vectors into a bi-directional long short-term memory neural network to determine a property of the path.
Cao differs from the claimed invention in that it does not explicitly disclose that the determining of the property uses an ensemble of trained surrogate models.
Stergioudis teaches wherein the property is determined using an ensemble of trained surrogate models; Stergioudis [0030] and [0101] teach determining a result using an ensemble of trained surrogate models in a query-by-committee arrangement in which a committee of models generates predictions.
The motivation to combine Ma and Cao at the effective filing date of the invention is to evaluate a generated circuit design without performing a full simulation.
The motivation to combine Ma, Cao, and Stergioudis at the effective filing date of the invention is to improve prediction accuracy and quantify uncertainty using an ensemble of models.
In regards to claim 12 (Ma) shows:
A system for circuit generation, comprising: a hardware processor; and a memory that stores a computer program which, when executed by the hardware processor, causes the hardware processor to; Ma [0068] and [0069] teach a system comprising a hardware processor and a memory storing a computer program that, when executed by the hardware processor, causes the hardware processor to perform the recited operations.
generate a circuit design; Ma [0038] and [0039] teach generating a circuit design by using a reinforcement learning agent to generate device parameters for the circuit and outputting the resulting circuit design.
Ma differs from the claimed invention in that it does not explicitly disclose extract paths from the circuit design, with the paths representing sequences of connected circuit components from one terminal of the circuit to another; embed the extracted paths as respective vectors in a latent space; determine a property of the circuit design using a model that accepts a sequence of the vectors as input; wherein the property is determined using an ensemble of trained surrogate models;
Cao teaches extract paths from the circuit design, with the paths representing sequences of connected circuit components from one terminal of the circuit to another; Cao [0033] teaches extracting topology information including a cell type, a cell size, and a corresponding load capacitance sequence of a path of the circuit, the path representing a sequence of connected cells from one terminal of the circuit to another.
Cao teaches embed the extracted paths as respective vectors in a latent space; Cao [0042] teaches inputting padded path sequences into an embedding layer to obtain a vector representation of each element of the path.
Cao teaches determine a property of the circuit design using a model that accepts a sequence of the vectors as input; Cao [0045] teaches inputting the embedded sequence of vectors into a bi-directional long short-term memory neural network to determine a property of the path.
Cao differs from the claimed invention in that it does not explicitly disclose that the determining of the property uses an ensemble of trained surrogate models.
Stergioudis teaches wherein the property is determined using an ensemble of trained surrogate models; Stergioudis [0030] and [0101] teach determining a result using an ensemble of trained surrogate models in a query-by-committee arrangement in which a committee of models generates predictions.
The motivation to combine Ma and Cao at the effective filing date of the invention is to evaluate a generated circuit design without performing a full simulation.
The motivation to combine Ma, Cao, and Stergioudis at the effective filing date of the invention is to improve prediction accuracy and quantify uncertainty using an ensemble of models.
In regards to claim 15 (Ma) shows the system of claim 12:
determine at least one of an efficiency and an output voltage as the property; Ma [0039] and [0062] teach determining at least one of a power efficiency and an output power of the circuit.
In regards to claim 16 (Ma modified by Cao) does not show: determine that the circuit design is a new circuit design based on an uncertainty of the trained surrogate models;
Stergioudis teaches determine that the circuit design is a new circuit design based on an uncertainty of the trained surrogate models; Stergioudis [0029], [0097], and [0101] teach determining, based on an uncertainty of the trained models, that a sample is a new sample selected from an unlabeled pool for labeling.
The motivation to combine Ma, Cao, and Stergioudis at the effective filing date of the invention is to identify circuit designs about which the surrogate models are uncertain so that those designs may be selected for further evaluation.
In regards to claim 17 (Ma) shows the system of claim 16:
simulate the new circuit design to determine a ground truth property of the new circuit design; Ma [0051] teaches a circuit simulator that simulates a netlist of the circuit to obtain a ground truth specification of the circuit.
Ma and Cao differ from the claimed invention in that it does not explicitly disclose update the surrogate models using the ground truth property;
Stergioudis teaches update the surrogate models using the ground truth property; Stergioudis [0029] and [0122] teach providing the selected sample to an oracle to obtain ground truth data and retraining the models using the ground truth data.
The motivation to combine Ma, Cao, and Stergioudis at the effective filing date of the invention is to improve prediction accuracy and quantify uncertainty using an ensemble of models.
Claims 2, 3, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over US20230267250A1 (Ma) in view of US20230195986A1 (Cao) and US20220230095A1 (Stergioudis) as applied to claims 1 and 12 above, and further in view of US20180032864A1 (Graepel).
In regards to claim 2 (Ma modified by Cao and Stergioudis) does not show: wherein generating the circuit design uses an upper confidence bound applied to trees (UCT) search;
Graepel teaches wherein generating the circuit design uses an upper confidence bound applied to trees (UCT) search; Graepel [0104] teaches selecting actions to be performed by an agent by traversing a state tree in a Monte Carlo tree search, and Graepel [0107] teaches computing an adjusted action score for an edge by adding a bonus that is proportional to a prior probability and decays with repeated visits to encourage exploration, thereby applying an upper confidence bound to the tree search.
The motivation to combine Ma, Cao, Stergioudis, and Graepel at the effective filing date of the invention is to use a known tree-search technique to explore the space of candidate circuit designs while balancing exploration and exploitation.
In regards to claim 3 (Ma) shows the method of claim 2:
wherein generating the circuit design further constrains generated circuit designs according to a design rule; Ma [0057] teaches constraining the generated circuit such that two transistors in a differential pair, and the devices in each driver stage, preserve the same parameters as practical constraints imposed by the circuit design.
In regards to claim 13 (Ma modified by Cao and Stergioudis) does not show: using an upper confidence bound applied to trees (UCT) search to generate the circuit design;
Graepel teaches using an upper confidence bound applied to trees (UCT) search to generate the circuit design; Graepel [0104] teaches selecting actions to be performed by an agent by traversing a state tree in a Monte Carlo tree search, and Graepel [0107] teaches computing an adjusted action score for an edge by adding a bonus that is proportional to a prior probability and decays with repeated visits to encourage exploration, thereby applying an upper confidence bound to the tree search.
The motivation to combine Ma, Cao, Stergioudis, and Graepel at the effective filing date of the invention is to use a known tree-search technique to explore the space of candidate circuit designs while balancing exploration and exploitation.
In regards to claim 14 (Ma) shows the system of claim 13:
constrain generated circuit designs according to a design rule; Ma [0057] teaches constraining the generated circuit such that two transistors in a differential pair, and the devices in each driver stage, preserve the same parameters as practical constraints imposed by the circuit design.
Claims 9, 10, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US20230267250A1 (Ma) in view of US20230195986A1 (Cao) and US20220230095A1 (Stergioudis) as applied to claims 1 and 12 above, and further in view of US20230004701A1 (Mahmud).
In regards to claim 9 (Ma modified by Cao and Stergioudis) does not show: evaluating a fitness of the circuit design for an intended purpose based on the property;
Mahmud teaches evaluating a fitness of the circuit design for an intended purpose based on the property; Mahmud [0031] teaches assessing the predicted property of the design against predefined goals to determine whether the design is fit for its intended purpose.
The motivation to combine Ma, Cao, Stergioudis, and Mahmud at the effective filing date of the invention is to fabricate only those circuit designs that are predicted to meet their performance goals.
In regards to claim 10 (Ma modified by Cao and Stergioudis) does not show: fabricating the circuit design responsive to determining that the circuit design is fit for the intended purpose;
Mahmud teaches fabricating the circuit design responsive to determining that the circuit design is fit for the intended purpose; Mahmud [0032] and [0033] teach fabricating the integrated circuit responsive to the predicted property meeting the predefined goals.
The motivation to combine Ma, Cao, Stergioudis, and Mahmud at the effective filing date of the invention is to fabricate only those circuit designs that are predicted to meet their performance goals.
In regards to claim 20 (Ma modified by Cao and Stergioudis) does not show: evaluate a fitness of the circuit design for an intended purpose based on the property; and to fabricate the circuit design responsive to determining that the circuit design is fit for the intended purpose;
Mahmud teaches evaluate a fitness of the circuit design for an intended purpose based on the property; Mahmud [0031] teaches assessing the predicted property of the design against predefined goals to determine whether the design is fit for its intended purpose.
Mahmud teaches and to fabricate the circuit design responsive to determining that the circuit design is fit for the intended purpose; Mahmud [0032] and [0033] teach fabricating the integrated circuit responsive to the predicted property meeting the predefined goals.
The motivation to combine Ma, Cao, Stergioudis, and Mahmud at the effective filing date of the invention is to fabricate only those circuit designs that are predicted to meet their performance goals.
Claims 7, 8, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US20230267250A1 (Ma) in view of US20230195986A1 (Cao) and US20220230095A1 (Stergioudis) as applied to claims 1 and 12 above, and further in view of US20190303795A1 (Khiari), US20180018575A1 (Baughman), and US20190101908A1 (Park).
In regards to claim 7 (Ma modified by Cao and Stergioudis) does not show: generating predictions by the surrogate models; identifying an interval for each of the predictions; calculating a mean of predictions in an interval that is selected most by the surrogate models as the property;
Khiari teaches generating predictions by the surrogate models; Khiari [0085] teaches that each model of the ensemble makes a prediction and that the predictions are aggregated to generate an output that is an average, that is, a mean, of the predictions.
Khiari differs from the claimed invention in that it does not explicitly disclose identifying an interval for each of the predictions; calculating a mean of predictions in an interval that is selected most by the surrogate models as the property;
Baughman teaches identifying an interval for each of the predictions; Baughman [0083] teaches determining a pair of thresholds within which a value lies, thereby identifying an interval for each prediction.
Baughman differs from the claimed invention in that it does not explicitly disclose calculating a mean of predictions in an interval that is selected most by the surrogate models as the property;
Park teaches calculating a mean of predictions in an interval that is selected most by the surrogate models as the property; Park [0055] and [0071] teach a bagging method by a majority vote among the models, so that the group of predictions selected by the most models is identified as the property.
The motivation to combine Ma, Cao, Stergioudis, and Khiari at the effective filing date of the invention is to aggregate the predictions of the ensemble of models to generate the property.
The motivation to combine Ma, Cao, Stergioudis, Khiari, and Baughman at the effective filing date of the invention is to assign each prediction to an interval so that the predictions can be grouped for selection and aggregation.
The motivation to combine Ma, Cao, Stergioudis, Khiari, Baughman, and Park at the effective filing date of the invention is to aggregate the ensemble predictions by selecting the interval chosen by the most models and computing the mean of the predictions in that interval as the property.
In regards to claim 8 (Ma modified by Cao and Stergioudis) does not show: calculating an uncertainty value as a standard deviation of the predictions in the interval that is selected most by the surrogate models;
Khiari teaches calculating an uncertainty value as a standard deviation of the predictions in the interval that is selected most by the surrogate models; Khiari [0049] teaches descriptive statistics about the predictions including a standard deviation and a mean of the predictions, providing an uncertainty value as the standard deviation of the predictions.
The motivation to combine Ma, Cao, Stergioudis, and Khiari at the effective filing date of the invention is to quantify the uncertainty of the determined property as a standard deviation of the predictions.
In regards to claim 18 (Ma modified by Cao and Stergioudis) does not show: generate predictions by the surrogate models; identify an interval for each of the predictions; calculate a mean of predictions in an interval that is selected most by the surrogate models as the property;
Khiari teaches generate predictions by the surrogate models; Khiari [0085] teaches that each model of the ensemble makes a prediction and that the predictions are aggregated to generate an output that is an average, that is, a mean, of the predictions.
Khiari differs from the claimed invention in that it does not explicitly disclose identify an interval for each of the predictions; calculate a mean of predictions in an interval that is selected most by the surrogate models as the property;
Baughman teaches identify an interval for each of the predictions; Baughman [0083] teaches determining a pair of thresholds within which a value lies, thereby identifying an interval for each prediction.
Baughman differs from the claimed invention in that it does not explicitly disclose calculate a mean of predictions in an interval that is selected most by the surrogate models as the property;
Park teaches calculate a mean of predictions in an interval that is selected most by the surrogate models as the property; Park [0055] and [0071] teach a bagging method by a majority vote among the models, so that the group of predictions selected by the most models is identified as the property.
The motivation to combine Ma, Cao, Stergioudis, and Khiari at the effective filing date of the invention is to aggregate the predictions of the ensemble of models to generate the property.
The motivation to combine Ma, Cao, Stergioudis, Khiari, and Baughman at the effective filing date of the invention is to assign each prediction to an interval so that the predictions can be grouped for selection and aggregation.
The motivation to combine Ma, Cao, Stergioudis, Khiari, Baughman, and Park at the effective filing date of the invention is to aggregate the ensemble predictions by selecting the interval chosen by the most models and computing the mean of the predictions in that interval as the property.
In regards to claim 19 (Ma modified by Cao and Stergioudis) does not show: calculate an uncertainty value as a standard deviation of the predictions in the interval that is selected most by the surrogate models;
Khiari teaches calculate an uncertainty value as a standard deviation of the predictions in the interval that is selected most by the surrogate models; Khiari [0049] teaches descriptive statistics about the predictions including a standard deviation and a mean of the predictions, providing an uncertainty value as the standard deviation of the predictions.
The motivation to combine Ma, Cao, Stergioudis, and Khiari at the effective filing date of the invention is to quantify the uncertainty of the determined property as a standard deviation of the predictions.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANWER AHMED ALAWDI whose telephone number is (703)756-1018. The examiner can normally be reached Monday - Friday 8:00 am - 5:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on (571)-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANWER AHMED ALAWDI/Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
Prosecution Insights