DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2 and 9-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dehganpour et al. (USPN 4,758,743).
With respect to claim 1, Dehganpour et al. discloses, in Fig. 4, a circuit (circuit of Fig. 4 and circuitry in which Fig. 4 is used to drive such as a bit line driver of a memory, see Col. 3 lines 5-6), comprising:
a first transistor device (28) with a first source/drain (S/D) terminal (source; terminal connected to VCC/31) and a second S/D terminal (drain; terminal connected to 51);
a second transistor device (27) with a third S/D terminal (terminal connected to VCC/31) and a fourth S/D terminal (terminal connected 51); and
a resistor device (31) electrically connected between the first and third S/D terminals or between the second and fourth S/D terminals (31 at the terminal of 31 not connected to VCC), wherein the resistor device comprises a terminal directly connected to a reference voltage supply (terminal directly connected to VCC).
With respect to claim 2, the circuit of claim 1, wherein the first transistor device comprises a p-type transistor (28 is PMOS) and the second transistor comprises an n-type transistor (27 is NMOS).
With respect to claim 9, Dehganpour et al. discloses, in Fig. 4, a circuit (circuit of Fig. 4 and circuitry in which Fig. 4 is used to drive such as a bit line driver of a memory, see Col. 3 lines 5-6), comprising:
a first transistor device (28) with a first source/drain (S/D) terminal (terminal connected to 31/VCC) and a second S/D terminal (terminal connected to 51);
a second transistor device (27) with a third S/D terminal (terminal connected to 31/VCC) and a fourth S/D terminal (terminal connected to 51),
wherein the third S/D terminal is electrically connected to the first S/D terminal (at 31) and the fourth S/D terminal is electrically connected to the second S/D terminal (at 51); and
a resistor device (31) comprising:
a first terminal directly electrically connected to the first and third S/D terminals (terminal of 31 not directly connected VCC); and
a second terminal directly connected to a reference voltage supply (terminal of 31 directly connected to VCC).
With respect to claim 10, the circuit of claim 9, wherein the first transistor device comprises a p-type transistor (28 is PMOS) and the second transistor comprises an n-type transistor (27 is NMOS).
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jin (USPN 10,911,044).
With respect to claim 1, Jin discloses, in Figs. 2 and 6, a circuit (circuit of Fig. 2 details of 60 of Fig. 2 disclosed in Fig. 6), comprising:
a first transistor device (M5 of Fig. 6) with a first source/drain (S/D) terminal (terminal connected to EVDD) and a second S/D terminal (terminal connected to MPUb);
a second transistor device (M6) with a third S/D terminal (terminal connected to EVDD) and a fourth S/D terminal (terminal connected MPUb); and
a resistor device (R2) electrically connected between the first and third S/D terminals or between the second and fourth S/D terminals (terminal of R2 directly connected to EVDD is connected between the first and third S/D terminals), wherein the resistor device comprises a terminal directly connected to a reference voltage supply (terminal directly connected to EVDD).
With respect to claim 3, the circuit of claim 1, wherein the terminal of the resistor device is directly connected to the first S/D terminal (terminal of R2 directly connected to EVDD is directly connected to the first S/D terminal of M5), and wherein the resistor device further comprises an other terminal directly connected to the third S/D terminal (other terminal of R2 that is not directly connected to EVDD), and wherein the second and fourth S/D terminals (terminals connected to MPUb) are directly connected to a driver circuit of a memory device (MPUb is directly connected to output driver 65. The recitation of “driver circuit of a memory device” is merely intended use of the driver which the driver 65 is capable of operating within. Furthermore, Jin discloses the use of an output driver within a memory device, see Col. 2 lines 25-27).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dehganpour et al. (USPN 4,758,743) in view of Lai et al. (USPN 7,830,241).
With respect to 5, Dehganpour et al., that the resistors (31) may be sized to set a desired di/dt of the circuit (see Col. 7 lines 21-24). Dehganpour et al. to disclose the specific area ratio between the resistors and transistors. Thus, Dehganpour et al.. fails to disclose “wherein a ratio of an area of the resistor device to an area of each of the first and second transistor devices ranges from about 1.5 to about 2.0”.
However, it would have been obvious to size the resistors and transistors of Bickford et al. such that “a ratio of an area of the resistor device to an area of each of the first and second transistor devices ranges from about 1.5 to about 2.0”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. One would have been motivated to do so for the purpose of, among other things, setting the di/dt of the driver to a desired level.
Assuming, arguendo, that Dehganpour et al. merely discloses sizing the resistance of the resistor to a desired range/value and not sizing the area of the resistor to a desired range/value. It would have been obvious to size the area of the resistor and transistors to provide the above desired obvious ranges, since it is known that in an ideal resistor the resistance of the ideal resistor is set and proportional to the coefficient of resistance, length and the inverse of sectional area of the resistor structure. It is further known to maintain a constant coefficient of resistor structure and constant sectional area of the resistor and alter the total resistance by altering the length of the resistor. This is further evidenced by Lai et al. in Col. 3 lines 51-59.
It would have been obvious to set the length, and therefore inherently set the circuit area of the resistor, of the material of the resistor structures while maintaining a constant coefficient of resistance and sectional area of the resistor structures of the resistors of Dehganpour et al., for the purpose of setting the resistance of the resistors to set the above obvious area ranges and setting the desired di/dt of the output driver.
Claim 13 is rejected for similar reasons as claim 5.
Claim(s) 1, 6, 9 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Braswell et al. (USPN 10,033,399) in view of Mathew et al. (USPN 6,404,237).
With respect to claim 1, Braswell et al. discloses, in Fig. 2, a circuit (circuit of Fig. 2), comprising:
a first switch (e.g., 247) having a first terminal (terminal directly connected RT1) and a second terminal (terminal directly connected to 260); and
a resistor device (e.g., RT1) electrically connected to the first terminal (terminal RT1 is connected to the first terminal of 247), wherein the resistor device comprises a terminal directly connected to a reference voltage supply (terminal directly connected to VDD).
Braswell et al. further discloses that the switches of Fig. 2 are constructed from transmission gates (see Col. 4 lines 58-60). However, Braswell et al. fails to explicitly disclose how the transmission gates are constructed. Thus, Braswell et al. fails to explicitly disclose:
“a first transistor device with a first source/drain (S/D) terminal and a second S/D terminal;
a second transistor device with a third S/D terminal and a fourth S/D terminal; and
a resistor device electrically connected between the first and third S/D terminals or between the second and fourth S/D terminals, wherein the resistor device comprises a terminal directly connected to a reference voltage supply”.
However, Mathew et al. discloses, in Fig. 2A, a specific transmission gate (Fig. 2A) comprising a first transistor device (290) with a first source/drain (S/D) terminal (e.g., terminal connected to IN) and a second S/D terminal (e.g., terminal connected to OUT);
a second transistor device (230) with a third S/D terminal (e.g., terminal connected to IN) and a fourth S/D terminal (e.g., terminal connected to OUT); and
an input node (IN) electrically connected between the first and third S/D terminals or between the second and fourth S/D terminals (IN is electrically connected between the first and third terminals).
The transmission gate of Mathew et al. has a reduced capacitive load when used with multiple transmission gate switch devices and allows for faster operation speeds (see Col. 1 lines 21-40 and Col. 2 lines 15-25).
It would have been obvious to replace the generic switches that are constructed from transmission gates of Fig. 2 of Braswell et al. with the transmission gate of Fig. 2A of Mathew et al. for the purpose of having transmission gates with a lower load capacitance and/or higher operational speed.
As combined above the resistor RT1 connected to 247 of Braswell et al. will be connected to the IN terminal of Mathew et al. Thus the resistor RT1 will be electrically connected between the first and third S/D terminals of Braswell et al. and the other terminal of RT1 is directly connected to a reference voltage supply. Thus, the above combination is connected and operative as claimed.
With respect to claim 6, the circuit of claim 1, wherein a gate terminal of the first transistor device (gate of 290) is electrically connected to the reference voltage supply (to VDD of Braswell et al./VCC of Mathew et al. via 248 of Mathew et al.) and a gate terminal of the second transistor device (gate of 230 of Mathew et al.) is electrically connected to a another reference voltage supply (either one of VCC+∆V, e.g., VDD+∆V as combined above with respect to Braswell et al, via 236 of Mathew et al. or ground via 238).
With respect to claim 7, the circuit of claim 6, wherein the reference voltage supply is electrically connected to the first and third S/D terminals (via RT1 of Braswell et al.).
With respect to claim 9, Braswell et al. discloses, in Fig. 2, circuit (Fig. 2), comprising:
a switch (e.g., 247) with a first terminal (terminal connected to RT1) and a second terminal (terminal connected to 260); and
a resistor device (RT1) comprising:
a first terminal directly connected to the first terminal (terminal directly connected to 247); and
a second terminal directly connected to a reference voltage supply (terminal directly connected to VDD).
Braswell et al. further discloses that the switches of Fig. 2 are constructed from transmission gates (see Col. 4 lines 58-60). However, Braswell et al. fails to explicitly disclose how the transmission gates are constructed. Thus, Braswell et al. fails to explicitly disclose:
“a first transistor device with a first source/drain (S/D) terminal and a second S/D terminal;
a second transistor device with a third S/D terminal and a fourth S/D terminal, wherein the third S/D terminal is electrically connected to the first S/D terminal and the fourth S/D terminal is electrically connected to the second S/D terminal”; and
the first terminal of the resistor device “directly connected to the first and third S/D terminals.”
However, Mathew et al. discloses, in Fig. 2A, a specific transmission gate (Fig. 2A) comprising a first transistor device (one of 230 and 290) with a first source/drain (S/D) terminal (terminal connected to IN) and a second S/D terminal (terminal connected to OUT);
a second transistor device (other one of 230 and 290) with a third S/D terminal (terminal connected to IN) and a fourth S/D terminal (terminal connected to OUT), wherein the third S/D terminal is electrically connected to the first S/D terminal (IN, 230 and 290 connected as claimed) and the fourth S/D terminal is electrically connected to the second S/D terminal (OUT, 230 and 290 connected as claimed); and
the input terminal directly connected to the first and third S/D terminals (IN connected as claimed).
The transmission gate of Mathew et al. has a reduced capacitive load when used with multiple transmission gate switch devices and allows for faster operation speeds (see Col. 1 lines 21-40 and Col. 2 lines 15-25).
It would have been obvious to replace the generic switches that are constructed from transmission gates of Fig. 2 of Braswell et al. with the transmission gate of Fig. 2A of Mathew et al. for the purpose of having transmission gates with a lower load capacitance and/or higher operational speed.
As combined above the resistor RT1 connected to 247 of Braswell et al. will be connected to the IN terminal of Mathew et al. Thus the resistor RT1 will be electrically connected between the first and third S/D terminals of Braswell et al. and the other terminal of RT1 is directly connected to a reference voltage supply. Thus, the above combination is connected and operative as claimed.
With respect to claim 14, the circuit of claim 9, wherein a gate terminal of the first transistor device (gate terminal of one of 230 and 290) is electrically connected to a first reference voltage supply (one of -∆V, via 246 for gate of 290 as the first transistor device; or one of ground via 238 and VCC+∆V for 230 as the first transistor device) and a gate terminal of the second transistor device is electrically connected to a second reference voltage supply (other one of ground via 238 and VCC+∆V for 230 as the second transistor device; or other one of -∆V, via 246 for gate of 290 as the second transistor device).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Flamm (USPN 8,179,158) in view of Dehganpour et al. (USPN 4,758,743).
With respect to claim 11, Flamm discloses, in Fig. 3, an output driver (16) having an output (14) directly (directly connected via conductors 32, 34 and 36. This is the same “direct” connection as applicants interconnect/conductor of 130 between output driver of 110 and memory 120 of Figs. 1 and 3 of the instant application) connected to a driver circuit of a memory device (“other” circuits 28 and 30 which are memory devices such RAMs, see Col. 4 lines 27-35).
Flamm fails to disclose, the “circuit of claim 9, wherein the second and fourth S/D terminals are directly connected to a driver circuit of” the memory device.
However, Dehganpour et al. discloses, in Fig. 4, an output driver (Fig. 4) comprising the circuit of claim 9 (see above rejection of claim 9), wherein the second and fourth S/D terminals (terminals connected to 51) are directly connected to the output of the driver circuit (51 directly connected to DO). The output driver of Dehganpour has an optimized di/dt to avoid errors in the output signal due to improper di/dt of the output signal (see Figs. 2 and 3).
It would have been obvious to replace the generic output driver of Flamm with the specific output driver of Dehganpour for the purpose of having an output driver with an optimized di/dt and avoids errors in the output signal.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3, 5-7, 9-11 and 13-14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2849