DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
This is in response to applicant’s amendment/response filed on December 22nd 2025 which have been entered and made of record.
Applicant’s arguments with respect to 35 U.S.C. 102 claim(s) 1-30 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective
filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-30 are rejected under 35 U.S.C. 103 as being unpatentable over Ray et al. U.S. Patent Application Publication 20240087077 A1 (hereinafter Ray) in view of Sarangi et al. U.S. Patent Application Publication 20160139934 A1 (hereinafter Sarangi)
Regarding claim 1, Ray teaches an apparatus (Graphics processor) for implementing information processing (Multi-Render Partitioning Techniques), the apparatus comprising: (Para. 0043)
a databus; (Bus, Para. 0045, Fig. 1)
a memory system coupled to the databus; (System Memory, Para. 0049, Fig. 1)
and a graphics processing unit (GPU) coupled to the memory system and the databus, wherein the GPU is configured to do the following: (Parallel Processor(s) 112, Para. 0045 and 0053, Fig. 1)
retrieve a first plurality of atomic operations (Multiple Bit-Operation Atomic Messages) containing a first plurality of data values (Channel Mask 2922) for a shared memory location; (Same DW Address, Para. 0377, Fig. 29)
compute a first aggregate data (Updated Mask 2942) value based on the first plurality of data values (Channel Mask 2922, Para. 0377, Fig. 29);
and generate (Merged Atomic Operation 2940) containing the first aggregate data value(Updated Mask 2942, Para. 0377, Fig. 29) to replace the first plurality of atomic operations. (Merges Multiple Atomic Operations into a Single Atomic Operation, Para. 0375)
However, Ray fails to teach:
Generate without conversion a first aggregate atomic operation
Ray and Sarangi are analogous to the claimed invention because both of them are in the same field of aggregating atomic operations.
Sarangi teaches:
and generate without conversion (Without Changing the Set of Atomic Operations Operator) a first aggregate atomic operation containing (Single Add Atomic Operation) the first aggregate data value (Sum of Add Atomic Operations Values) to replace the first plurality of atomic operations (Set of Add Atomic Operations). (Para. 0013 and 0021, Fig. 1B) Sarangi changes multiple add atomic operations into a single add atomic operation.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ray’s Generation of Aggregate Atomic Operations to incorporate Sarangi’s Generation that Does Not Include Conversion. Since doing so would provide the benefit of reducing complexity and increasing performance gain by maintaining substantially the atomic operation (Sarangi et al. Para. 0021)
Regarding claim 2, Ray teaches the apparatus of claim 1, wherein the GPU includes an aggregator (Atomic Operand Merge Logic 2822), wherein the aggregator is configured to compute the first aggregate data value (Updated Mask 2942) and to generate the first aggregate atomic operation. (Merged Atomic Operation 2940, Para. 0377, Fig. 27-29)
Regarding claim 3, Ray teaches the apparatus of claim 1, wherein the GPU (Graphics Processing Engine 2710) is further configured to execute (Graphics Core 2724) the first aggregate atomic operation (Merged Atomic Operation 2940) containing the first aggregate data value (Updated Mask 2942) by modifying the shared memory (Byte Offset, Table 5) location. (Para. 0364 and 0377, Fig. 27-28)
Regarding claim 4, Ray teaches the apparatus of claim 3, wherein the GPU is further configured to receive (Unified Return Buffer 1718) a first return data value (Output Data) from execution (Threads Executing on Graphics Core Cluster 1714) of the first aggregate atomic operation with data return. (Fig. 17, Para. 0278)
Regarding claim 5, Ray teaches the apparatus of claim 4, wherein the GPU is further configured to successively offset the first return data value (Byte Offset) to generate a first plurality of offsetted return data values. (Table 5, Para. 0374)
Regarding claim 6, Ray teaches the apparatus of claim 5, further comprising:
a display processing unit (DPU) (I/O Hub 107) coupled to the databus; (Communication Link 106/113, Para. 0049, Fig. 1)
and a video display (Display Devices 110A) coupled to the DPU and the databus, wherein the video display is configured to display the first return data value (Rendered Image for Display) and/or the first plurality of offsetted return data values. (Fig. 1, Para.0062)
Regarding claim 7, has similar limitations as of claim 2, therefore it is rejected under the same rationale as claim 2.
Regarding claim 8, Ray teaches the apparatus of claim 5, wherein the GPU is further configured to:
retrieve a second plurality of atomic operations (Multiple Bit-Operation Atomic Messages) containing a second plurality of data values (Channel Mask 2922) for the shared memory location; (Same DW Address, Para. 0377, Fig. 29)
compute a second aggregate data value (Updated Mask 2942) based on the second plurality of data values; (Channel Mask 2922, Para. 0377, Fig. 29)
and generate a second aggregate atomic operation (Merged Atomic Operation 2940) containing the second aggregate data value. (Updated Mask 2942, Para. 0377, Fig. 29)
Regarding claim 9, Ray teaches the apparatus of claim 8, wherein the GPU is further configured to:
Receive (Unified Return Buffer 1718) a second return data value (Output Data) from the executing (Threads Executing on Graphics Core Cluster 1714) of the second aggregate atomic operation with data return; (Fig.17, Para. 9278)
and successively offset the second return data value (Byte Offset) to generate a second plurality of offsetted return data values. (Table 5, Para. 0374)
Regarding claim 10, Ray teaches the apparatus of claim 9, wherein the memory system (Fig. 1) comprises a memory unit (Memory Unit 224, Fig. 2A) and a cache memory. (L2 Cache 221, Fig. 2B)
Regarding claim 11, is drawn to the method of using the corresponding apparatus claimed in claim 1. Therefore, method claim 11 corresponds to apparatus claim 1 and is rejected for the same reasons of anticipation as used above.
Regarding claim 12, Ray teaches the method of claim 11, further comprising retrieving a second plurality of atomic operations (Multiple Bit-Operation Atomic Messages) containing a second plurality of data values (Channel Mask 2922) for the shared memory location. (Same DW Address, Para. 0377, Fig. 29)
Regarding claim 13, Ray teaches the method of claim 12, further comprising computing a second aggregate data value (Updated Mask 2942) based on the second plurality of data values. (Channel Mask 2922, Para. 0377, Fig. 29)
Regarding claim 14, Ray teaches the method of claim 13, further comprising generating a second aggregate atomic operation (Merged Atomic Operation 2940) containing the second aggregate data value. (Updated Mask 2942, Para. 0377, Fig. 29)
Regarding claim 15, has similar limitations as of claim 3, therefore it is rejected under the same rationale as claim 3.
Regarding claim 16, Ray teaches the method of claim 15, further comprising executing (Graphics Core 2724) the second aggregate atomic operation (Merged Atomic Operation 2940) containing the second aggregate data value (Updated Mask 2942) by modifying the shared memory (Byte Offset, Table 5) location. (Para, 0364 and 0377, Fig. 27-28)
Regarding claim 17, has similar limitations as of claim 4, therefore it is rejected under the same rationale as claim 4.
Regarding claim 18, has similar limitations as of claim 5, therefore it is rejected under the same rationale as claim 5.
Regarding claim 19, Ray teaches the method of claim 18, further comprising receiving (Unified Return Buffer 1718) a second return data value (Output Data) from the executing (Threads Executing on Graphics Core Cluster 1714) of the second aggregate atomic operation with data return. (Fig. 17, Para. 0278)
Regarding claim 20, Ray teaches 20. the method of claim 19, further comprising successively offsetting the second return data value (Byte Offset) to generate a second plurality of offsetted return data values. (Table 5, Para. 0374)
Regarding claim 21, has similar limitations as of claim 15, therefore it is rejected under the same rationale as claim 15.
Regarding claim 22, has similar limitations as of claim 17, therefore it is rejected under the same rationale as claim 17.
Regarding claim 23, has similar limitations as of claim 18, therefore it is rejected under the same rationale as claim 18.
Regarding claim 24, has similar limitations as of claim 1, therefore it is rejected under the same rationale as claim 1.
Regarding claim 25, has similar limitations as of claim 8, therefore it is rejected under the same rationale as claim 8.
Regarding claim 26, has similar limitations as of claims 3 and 16, therefore it is rejected under the same rationale as claims 3 and 16.
Regarding claim 27, Ray teaches the apparatus of claim 26, further comprising:
a first processing engine (Para. 0274) configured to receive (Unified Return Buffer 1718) a first return data value (Output Data) from the executing (Threads Executing on Graphics Core Cluster 1714) of the first aggregate atomic operation with data return; (Fig. 17, Para. 0278)
means for successively offsetting the first return data value (Byte Offset) to generate a first plurality of offsetted return data values. (Table 5, Para. 0374)
Regarding claim 28, Ray teaches the apparatus of claim 27, further comprising:
a modem (Para. 0049 and 0274) configured to receive (Unified Return Buffer 1718) a second return data value (Output Data) from the executing (Threads Executing on Graphics Core Cluster 1714) of the second aggregate atomic operation with data return; (Fig.17, Para. 9278) A modem is an input/output device to external entities.
and means for successively offsetting the second return data value (Byte Offset) to generate a second plurality of offsetted return data values. (Table 5, Para. 0374)
Regarding claim 29, Ray discloses the apparatus of claim 1 as discussed above and a non-transitory computer-readable medium (Para. 0428) storing computer executable code, operable on a device comprising at least one processor (Processor(s) 102 or Parallel Processor(s) 112) and at least one memory (System Memory 104 or Memory Hub 105) coupled to the at least one processor (Fig. 1, Para. 0049), wherein the at least one processor is configured to execute the instructions of claim 1. Therefore claim 29 is rejected under the same rationale as claim 1.
Regarding claim 30, has similar limitations as of claims 3-5, therefore it is rejected under the same rationale as claims 3-5.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIANNA R COCHRAN whose telephone number is (571)272-4671. The examiner can normally be reached Mon-Fri. 7:30am - 5:00pm.
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/BRIANNA RENAE COCHRAN/Examiner, Art Unit 2615
/ALICIA M HARRINGTON/Supervisory Patent Examiner, Art Unit 2615