DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3, 5, 9, 11, 19 have been amended. Claim 2 has been canceled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Attarwala (US-20160205066) in view of Tang (20220188254).
Regarding claim 1 Attarwala teaches A computer-implemented method for operating a data routing platform of a home appliance, the data routing platform comprising a plurality of devices communicatively coupled to a master control board, the method comprising:
receiving, at a device of the plurality of devices, a data packet ([0048] “the host controller 205 can utilize the UART packet structure to transmit and receive data on the communication bus”),
the data packet comprising packet address data ([0082] “FIG. 20 illustrates the operation of the host controller 2005 dispatching a communication 2010 that is directed to an individual slave device 2020, where the communication is an individual write command. The individual write command 2010 is specified by the host controller 2005 via a command byte that includes bit sequences signaling a command to an individual slave device, and further signaling a write operation and providing the unique device address of slave device to which the individual command is directed”),
the plurality of devices being communicatively coupled in a daisy chain topology to form a daisy chain sequence that is coupled to the master control board at a pin location of the master control board ([0049] “the host controller 105 communicates with each of the slave devices 110, 115, 120 using the unique device address of each slave device. Rather than utilizing fixed unique device addresses provided by the manufactures of the slave device, as described above, embodiments assign unique addresses to each slave device 110, 115, 120 when the daisy chain system is initialized for the first time. Thus, via the single-wire communication bus linking the daisy chained devices to the host controller 105, each slave device 110, 115, 120 is assigned a unique device address based on a starting device addressing that is specified by the host controller 105 and assigned to the first slave device 110 in the chain, (Examiner’s Note: host controller is equivalent to master control board, slave devices are equivalent to plurality of device), ([0047] “ embodiments where a set of slave devices 110, 115, 120 is connected in a daisy chain configuration to a host controller 105 via a single pin 125 of the host controller. As a daisy chain configuration, each device is connected to exactly two neighboring devices, except for the host controller 105 and the final slave device 120 in the chain, which are connected to a single neighbor. The host controller 105 sends commands to the slave devices 110, 115, 120 via the single communication bus forming the daisy chain connection between the devices”);
determining, at the device, whether the packet address data matches device address data of the device ([0082] “FIG. 20 illustrates the operation of the host controller 2005 dispatching a communication 2010 that is directed to an individual slave device 2020, where the communication is an individual write command. The individual write command 2010 is specified by the host controller 2005 via a command byte that includes bit sequences signaling a command to an individual slave device, and further signaling a write operation and providing the unique device address of slave device to which the individual command is directed”),
the device address data comprising a physical address corresponding to the pin location at which the daisy chain sequence is coupled to the master control board, ([0047] “ embodiments where a set of slave devices 110, 115, 120 is connected in a daisy chain configuration to a host controller 105 via a single pin 125 of the host controller. As a daisy chain configuration, each device is connected to exactly two neighboring devices, except for the host controller 105 and the final slave device 120 in the chain, which are connected to a single neighbor. The host controller 105 sends commands to the slave devices 110, 115, 120 via the single communication bus forming the daisy chain connection between the devices”);
and responsive to determining the packet address data does not match the device address data of the device, ([0083] “The first slave device 2015 receives the write command 2010, parses the command byte and determines that an individual write command is specified, but the device address specified by the command byte command is different from the device address of the first slave device 2015. Since the write command 201 is individual command not addressed to the first slave device 2015, the first slave device takes no further action”).
Attarwala does not teach each device of the plurality of devices storing identical device address data, implementing, at the device, an address translation operation to generate updated packet address data.
Tang teaches each device of the plurality of devices storing identical device address data ([0002] “ Some SPI Slave devices come with built-in address. In the independent SPI connection (e.g., FIG. 2), chip select (CS) is used to select one of the Slave devices from all Slave devices with the same built-in address”), implementing, at the device, an address translation operation to generate updated packet address data ([0005] “when the target slave address and the slave address stored in the first slave device matches, reporting to the master device, or when the target slave address and the slave address stored in the first slave device does not match, updating the data packet and transmitting the updated data packet to a second slave device in the plurality of slave devices, updating the data packet comprises updating the start address by adding to the current start address the increment value”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Attarwala to incorporate the teachings of Tang. One of ordinary skill in the art would have been motivated to make this modification in order to effectively identify identifying target slave address for serial communication interface.
Regarding claim 9, Attarwala wherein the data routing platform further comprises a network interface, the network interface coupling the daisy chain sequence to the master control board at the pin location of the master control board ([0048] “In the system of FIG. 2, the host controller 205 utilizes one pin 225 for transmissions and another pin 230 for receipt of communications. Such a configuration utilizing separate input and output pins allows the host controller 205 to be configured as a UART (Universal Asynchronous Receiver/Transmitter) controller, thus utilizing existing UART communication capabilities already present in certain controllers. Configured as a UART controller, the host controller 205 can utilize the UART packet structure to transmit and receive data on the communication bus”).
Claim(s) 3-8, 10-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Attarwala in view of Tang further in view of Swain et al. (US20080155073 herein Swain).
Regarding claim 3, Attarwala teaches wherein: the packet address data comprises a destination address corresponding to an intended receiving device of the data packet ([0084] “The second slave device 2020 receives the write command 2010 on the communication bus, reads the command and forwards the command downstream to the third slave device 2025. The second slave device 2020 processes the write command 2010 and determines that that the device address specified in the command byte matches the device address assigned to the second slave device. The second slave device 2020 processes the write command 2010 further to extract the address location encoded in the register pointer byte. In some embodiments, multiple register pointer bytes will be included in the write command 2010.”, (Examiner’s Note: device address specified in the command byte is equivalent to destination address)
the intended receiving device and ([0084[ “The second slave device 2020 receives the write command 2010 on the communication bus, reads the command and forwards the command downstream to the third slave device 2025. The second slave device 2020 processes the write command 2010 and determines that that the device address specified in the command byte matches the device address assigned to the second slave device. The second slave device 2020 processes the write command 2010 further to extract the address location encoded in the register pointer byte. In some embodiments, multiple register pointer bytes will be included in the write command 2010.”, (Examiner’s Note: one of the plurality of devices).
Attarwala, and Tang does not explicitly teach and a source address corresponding to a source device of the data packet, the source device being at least one of the plurality of devices or the master control board.
Swain teaches and a source address corresponding to a source device of the data packet ([0028] “Framing of packets for configuration PDUs is performed at the Transport Layer 210. The Transport Layer 210 prepends the multicast address, source address and type of message to each command message.”), the source device being at least one of the plurality of devices or the master control board ([0040] “With the boundary ports identified and boundary devices identified, a master device for the daisy-chain system is defined such that the discovery propagation packet may be sent in only one direction. Specifically, both boundary devices start the discovery process after receiving the link change propagation packet, by generating discovery propagation packets in both directions, and the source MAC addresses of the discovery propagation packets are compared to only propagate the device information in one direction, from the master device”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Attarwala, Tang to incorporate the teachings of Swain. One of ordinary skill in the art would have been motivated to make this modification in order to improve management of daisy system chain topology systems.
Regarding claim 4, Attarwala wherein determining whether the packet address data matches the device address data of the device comprises: determining, at the device, whether the destination address of the packet address data matches the physical address of the device address data ([0084] “ The second slave device 2020 processes the write command 2010 and determines that that the device address specified in the command byte matches the device address assigned to the second slave device. The second slave device 2020 processes the write command 2010 further to extract the address location encoded in the register pointer byte”).
Regarding claim 5, Attarwala teaches further comprising: responsive to determining the destination address of the packet address data matches the physical address of the device address data ([0084] “ The second slave device 2020 processes the write command 2010 and determines that that the device address specified in the command byte matches the device address assigned to the second slave device. The second slave device 2020 processes the write command 2010 further to extract the address location encoded in the register pointer byte”),
generating, at the device, a response packet; and responsive to generating the response packet, transmitting the response packet to an adjacent device in an up-chain direction from the device, wherein the up-chain direction is a direction moving towards the master control board along the daisy chain sequence ([0092] “Upon determining that its device address matches the device address specified in the global read command such that no downstream devices will respond to the command, the second slave device 2220 retrieves the data stored at the location specified by the register pointer byte of the global read command… The first slave device 2215, still in reverse pass-through mode, receives the data response 2210, reads the response and forwards it upstream to the host controller 2205”).
Regarding claim 6, Attarwala does not explicitly teach wherein implementing the address translation operation comprises: responsive to determining the destination address of the packet address data does not match the physical address of the device address data, determining, at the device, the source device based on the source address of the packet address data.
Tang teaches wherein implementing the address translation operation comprises: responsive to determining the destination address of the packet address data does not match the physical address of the device address data ([0005] “when the target slave address and the slave address stored in the first slave device matches, reporting to the master device, or when the target slave address and the slave address stored in the first slave device does not match, updating the data packet and transmitting the updated data packet to a second slave device in the plurality of slave devices, updating the data packet comprises updating the start address by adding to the current start address the increment value”),
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Attarwala to incorporate the teachings of Tang. One of ordinary skill in the art would have been motivated to make this modification in order to effectively identify identifying target slave address for serial communication interface.
Tang does not teach determining, at the device, the source device based on the source address of the packet address data.
Swain teaches determining, at the device, the source device based on the source address of the packet address data ([0040] “With the boundary ports identified and boundary devices identified, a master device for the daisy-chain system is defined such that the discovery propagation packet may be sent in only one direction. Specifically, both boundary devices start the discovery process after receiving the link change propagation packet, by generating discovery propagation packets in both directions, and the source MAC addresses of the discovery propagation packets are compared to only propagate the device information in one direction, from the master device”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Attarwala, Tang to incorporate the teachings of Swain. One of ordinary skill in the art would have been motivated to make this modification in order to improve management of daisy system chain topology systems.
Regarding claim 7, Attarwala does not explicitly teach wherein implementing the address translation operation further comprises: responsive to determining the source device is the master control board, decrementing, at the device, the destination address of the packet address data to generate the updated packet address data, the updated packet address data comprising an updated destination address of the data packet; and responsive to decrementing the destination address of the packet address data, transmitting the data packet to an adjacent device in a down-chain direction from the device, the data packet comprising the updated packet address data, wherein the down-chain direction is a direction moving away from the master control board along the daisy chain sequence.
Tang teaches wherein implementing the address translation operation further comprises: ([0005] “when the target slave address and the slave address stored in the first slave device matches, reporting to the master device, or when the target slave address and the slave address stored in the first slave device does not match, updating the data packet and transmitting the updated data packet to a second slave device in the plurality of slave devices, updating the data packet comprises updating the start address by adding to the current start address the increment value”);
and responsive to decrementing the destination address of the packet address data, transmitting the data packet to an adjacent device in a down-chain direction from the device, the data packet comprising the updated packet address data, wherein the down-chain direction is a direction moving away from the master control board along the daisy chain sequence ([0005] “when the target slave address and the slave address stored in the first slave device matches, reporting to the master device, or when the target slave address and the slave address stored in the first slave device does not match, updating the data packet and transmitting the updated data packet to a second slave device in the plurality of slave devices, updating the data packet comprises updating the start address by adding to the current start address the increment value”, (Examiner’s Note: Decrementing is interpreted as going down the chain).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Attarwala to incorporate the teachings of Tang. One of ordinary skill in the art would have been motivated to make this modification in order to effectively identify identifying target slave address for serial communication interface.
Tang does not teach responsive to determining the source device is the master control board.
Swain teaches responsive to determining the source device is the master control board ([0040] “With the boundary ports identified and boundary devices identified, a master device for the daisy-chain system is defined such that the discovery propagation packet may be sent in only one direction. Specifically, both boundary devices start the discovery process after receiving the link change propagation packet, by generating discovery propagation packets in both directions, and the source MAC addresses of the discovery propagation packets are compared to only propagate the device information in one direction, from the master device”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Attarwala, Tang to incorporate the teachings of Swain. One of ordinary skill in the art would have been motivated to make this modification in order to improve management of daisy system chain topology systems.
Regarding claim 8, Attarwala does not teach wherein implementing the address translation operation further comprises: responsive to determining the source device is a device of the daisy chain sequence, incrementing, at the device, the source address of the packet address data to generate the updated packet address data, the updated packet address data comprising an updated source address of the data packet; and responsive to incrementing the source address of the packet address data, transmitting the data packet to an adjacent device in an up-chain direction from the device, the data packet comprising the updated packet address data, wherein the up-chain direction is a direction moving towards the master control board along the daisy chain sequence.
Tang teaches wherein implementing the address translation operation further comprises: ([0005] “when the target slave address and the slave address stored in the first slave device matches, reporting to the master device, or when the target slave address and the slave address stored in the first slave device does not match, updating the data packet and transmitting the updated data packet to a second slave device in the plurality of slave devices, updating the data packet comprises updating the start address by adding to the current start address the increment value”),
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Attarwala to incorporate the teachings of Tang. One of ordinary skill in the art would have been motivated to make this modification in order to effectively identify identifying target slave address for serial communication interface.
Tang does not teach responsive to determining the source device is a device of the daisy chain sequence, transmitting the data packet to an adjacent device in an up-chain direction from the device, the data packet comprising the updated packet address data, wherein the up-chain direction is a direction moving towards the master control board along the daisy chain sequence.
Swain teaches responsive to determining the source device is a device of the daisy chain sequence ([0043] “A discovery packet (either propagation or enumeration) format includes a multicast address, a source address, a length, a type, and a field including a device identifier (prpg) and a flag for device identifier (enum). When the flag is set to “0,” the device identifier in prpg is an advertised device identifier. When the flag is set to “1,” the device identifier in prpg is an actual device identifier”), transmitting the data packet to an adjacent device in an up-chain direction from the device, the data packet comprising the updated packet address data, wherein the up-chain direction is a direction moving towards the master control board along the daisy chain sequence ([0058] “The new device identifies itself as having a link status change, and generates a link change packet and a discovery packet that are propagated to the other devices on the new device's internal port that is coupled to device A, port 1. Device A, port 1 becomes an internal port, and device A”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Attarwala, Tang to incorporate the teachings of Swain. One of ordinary skill in the art would have been motivated to make this modification in order to improve management of daisy system chain topology systems.
Regarding claim 10, Attarwala, Tang does not explicitly teach wherein each of the plurality of devices is a circuit board comprising identical hardware and identical firmware.
Swain teaches wherein each of the plurality of devices is a circuit board comprising identical hardware ([0021]“Each device 102, 104, 106 includes storage 108, 112, and 116 respectively such as a flash memory or other form of non-volatile storage such as a hard drive, any form of read-only memory (ROM), or any type of magnetic storage device. Each device 102-106 also includes an Ethernet switch 110, 114, 116 respectively that preferably has at least two Ethernet ports, although more than two ports are possible”) and identical firmware ([0020] “ Device 102, Device 104, and Device 106 inter-connected in a serial fashion to form a daisy-chain system 100… A stacking protocol, implemented in software stored on each device, executes within each of the devices. The stacking protocol comprises a means by which the daisy-chain system topology is discovered, each device is enumerated, and a master device is defined. The stacking protocol also interacts with a virtual device manager, implemented as a software module, to manage and configure the system based on the known topology”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Attarwala, Tang to incorporate the teachings of Swain. One of ordinary skill in the art would have been motivated to make this modification in order to improve management of daisy system chain topology systems.
Regarding claim 11, Attarwala teaches A data routing platform for a home appliance, comprising: a master control board coupled to a network interface; a plurality of devices coupled in a daisy chain topology to form a daisy chain sequence, the daisy chain sequence being communicatively coupled to the master control board at a pin location of the master control board via the network interface, each device of the plurality of devices configured to perform data routing operations ([0049] “the host controller 105 communicates with each of the slave devices 110, 115, 120 using the unique device address of each slave device. Rather than utilizing fixed unique device addresses provided by the manufactures of the slave device, as described above, embodiments assign unique addresses to each slave device 110, 115, 120 when the daisy chain system is initialized for the first time. Thus, via the single-wire communication bus linking the daisy chained devices to the host controller 105, each slave device 110, 115, 120 is assigned a unique device address based on a starting device addressing that is specified by the host controller 105 and assigned to the first slave device 110 in the chain, (Examiner’s Note: host controller is equivalent to master control board, slave devices are equivalent to plurality of device), ([0047] “ embodiments where a set of slave devices 110, 115, 120 is connected in a daisy chain configuration to a host controller 105 via a single pin 125 of the host controller. As a daisy chain configuration, each device is connected to exactly two neighboring devices, except for the host controller 105 and the final slave device 120 in the chain, which are connected to a single neighbor. The host controller 105 sends commands to the slave devices 110, 115, 120 via the single communication bus forming the daisy chain connection between the devices”),
the data routing operations comprising, for each device of the plurality of devices: receiving a data packet ([0048] “the host controller 205 can utilize the UART packet structure to transmit and receive data on the communication bus”) comprising packet address data ([0082] “FIG. 20 illustrates the operation of the host controller 2005 dispatching a communication 2010 that is directed to an individual slave device 2020, where the communication is an individual write command. The individual write command 2010 is specified by the host controller 2005 via a command byte that includes bit sequences signaling a command to an individual slave device, and further signaling a write operation and providing the unique device address of slave device to which the individual command is directed”),
the packet address data comprising a destination address corresponding to an intended receiving device of the data packet ([0082] “FIG. 20 illustrates the operation of the host controller 2005 dispatching a communication 2010 that is directed to an individual slave device 2020, where the communication is an individual write command. The individual write command 2010 is specified by the host controller 2005 via a command byte that includes bit sequences signaling a command to an individual slave device, and further signaling a write operation and providing the unique device address of slave device to which the individual command is directed”)
determining whether the destination address of the packet address data matches device address data corresponding to the device ([0082] “FIG. 20 illustrates the operation of the host controller 2005 dispatching a communication 2010 that is directed to an individual slave device 2020, where the communication is an individual write command. The individual write command 2010 is specified by the host controller 2005 via a command byte that includes bit sequences signaling a command to an individual slave device, and further signaling a write operation and providing the unique device address of slave device to which the individual command is directed”),
the device address data comprising a physical address corresponding to the pin location at which the daisy chain sequence is coupled to the master control board ([0047] “ embodiments where a set of slave devices 110, 115, 120 is connected in a daisy chain configuration to a host controller 105 via a single pin 125 of the host controller. As a daisy chain configuration, each device is connected to exactly two neighboring devices, except for the host controller 105 and the final slave device 120 in the chain, which are connected to a single neighbor. The host controller 105 sends commands to the slave devices 110, 115, 120 via the single communication bus forming the daisy chain connection between the devices”);
and responsive to determining the destination address of the address data does not match the physical address of the device address data ([0083] “The first slave device 2015 receives the write command 2010, parses the command byte and determines that an individual write command is specified, but the device address specified by the command byte command is different from the device address of the first slave device 2015. Since the write command 201 is individual command not addressed to the first slave device 2015, the first slave device takes no further action”),
Attarwala does not explicitly teach and a source address corresponding to a source device of the data packet, each device of the plurality of devices storing identical device address data; implementing an address translation operation to generate updated packet address data.
Tang teaches each device of the plurality of devices storing identical device address data ([0002] “ Some SPI Slave devices come with built-in address. In the independent SPI connection (e.g., FIG. 2), chip select (CS) is used to select one of the Slave devices from all Slave devices with the same built-in address”),
implementing an address translation operation to generate updated packet address data ([0005] “when the target slave address and the slave address stored in the first slave device matches, reporting to the master device, or when the target slave address and the slave address stored in the first slave device does not match, updating the data packet and transmitting the updated data packet to a second slave device in the plurality of slave devices, updating the data packet comprises updating the start address by adding to the current start address the increment value”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Attarwala to incorporate the teachings of Tang. One of ordinary skill in the art would have been motivated to make this modification in order to effectively identify identifying target slave address for serial communication interface.
Tang does not teach and a source address corresponding to a source device of the data packet.
Swain teaches and a source address corresponding to a source device of the data packet ([0028] “Framing of packets for configuration PDUs is performed at the Transport Layer 210. The Transport Layer 210 prepends the multicast address, source address and type of message to each command message.”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Attarwala, Tang to incorporate the teachings of Swain. One of ordinary skill in the art would have been motivated to make this modification in order to improve management of daisy system chain topology systems.
Regarding claim 12, Attarwala does not explicitly teach wherein the address translation operation comprises, for each device of the plurality of devices: responsive to determining the destination address of the packet address data does not match the physical address of the device address data, determining the source device based on the source address of the packet address data; responsive to determining the source device is the master control board, decrementing the destination address of the packet address data to generate the updated packet address data, the updated packet address data comprising an updated destination address of the data packet; and responsive to decrementing the destination address of the packet address data, transmitting the data packet to an adjacent device in a down-chain direction from the device, the data packet comprising the updated packet address data, wherein the down-chain direction is a direction moving away from the master control board along the daisy chain sequence.
Tang teaches wherein the address translation operation comprises, for each device of the plurality of devices: responsive to determining the destination address of the packet address data does not match the physical address of the device address data, determining the source device based on the source address of the packet address data; ([0005] “when the target slave address and the slave address stored in the first slave device matches, reporting to the master device, or when the target slave address and the slave address stored in the first slave device does not match, updating the data packet and transmitting the updated data packet to a second slave device in the plurality of slave devices, updating the data packet comprises updating the start address by adding to the current start address the increment value”);
and responsive to decrementing the destination address of the packet address data, transmitting the data packet to an adjacent device in a down-chain direction from the device, the data packet comprising the updated packet address data, wherein the down-chain direction is a direction moving away from the master control board along the daisy chain sequence ([0005] “when the target slave address and the slave address stored in the first slave device matches, reporting to the master device, or when the target slave address and the slave address stored in the first slave device does not match, updating the data packet and transmitting the updated data packet to a second slave device in the plurality of slave devices, updating the data packet comprises updating the start address by adding to the current start address the increment value”, (Examiner’s Note: Decrementing is interpreted as going down the chain).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Attarwala to incorporate the teachings of Tang. One of ordinary skill in the art would have been motivated to make this modification in order to effectively identify identifying target slave address for serial communication interface.
Tang does not teach responsive to determining the source device is the master control board.
Swain teaches responsive to determining the source device is the master control board ([0040] “With the boundary ports identified and boundary devices identified, a master device for the daisy-chain system is defined such that the discovery propagation packet may be sent in only one direction. Specifically, both boundary devices start the discovery process after receiving the link change propagation packet, by generating discovery propagation packets in both directions, and the source MAC addresses of the discovery propagation packets are compared to only propagate the device information in one direction, from the master device”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Attarwala, Tang to incorporate the teachings of Swain. One of ordinary skill in the art would have been motivated to make this modification in order to improve management of daisy system chain topology systems.
Regarding claim 13, Attarwala does not explicitly teach wherein the address translation operation comprises, for each device of the plurality of devices: responsive to determining the destination address of the packet address data does not match the physical address of the device address data, determining the source device based on the source address of the packet address data; responsive to determining the source device is a device of the daisy chain sequence, incrementing the source address of the packet address data to generate the updated packet address data, the updated packet address data comprising an updated source address of the data packet; and responsive to incrementing the source address of the packet address data, transmitting the data packet to an adjacent device in an up-chain direction from the device, the data packet comprising the updated packet address data, wherein the up-chain direction is a direction moving towards the master control board along the daisy chain sequence.
Tang teaches wherein the address translation operation comprises, for each device of the plurality of devices: responsive to determining the destination address of the packet address data does not match the physical address of the device address data, determining the source device based on the source address of the packet address data; ([0005] “when the target slave address and the slave address stored in the first slave device matches, reporting to the master device, or when the target slave address and the slave address stored in the first slave device does not match, updating the data packet and transmitting the updated data packet to a second slave device in the plurality of slave devices, updating the data packet comprises updating the start address by adding to the current start address the increment value”),
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Attarwala to incorporate the teachings of Tang. One of ordinary skill in the art would have been motivated to make this modification in order to effectively identify identifying target slave address for serial communication interface.
Tang does not teach responsive to determining the source device is a device of the daisy chain sequence, transmitting the data packet to an adjacent device in an up-chain direction from the device, the data packet comprising the updated packet address data, wherein the up-chain direction is a direction moving towards the master control board along the daisy chain sequence.
Swain teaches responsive to determining the source device is a device of the daisy chain sequence ([0043] “A discovery packet (either propagation or enumeration) format includes a multicast address, a source address, a length, a type, and a field including a device identifier (prpg) and a flag for device identifier (enum). When the flag is set to “0,” the device identifier in prpg is an advertised device identifier. When the flag is set to “1,” the device identifier in prpg is an actual device identifier”),
transmitting the data packet to an adjacent device in an up-chain direction from the device, the data packet comprising the updated packet address data, wherein the up-chain direction is a direction moving towards the master control board along the daisy chain sequence ([0058] “The new device identifies itself as having a link status change, and generates a link change packet and a discovery packet that are propagated to the other devices on the new device's internal port that is coupled to device A, port 1. Device A, port 1 becomes an internal port, and device A”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Attarwala, Tang to incorporate the teachings of Swain. One of ordinary skill in the art would have been motivated to make this modification in order to improve management of daisy system chain topology systems.
Regarding claim 14, Attarwala teaches wherein the data routing operations further comprise, for each device of the plurality of devices: responsive to determining the destination address of the packet address data matches the physical address of the device address data ([0084] “ The second slave device 2020 processes the write command 2010 and determines that that the device address specified in the command byte matches the device address assigned to the second slave device. The second slave device 2020 processes the write command 2010 further to extract the address location encoded in the register pointer byte”),
generating a response packet; responsive to generating the response packet, transmitting the response packet to an adjacent device in an up-chain direction from the device, wherein the up-chain direction is a direction moving towards the master control board along the daisy chain sequence ([0092] “Upon determining that its device address matches the device address specified in the global read command such that no downstream devices will respond to the command, the second slave device 2220 retrieves the data stored at the location specified by the register pointer byte of the global read command… The first slave device 2215, still in reverse pass-through mode, receives the data response 2210, reads the response and forwards it upstream to the host controller 2205”).
Regarding claim 15, Attarwala, Tang does not explicitly teach wherein each of the plurality of devices is a circuit board comprising identical hardware and identical firmware.
Swain teaches wherein each of the plurality of devices is a circuit board comprising identical hardware ([0021]“Each device 102, 104, 106 includes storage 108, 112, and 116 respectively such as a flash memory or other form of non-volatile storage such as a hard drive, any form of read-only memory (ROM), or any type of magnetic storage device. Each device 102-106 also includes an Ethernet switch 110, 114, 116 respectively that preferably has at least two Ethernet ports, although more than two ports are possible”) and identical firmware ([0020] “ Device 102, Device 104, and Device 106 inter-connected in a serial fashion to form a daisy-chain system 100… A stacking protocol, implemented in software stored on each device, executes within each of the devices. The stacking protocol comprises a means by which the daisy-chain system topology is discovered, each device is enumerated, and a master device is defined. The stacking protocol also interacts with a virtual device manager, implemented as a software module, to manage and configure the system based on the known topology”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Attarwala, Tang to incorporate the teachings of Swain. One of ordinary skill in the art would have been motivated to make this modification in order to improve management of daisy system chain topology systems.
Regarding claim 16, Attarwala teaches wherein the network interface is a Universal Asynchronous Receiver/Transmitter (UART) ([0048] “In the system of FIG. 2, the host controller 205 utilizes one pin 225 for transmissions and another pin 230 for receipt of communications. Such a configuration utilizing separate input and output pins allows the host controller 205 to be configured as a UART (Universal Asynchronous Receiver/Transmitter) controller, thus utilizing existing UART communication capabilities already present in certain controllers. Configured as a UART controller, the host controller 205 can utilize the UART packet structure to transmit and receive data on the communication bus”).
Regarding claim 17, Attarwala teaches wherein the data routing platform comprises a single UART ([0048] “In the system of FIG. 2, the host controller 205 utilizes one pin 225 for transmissions and another pin 230 for receipt of communications. Such a configuration utilizing separate input and output pins allows the host controller 205 to be configured as a UART (Universal Asynchronous Receiver/Transmitter) controller, thus utilizing existing UART communication capabilities already present in certain controllers. Configured as a UART controller, the host controller 205 can utilize the UART packet structure to transmit and receive data on the communication bus”).
Regarding claim 18, Attarwala teaches wherein the UART is integral to the master control board ([0048] “In the system of FIG. 2, the host controller 205 utilizes one pin 225 for transmissions and another pin 230 for receipt of communications. Such a configuration utilizing separate input and output pins allows the host controller 205 to be configured as a UART (Universal Asynchronous Receiver/Transmitter) controller, thus utilizing existing UART communication capabilities already present in certain controllers. Configured as a UART controller, the host controller 205 can utilize the UART packet structure to transmit and receive data on the communication bus”).
Regarding claim 19, Attarwala teaches An appliance, comprising: a user interface comprising one or more user inputs; and a data routing platform comprising: a master control board coupled to a network interface; a plurality of devices coupled in a daisy chain topology to form a daisy chain sequence, the daisy chain sequence being communicatively coupled to the master control board at a pin location of the master control board via the network interface, each device of the plurality of devices configured to perform data routing operations ([0049] “the host controller 105 communicates with each of the slave devices 110, 115, 120 using the unique device address of each slave device. Rather than utilizing fixed unique device addresses provided by the manufactures of the slave device, as described above, embodiments assign unique addresses to each slave device 110, 115, 120 when the daisy chain system is initialized for the first time. Thus, via the single-wire communication bus linking the daisy chained devices to the host controller 105, each slave device 110, 115, 120 is assigned a unique device address based on a starting device addressing that is specified by the host controller 105 and assigned to the first slave device 110 in the chain, (Examiner’s Note: host controller is equivalent to master control board, slave devices are equivalent to plurality of device), ([0047] “ embodiments where a set of slave devices 110, 115, 120 is connected in a daisy chain configuration to a host controller 105 via a single pin 125 of the host controller. As a daisy chain configuration, each device is connected to exactly two neighboring devices, except for the host controller 105 and the final slave device 120 in the chain, which are connected to a single neighbor. The host controller 105 sends commands to the slave devices 110, 115, 120 via the single communication bus forming the daisy chain connection between the devices”),
the data routing operations comprising, for each device of the plurality of devices: receiving a data packet ([0048] “the host controller 205 can utilize the UART packet structure to transmit and receive data on the communication bus”) comprising packet address data ([0082] “FIG. 20 illustrates the operation of the host controller 2005 dispatching a communication 2010 that is directed to an individual slave device 2020, where the communication is an individual write command. The individual write command 2010 is specified by the host controller 2005 via a command byte that includes bit sequences signaling a command to an individual slave device, and further signaling a write operation and providing the unique device address of slave device to which the individual command is directed”),
the packet address data comprising a destination address corresponding to an intended receiving device of the data packet ([0082] “FIG. 20 illustrates the operation of the host controller 2005 dispatching a communication 2010 that is directed to an individual slave device 2020, where the communication is an individual write command. The individual write command 2010 is specified by the host controller 2005 via a command byte that includes bit sequences signaling a command to an individual slave device, and further signaling a write operation and providing the unique device address of slave device to which the individual command is directed”)
determining whether the destination address of the packet address data matches device address data corresponding to the device ([0082] “FIG. 20 illustrates the operation of the host controller 2005 dispatching a communication 2010 that is directed to an individual slave device 2020, where the communication is an individual write command. The individual write command 2010 is specified by the host controller 2005 via a command byte that includes bit sequences signaling a command to an individual slave device, and further signaling a write operation and providing the unique device address of slave device to which the individual command is directed”),
the device address data comprising a physical address corresponding to the pin location at which the daisy chain sequence is coupled to the master control board, ([0047] “ embodiments where a set of slave devices 110, 115, 120 is connected in a daisy chain configuration to a host controller 105 via a single pin 125 of the host controller. As a daisy chain configuration, each device is connected to exactly two neighboring devices, except for the host controller 105 and the final slave device 120 in the chain, which are connected to a single neighbor. The host controller 105 sends commands to the slave devices 110, 115, 120 via the single communication bus forming the daisy chain connection between the devices”);
and responsive to determining the destination address of the address data does not match the physical address of the device address data ([0083] “The first slave device 2015 receives the write command 2010, parses the command byte and determines that an individual write command is specified, but the device address specified by the command byte command is different from the device address of the first slave device 2015. Since the write command 201 is individual command not addressed to the first slave device 2015, the first slave device takes no further action”),
Attarwala does not explicitly teach and a source address corresponding to a source device of the data packet; each device of the plurality of devices storing identical device address data; implementing an address translation operation to generate updated packet address data.
Tang teaches each device of the plurality of devices storing identical device address data ([0002] “ Some SPI Slave devices come with built-in address. In the independent SPI connection (e.g., FIG. 2), chip select (CS) is used to select one of the Slave devices from all Slave devices with the same built-in address”);
implementing an address translation operation to generate updated packet address data ([0005] “when the target slave address and the slave address stored in the first slave device matches, reporting to the master device, or when the target slave address and the slave address stored in the first slave device does not match, updating the data packet and transmitting the updated data packet to a second slave device in the plurality of slave devices, updating the data packet comprises updating the start address by adding to the current start address the increment value”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Attarwala to incorporate the teachings of Tang. One of ordinary skill in the art would have been motivated to make this modification in order to effectively identify identifying target slave address for serial communication interface.
Tang does not teach and a source address corresponding to a source device of the data packet.
Swain teaches and a source address corresponding to a source device of the data packet ([0028] “Framing of packets for configuration PDUs is performed at the Transport Layer 210. The Transport Layer 210 prepends the multicast address, source address and type of message to each command message.”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Attarwala, Tang to incorporate the teachings of Swain. One of ordinary skill in the art would have been motivated to make this modification in order to improve management of daisy system chain topology systems.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Attarwala in view of Tang further in view of Swain further in view of Shribman et al. (US20160337426).
Regarding claim 20, Attarwala, Tang, Swain does not teach wherein the appliance is an induction cooktop appliance.
Shribman teaches wherein the appliance is an induction cooktop appliance ([0562] “any device or network element herein may comprise, consist of, or include a major appliance (white goods) and may be an air conditioner, dishwasher, clothes dryer, drying cabinet, freezer, refrigerator, kitchen stove, water heater, washing machine, trash compactor, microwave oven and induction cooker”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Attarwala, Tang, Swain to incorporate the teachings of Shribman. One of ordinary skill in the art would have been motivated to make this modification in order to provide functionality to a number of different types of devices.
Response to Arguments
Applicant's arguments filed 11/25/2025 have been fully considered but they are not persuasive.
Applicant’s Argument
As such, Attarwala fails to disclose or suggest "each device of the plurality of devices storing identical device address data" as required by amended claim 1.
Tang fails to cure this deficiency of Attarwala. Like Attarwala,Tang is directed to
systems and methods for assigning "each slave device in the plurality of slave devices a slave address that is unique to each slave device[,]" and the assigned "unique" slave device is subsequently stored by each salve device. Tang, Abstract. As such,Tang likewise fails to disclose or suggest "each device of the plurality of devices storing identical device address data" as required by amended claim 1.
Examiner’s Response
Examiner respectfully disagrees. See updated rejection. Attarwala in view of Tang teaches each device of the plurality of devices storing identical device address data.
Tang is relied upon to show each device of the plurality of devices storing identical device address data ([0002] In the SPI protocol, there are a 7-bit address for the target slave device and chip select (CS). Some SPI Slave devices come with built-in address. In the independent SPI connection (e.g., FIG. 2), chip select (CS) is used to select one of the Slave devices from all Slave devices with the same built-in address”).
Furthermore, Attarwala shows could BRI show each device having identical device address data ([0047] “ embodiments where a set of slave devices 110, 115, 120 is connected in a daisy chain configuration to a host controller 105 via a single pin 125 of the host controller) because since they all share the same pin connected to the controller could interpret that as a pin address which is a physical address.
Both Attarwala [0005] and Tang [0004] teach the same adding unique addresses to more effectively allow the master device/ controller to communicate. Based on Fig 6 of application there are two distinct addresses for each device one that identical and one that is unique. The unique addresses is the logical address, and it is because updated. Tang and Attarwala broadly show the physical address shown above. Based on the claims the updated addresses is the logical address.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wang (US 20240152480) mentions use of serial daisy chain that uses identical devices for peripheral devices.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/K.T.F./Examiner, Art Unit 2411
/DERRICK W FERRIS/Supervisory Patent Examiner, Art Unit 2411
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