DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 05/05/2026 Amendment.
Claims 1-9, 14-17 are pending and examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over US 8,982,647 to Nazarian et al. (hereafter Nazarian) in view of US 10,847,219 to Ge (hereafter Ge).
Regarding independent claim 1, Nazarian teaches an apparatus, comprising:
a plurality of bit lines intersecting with a plurality of word lines (FIG. 3B);
a plurality of cross-point devices, wherein each of the plurality of cross-point devices is connected to at least one of the plurality of word lines and at least one of the plurality of bit lines, and wherein each of the plurality of cross-point devices comprises a resistive random-access memory (RRAM) device (see FIG. 3B); and
a plurality of inherent switches connected to the plurality of word lines (FIG. 11: inherent switches within row control 1104, see 17:28-35), wherein each of the plurality of switches word lines is selectively connected to ground or a reference voltage via at least one of the plurality of switches to provide a FIG. 3B: switches to provide either 0V or 1V to word lines 302B), FIG. 3B: selected bit line 304B is provided with 1V).
Nazarian does not explicitly teach the strikethrough limitations. However, Nazarian suggests that selected word line is applied with 0V, while unselected word lines are applied with 1V. In digital memory, selection and de-selection of a word line are often represented with bit “1” and bit ‘0” at row control level, respectively.
Ge teaches RRAM cross-point device comprising digital-to-analog converters (DAC) 111 for converting input signal from digital format to analog values and supply the analog values to rows of RRAM cross-point device (see FIG. 1).
Since Nazarian and Ge are both from the same field of endeavor, the purpose disclosed by Nazarian would have been recognized in the pertinent art of Ge.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art:
to apply voltage scheme suggested in Nazarian to RRAM cross-point device of Ge in order to reduce sneak current (see Nazarian, FIGS. 3-4 and 5:55-6:14).
to realize that converting digital bit of “1” and “0” to analog values of ground and reference voltage is matter of design choice.
Regarding dependent claim 2, Nazarian teaches wherein a first switch of the plurality of switches is connected to a first word line of the plurality of word lines, wherein the first switch is connected to the ground when a first FIG. 3B: middle word line of word lines 302B is the selected word line and applied with 0V).
Ge teaches the input is digital input corresponding to each of the word lines (FIG. 1: digital input signal 119).
Regarding dependent claim 3, Nazarian teaches wherein the first switch is connected to the reference voltage when a second FIG. 3B: first word line of word lines 302B is the unselected word line and applied with 1V).
Ge teaches the input is digital input corresponding to each of the word lines (FIG. 1: digital input signal 119).
Regarding dependent claim 4, Nazarian implicitly teaches wherein the first bit of the digital input is a bit one, and wherein the second bit of the digital input is a bit zero (because in digital memory, selection and non-selection of a word line are often represented with bit “1” and bit ‘0” at row control level, respectively).
Regarding dependent claim 5, Nazarian teaches wherein a first terminal of a first RRAM device is connected to the first word line (FIG. 2: first terminal of each RRAM device is coupled to corresponding local word line 210), and wherein a second terminal of the first RRAM device is connected to a source terminal or a drain terminal of a transistor (the second terminal of each RRAM device is coupled to corresponding bit line 202, and the bit line is coupled to source/drain of Vbias switch 612 of FIG. 6).
Regarding dependent claim 6, Nazarian teaches wherein the reference voltage corresponds to a read voltage applied to a bit line connected to the first cross-point device (FIG. 3B: read voltage applied to middle bit line of bit lines 304B is also 1.0V).
Regarding dependent claim 7, Ge teaches a buffer that generates the reference voltage, wherein an output of the buffer is selectively connected to the plurality of switches (FIG. 1: circuit 101, details of which are in FIG. 3).
Regarding dependent claim 8, Ge teaches wherein the buffer is a unity gain amplifier (i.e. op-amp with negative feedback).
Regarding dependent claim 9, Nazarian wherein the plurality of switches comprises a plurality of multiplexers (FIG. 11: row control 1101 is considered multiplexers applying selective voltage to each of the word lines).
Regarding independent claim 14, Nazarian teaches an apparatus, comprising:
a first plurality of bit lines and a second plurality of bit lines intersecting with a plurality of word lines (FIG. 8: bit lines corresponding to block1 802 and block2 804, respectively; FIG. 2: word lines WL0-WLn);
a first switch that selectively connects a first segment of a first word line of the plurality of word lines to ground or a reference voltage (FIG. 3B: e.g. switch to provide 0V to middle word line of the word lines 302B of block1 802);
a second switch that selectively connects a second segment of the first word line to ground or the reference voltage (FIG. 3B: e.g. switch to provide 1V to first word line of the word lines 302B of block1 802);
a first plurality of cross-point devices connected to the first segment of the first word line and the first plurality of bit lines (FIG. 8: see block1); and
a second plurality of cross-point devices connected to the second segment of the first word line and the second plurality of bit lines (FIG. 8: see block2), wherein the first segment of the first word line is connected to ground to select de-select
Nazarian does not explicitly teach the bit “1” and bit “0” are corresponding to ground and reference voltage, respectively. However, in digital memory, selection and de-selection of a word line are often represented with bit “1” and bit ‘0” at row control level, respectively.
Ge teaches RRAM cross-point device comprising digital-to-analog converters (DAC) 111 for converting input signal from digital format to analog values and supply the analog values to rows of RRAM cross-point device (see FIG. 1).
Since Nazarian and Ge are both from the same field of endeavor, the purpose disclosed by Nazarian would have been recognized in the pertinent art of Ge.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art:
to apply voltage scheme suggested in Nazarian to RRAM cross-point device of Ge in order to reduce sneak current (see Nazarian, FIGS. 3-4 and 5:55-6:14).
to realize that converting digital bit of “1” and “0” to analog values of ground and reference voltage is matter of design choice.
Regarding dependent claim 15, Nazarian teaches wherein each of the first plurality of cross-point devices and the second plurality of cross-point devices comprises a resistive random-access memory (RRAM) device (see FIG. 3B).
Regarding dependent claim 16, Nazarian implicitly teaches wherein the first segment of the first word line is floating when the first switch is off (FIG. 2: when word line select 212 is off, the local word line 210 corresponding to block1 of FIG. 8 is floating).
Regarding dependent claim 17, Nazarian implicitly teaches wherein the second segment of the first word line is floating when the second switch is off (FIG. 2: when word line select 212 is off, the local word line 210 corresponding to block2 of FIG. 8 is floating).
Response to Arguments
Applicant’s arguments with respect to claims 1-9 and 14-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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August 10, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
