DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1-4 & 12 recite the limitation "the neuron circuit" in various lines. The claims as written are unclear. Neuron circuits for each intermediate circuit have been introduced and thus it is unclear if the limitation is referring to each of the neuron circuits or a singular neuron circuit among the neuron circuits for each intermediate circuit. For examination purposes, examiner has interpreted “the neuron circuit” to read “each of the neuron circuits”.
By virtue of their dependency on claim 1, claims 5-11 are also rejected.
Claims 7-11 recite the limitations "the time constant circuit" or “the time constant” in various lines. The claims as written are unclear. Time constant circuits with respective time constants for each neuron circuit have been introduced and thus it is unclear if the limitation is referring to each of the time constant circuits/time constant or a singular time constant circuit/time constant among the time constant circuits for each neuron circuit. For examination purposes, examiner has interpreted “the time constant circuit” to read “each of the time constant circuits” and “the time constant” to read “the respective time constant”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 & 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Marukame et al. (US 2019/0156181 A1), hereinafter Marukame, in view of Marukame et al. (US 11,586,887 B2), hereinafter Marukame 887.
Regarding claim 1, as best understood based on the 35 U.S.C. 112(b) rejection made above, Marukame discloses, in figures 1, 10, & 11, a reservoir calculation device comprising:
an input circuit configured to acquire an input signal and output input data corresponding to a level of the input signal (Para [0043], “communication unit 16 receives one or a plurality of input values to be computed”…of the neural network device 10);
a reservoir circuit (20) to which the input data is provided (from 22 to 52), the reservoir circuit being configured to output intermediate signals (output of multipliers 54), each undergoing a transient change when the input data changes (Para [0085], “each of the (m×n) multipliers 54 multiplies the first signal value corresponding to the row with which each multiplier 54 is associated among the m first signal values and the coefficient with which each multiplier 54 is associated among the (m×n) coefficients included in the coefficient matrix”); and
an output circuit configured to output an output signal obtained by combining the intermediate signals (Para [0094], “the addition circuit 58 adds (m×n) multiplication values output from the (m×n) multipliers 54 for each column to calculate the n forward multiplication-accumulation values (v.sub.1 to v.sub.n”), wherein
the reservoir circuit includes intermediate circuits (multipliers 54 with coefficient memories 56),
each of the intermediate circuits (54 & 56) includes:
a neuron circuit (54) for which weight data is set (Para [0004], “neural network multiplies each of the plurality of signal values output from a previous layer by a coefficient (weight)”…weight data set by the coefficient memory 56 for the multipliers 54), the neuron circuit being configured to acquire the input data and generate an intermediate voltage (multiplication values output from multipliers 54 that acquire input data from acquisition circuit 52), the intermediate voltage undergoing a transient change corresponding to the weight data and the input data when the input data changes (Para [0085], “each of the (m×n) multipliers 54 multiplies the first signal value corresponding to the row with which each multiplier 54 is associated among the m first signal values and the coefficient with which each multiplier 54 is associated among the (m×n) coefficients included in the coefficient matrix”); and
an intermediate output circuit configured to output, as one of the intermediate signals, an intermediate signal representing a level of the intermediate voltage output from the neuron circuit (the output line extending from each multiplier 54 indicative of each intermediate signal that represents a level of the intermediate voltage), but does not explicitly disclose each of the neuron circuits including a time constant circuit capable of changing a time constant, the time constant circuit being connected between a reference potential and an intermediate terminal outputting the intermediate voltage.
However, Marukame 887 discloses, in figure 3, each of the neuron circuits (neuron circuits 30) including a time constant circuit (firing circuit 68) capable of changing a time constant (Col. 6, Lines 23-27, “coefficient updating circuit 72 can acquire the timing of a pulse signal generated by the firing circuit 68 via a path inside the neuron circuit 30, and can update the coefficient assigned to the synapse circuit 40 based on the acquired timing”), the time constant circuit being connected between a reference potential and an intermediate terminal outputting the intermediate voltage (68 connected between reference potential via capacitor 70 and intermediate terminal 64).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the time constant circuit of Marukame 887 in the neuron circuits of Marukame, to achieve the benefit of effectively updating the coefficient values based on the timing of the neuron firing within the neuron circuits (Marukame 887, Col. 6, Lines 23-33).
Regarding claim 6, Marukame in view of Marukame 887 disclose the reservoir calculation device according to claim 1, and Marukame discloses, in figure 10, wherein the output circuit is configured to output the output signal obtained by multiplying and accumulating the intermediate signals and output weights set for advance (Para [0094], “addition circuit 58 adds (m×n) multiplication values output from the (m×n) multipliers 54 for each column to calculate the n forward multiplication-accumulation values (v.sub.1 to v.sub.n). Then, in the forward process, the addition circuit 58 outputs the calculated n forward multiplication-accumulation values (v.sub.1 to v.sub.n) to the layer computation unit 22”).
Regarding claim 7, Marukame in view of Marukame 887 disclose the reservoir calculation device according to claim 1, but does not explicitly disclose a control circuit configured to control each of the time constant circuits to change the respective time constant.
However, It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the control circuit to control each time constant circuit, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art [i.e., utilizing a control circuit to control and adjust values as needed]. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Marukame in view of Marukame 887 as applied to claims 1 & 6-7 above, and further in view of Marukame et al. (US 10,175,947 B1), hereinafter Marukame 947.
Regarding claim 2, as best understood based on the 35 U.S.C. 112(b) rejection made above, Marukame in view of Marukame 887 disclose the reservoir calculation device according to claim 1, and Marukame continues to disclose, in figures 1, 10, & 11, wherein
the input data includes input bits, each representing a binary value (Para [0148], “a neural network using a signal value expressed by binary values”),
the weight data includes weight bits, each representing a binary value (Para [0148], “coefficient expressed by multivalues (for example, four bits, eight bits, or 16 bits)”),
each of the input bits corresponds to a different one of the weight bits (each input bit corresponds to the associated row with set weight bits), but does not explicitly disclose each of the neuron circuits further including:
a constant current source; and
arithmetic circuits having a one-to-one correspondence with the input bits, each of the arithmetic circuits being connected between the intermediate terminal and the reference potential,
each of the arithmetic circuits includes a resistor and a switch, each of the arithmetic circuits having a resistance value caused by switching the switch, the resistance value corresponding to a multiplication value obtained by multiplying a corresponding one of the input bits by a corresponding one of the weight bits, and
the arithmetic circuits allow a current output from the constant current source to flow through the resistor.
However, Marukame 947 discloses, in figure 3, each of the neuron circuits further including:
a constant current source (32); and
arithmetic circuits having a one-to-one correspondence with the input bits (Col. 2, Lines 39-41, “arithmetic unit 20 receives M input signals and M coefficients. M is an integer equal to or larger than 2. The M coefficients correspond one-to-one to the M input signals”), each of the arithmetic circuits being connected between the intermediate terminal and the reference potential (connected between either of terminals 46/50 and ground),
each of the arithmetic circuits includes a resistor and a switch (resistors 74, 76 and cross switches 38), each of the arithmetic circuits having a resistance value caused by switching the switch (cross switches 38 present differing combined resistance values based on the state of operation), the resistance value corresponding to a multiplication value obtained by multiplying a corresponding one of the input bits by a corresponding one of the weight bits (Col. 3, Lines 17-20, “ arithmetic unit 20 performs product-sum operation (multiply accumulate operation) of the M input signals and M coefficients by analog processing”), and
the arithmetic circuits allow a current output from the constant current source to flow through the resistor (Col. 8, Lines 3-6, “When an ith input signal (x.sub.i) is +1, an ith cross switch 38-i is straight-connected. Therefore, the positive-side terminal 46 of the positive-side current source 32 supplies a current to the first resistor 74”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the arithmetic circuits of Marukame 947 in the neuron circuits of Marukame and Marukame 887, to achieve the benefit of realizing a nonlinear operation that simulates neurons with a simple configuration (Marukame 947, Col. 11, Lines 13-25).
Regarding claim 3, as best understood based on the 35 U.S.C. 112(b) rejection made above, Marukame in view of Marukame 887 disclose the reservoir calculation device according to claim 1, and Marukame continues to disclose, in figures 1, 10, & 11, wherein
the input data includes input bits, each representing a binary value (Para [0148], “a neural network using a signal value expressed by binary values”),
the weight data includes weight bits, each representing a binary value (Para [0148], “coefficient expressed by multivalues (for example, four bits, eight bits, or 16 bits)”),
each of the input bits corresponds to a different one of the weight bits (each input bit corresponds to the associated row with set weight bits), but does not explicitly disclose the elements of each of the neuron circuits.
However, Marukame 947 discloses, in figure 3, 5, & 6, each of the neuron circuits including:
a positive current source connected between a power supply potential and a positive intermediate terminal serving as the intermediate terminal on a positive side (positive-side current source 32 between V.sub.DD and intermediate terminal 46), the positive current source allowing a constant current to flow (constant current supplied to corresponding resistor depending on state of operation);
a negative current source connected between the power supply potential and a negative intermediate terminal serving as the intermediate terminal on a negative side (negative-side current source 34 between V.sub.DD and intermediate terminals 50), the negative current source allowing a constant current to flow (constant current supplied to corresponding resistor depending on state of operation); and
arithmetic circuits having a one-to-one correspondence with the input bits (Col. 2, Lines 39-41, “arithmetic unit 20 receives M input signals and M coefficients. M is an integer equal to or larger than 2. The M coefficients correspond one-to-one to the M input signals”), each of the arithmetic circuits being connected between the intermediate terminal and the reference potential (connected between either of terminals 46/50 and ground),
each of the arithmetic circuits includes
a cross switch (cross switches 38), and
a positive resistor and a negative resistor (positive resistors 74 and negative resistors 76),
a difference value between resistance of the positive resistor and resistance of the negative resistor is inverted to be positive or negative in accordance with a corresponding weight bit (a structural difference between the claimed invention and the prior art must be present in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. Cross switches 38 in combination with resistors 76, 74 and corresponding weight bits meets the limitation as written),
the cross switch is configured to switch between a straight connection state and a reverse connection state in accordance with a corresponding input bit (Col. 7, Lines 40-59, “cross switch 38 having such configurations, when the value of the input signal is +1 [straight connection]…when the value of the input signal is -1 [reverse connection]”),
the cross switch is configured to, in the straight connection state (figure 5),
connect the positive resistor between the reference potential and the positive intermediate terminal (see figure 5), and
connect the negative resistor between the reference potential and the negative intermediate terminal (see figure 5), and
the cross switch is configured to, in the reverse connection state (figure 6),
connect the positive resistor between the reference potential and the negative intermediate terminal (see figure 6), and
connect the negative resistor between the reference potential and the positive intermediate terminal (see figure 6).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the arithmetic circuits of Marukame 947 in the neuron circuits of Marukame and Marukame 887, to achieve the benefit of realizing a nonlinear operation that simulates neurons with a simple configuration (Marukame 947, Col. 11, Lines 13-25).
Regaridng claim 4, as best understood based on the 35 U.S.C. 112(b) rejection made above, the combination of Marukame, Marukame 887, and Marukame 947 disclose the reservoir calculation device according to claim 3, and Marukame 947 continues to disclose, in figure 3 & 10, wherein the positive intermediate terminal outputs a positive intermediate voltage (positive intermediate terminals 46),
the negative intermediate terminal outputs a negative intermediate voltage (negative intermediate terminals 50), and
each of the neuron circuits further includes a selector (selector 112) configured to
select either the positive intermediate voltage or the negative intermediate voltage in accordance with one of the weight bits (Col. 11, Lines 46-55, “selector 112 selects any one of N word addresses at the time of performing the arithmetic operation. Upon reception of M input signals, the arithmetic unit 20 performs the product-sum operation (multiply accumulate operation) of the M input signals and the M coefficients at the selected word address by analog processing. The arithmetic unit 20 performs sign function processing on the signal corresponding to the multiply accumulate operation value to generate an output signal.”), and
output the selected voltage as the intermediate voltage (Col. 11, Lines 53-55, “The arithmetic unit 20 performs sign function processing on the signal corresponding to the multiply accumulate operation value to generate an output signal.”).
Regaridng claim 5, the combination of Marukame, Marukame 887, and Marukame 947 disclose the reservoir calculation device according to claim 2, and Marukame discloses, in figure 10, wherein the input bits include positive bits and negative bits (Para [0133], “neural network using a signal value expressed by binary values, an error value expressed by binary values, and a coefficient expressed by binary values is known. When computation is performed in such a neural network, the matrix computation unit 20 may have the configuration indicated by the second circuit example as illustrated in FIG. 16. Note that the present embodiment will illustrate an example using, as a signal expressed by binary values, a signal that switches H logic and L logic. However, the signal expressed by binary values may be a signal for switching 0 and 1, a signal for switching −1 and +1”), the positive bits expressing an absolute value of the level of the input signal by a number of first values when the level is positive (+1), each of the first value being either one of binary values (+1 or -1), the negative bits expressing an absolute value of the level of the input signal by a number of the first values when the level is negative (-1).
Allowable Subject Matter
Claims 8-11 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 12 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claim 12 would be allowed because none of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claim:
the adjustment method of adjusting the reservoir calculation device comprising acquiring the input signal; acquiring the output signal being output in response to the input signal provided to the input circuit; generating a restored signal by restoring the input signal on the basis of the output signal; and adjusting the time constant in the time constant circuit on the basis of a result of comparing the input signal and the restored signal.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Oshima (US 2022/0188617 A1) [Figure 1. Discloses a reservoir computer includes a reservoir unit including a plurality of neuron circuits and an output layer. Each of the neuron circuits includes a plurality of inputs, an analog output, and a digital output. Each of the plurality of inputs is supplied with the analog output of any one of other neuron circuits, the analog output of the neuron circuit itself, or an analog input signal from the outside. The neuron circuit includes a capacitor circuit, an amplifier, a capacitor memory circuit, a buffer circuit, and an analog-to-digital conversion circuit. The capacitor circuit includes a plurality of capacitors between the plurality of inputs and a single output, performs a product-sum calculation on analog signals supplied to the plurality of inputs together with the amplifier, and performs a non-linear calculation on a result of the product-sum calculation by using saturation characteristics of the amplifier.]
Nishi et al. (US 2021/0279559 A1) [Figure 6. Discloses a spiking neural network device according to an embodiment includes a synaptic element, a neuron circuit, a determinator, a synaptic depressor, and a synaptic potentiator. The synaptic element has a variable weight and outputs, in response to input of a first spike signal, a synaptic signal having intensity adjusted in accordance with the weight. The neuron circuit outputs a second spike signal in a case where the synaptic signal is inputted and a predetermined firing condition for the synaptic signal is satisfied. The determinator determines whether or not the weight is to be updated on a basis of an output frequency of the second spike signal by the neuron circuit. The synaptic depressor performs depression operation for depressing the weight in a case where it is determined that the weight is to be updated. The synaptic potentiator performs potentiating operation for potentiating the weight.]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER J PERENY whose telephone number is (571)272-4189. The examiner can normally be reached M-F 7:30-5.
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/TYLER J PERENY/Examiner, Art Unit 2836
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