DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 14 is objected to because of the following informalities:
CLAIM 14:
In line 5, before “gate” insert --second-- to correspond to the language of line 6 in claim 15.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 18 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ajit (2004/0119526).
In re Claim 18, Ajit teaches an output driver as seen in Figure 6 comprising: a pull-up driving circuit including a first PMOS transistor (301, see Figure 3) and a second PMOS transistor (303, see Figure 3) coupled in series between a supply voltage terminal (VDD0) and an output pad (309), and configured to perform a pull-up operation on the output pad (paragraph 49); and a dynamic gate bias circuit (405) coupled between a gate of the second PMOS transistor and the output pad, and configured to dynamically vary a level of a gate of the second PMOS transistor (paragraph 55).
In re Claim 19, Ajit teaches the dynamic gate bias circuit includes a third PMOS transistor (1301 as seen in Figure 18), wherein a gate of the third PMOS transistor is coupled to the supply voltage terminal (via “STRONGER DEVICE” as seen in Figure 11B), a source of the third PMOS transistor is coupled to the gate of the second PMOS transistor (as seen in Figure 18), and a drain of the third PMOS transistor is coupled to the output pad (as seen in Figure 18).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 11-15, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ajit (2004/0119526) in view of Kwong (2003/0071662).
In re Claim 1, Ajit teaches an output driver as seen in Figure 6 comprising: a pull-up driving circuit (301 and 303) coupled between a supply voltage terminal (VDD0) and an output pad (309), and configured to perform a pull-up operation on the output pad (paragraph 49); and a pull-down driving circuit (305) coupled between the output pad and a ground terminal, and configured to perform a pull-down operation on the output pad (paragraph 49).
Ajit fails to teach the high voltage protection circuit as claimed.
Kwong teaches an output pad 10 with a pull-up driving circuit 22 and pull-down driving circuit 24 as seen in Figure 2. Kwong further teaches a high voltage protection circuit 18 that comprises a resistor 20 and a transistor 23 connected in series to handle ESD pulses on the output pad 10 (paragraph 20).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the high voltage protection circuit as taught by Kwong with the output driver of Ajit since Kwong teaches it provides protection against ESD pulses on the output pad.
Ajit as modified by Kwong discloses the claimed invention except for including a string of resistors. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include further resistors since it is was known in the art that a single resistor can be replaced with a number of resistors in series to constitute an equivalent overall resistance and that adding further resistors in series increases the overall resistance to reduce higher levels of current.
In re Claim 2, Kwong teaches that the path to ground via transistor 23 is not formed until an irregular high voltage (i.e., higher than a supply voltage) is provided on the output pad 10 (paragraph 5).
In re Claim 11, Ajit teaches a floating well voltage generating circuit (401) coupled between the supply voltage terminal and the output pad (as seen in Figure 6), and configured to generate a floating well voltage (paragraph 50), wherein the pull-up driving circuit includes a first PMOS transistor (301) and a second PMOS transistor (303), and wherein N-type well regions of the first PMOS transistor and the second PMOS transistor receive the floating well voltage in common (paragraph 50).
In re Claim 12, Ajit teaches the floating well voltage generating circuit as seen in Figure 10 includes: a fourth PMOS transistor 1003 having a gate coupled to the output pad 309 (physically connected via 303), a source coupled to the supply voltage terminal VDD0, and a drain coupled to an output line outputting the floating well voltage at 1005; and a fifth PMOS transistor 1001 having a gate coupled to the supply voltage terminal (via “STRONGER DEVICE” as seen in Figure 11B), a source coupled to the output line outputting the floating well voltage at 1005, and a drain coupled to the output pad.
In re Claim 13, Ajit teaches wherein N-type well regions of the fourth PMOS transistor 1003 and the fifth PMOS transistor 1001 receive the floating well voltage in common as seen in Figure 10.
In re Claim 14, Ajit teaches the pull-up driving circuit including a first PMOS transistor (301, see Figure 3) and a second PMOS transistor (303, see Figure 3); and a dynamic gate bias circuit (405) coupled between a gate of the second PMOS transistor and the output pad, and configured to dynamically vary a level of a gate of the second PMOS transistor (paragraph 55).
In re Claim 15, Ajit teaches the dynamic gate bias circuit includes a sixth PMOS transistor (1301 as seen in Figure 18), wherein a gate of the sixth PMOS transistor is coupled to the supply voltage terminal (via “STRONGER DEVICE” as seen in Figure 11B), a source of the sixth PMOS transistor is coupled to the gate of the second PMOS transistor (as seen in Figure 18), and a drain of the sixth PMOS transistor is coupled to the output pad (as seen in Figure 18).
In re Claim 17, Ajit teaches that the pull-up driving circuit as seen in Figure 6 includes: a first PMOS transistor 301 coupled between the supply voltage terminal VDD0 and a first node; and a second PMOS transistor 303 coupled between the first node and the output pad 309, and wherein the pull-down driving circuit includes: a first NMOS transistor 305 coupled between the output pad 309 and a second node; and a second NMOS transistor 307 coupled between the second node and the ground terminal.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ajit (2004/0119526) in view of Kwong (2003/0071662) as applied to claim 1 above and further in view of Ker et al (6,249,410).
In re Claim 3, Kwong teaches the transistor 23 is diode connected. Though Kwong does not teach the inclusion of additional diode connected transistors.
Ker teaches additional diode connected transistors can be connected in series to increase the threshold voltage to the desired level at which the ESD voltage is shunted as seen in Figures 13-15 (col 12 lines 20-38).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include further diode connected transistors as taught by Ker in order to set the desired threshold for an ESD event.
Allowable Subject Matter
Claims 4-10, 16, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In re Claim 4, Ajit teaches a control circuit (405, 407, 409, and 411) configured to provide gate signals to the pull-up and pull-down driving circuits as seen in Figure 6, wherein a voltage selection signal generating circuit 405 outputs a voltage selection signal VGP1 that changes as a result of the magnitude of the pad voltage (paragraph 56). However, as seen in Figure 7 the voltage of signal VGP1 remains at a logic high level (VDD0) or higher and does not reach what can be considered a logic low level.
Claims 5-10 are dependent on claim 4.
In re Claims 16 and 20, Ajit fails to teach that the PMOS 1301 of the gate biasing circuit receives a voltage at an N-type well region from the floating well voltage generating circuit 401.
Conclusion
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/CHRISTOPHER J CLARK/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838