DETAILED ACTION
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Pflum (US 5822560 A) in view of Hill (US 20070050600 A1).
Regarding Claim 1, Pflum teaches an apparatus comprising: scheduling circuitry configured to schedule one or more operations to be performed in at least a given cycle (
Pflum discloses, “Superscalar microprocessors achieve high performance by executing multiple instructions during a clock cycle and by specifying the shortest possible clock cycle consistent with the design,” Col 1, Lines 13-16.);
determination circuitry configured to identify one of the one or more operations as a variable-issue operation and to perform a determination of whether the variable-issue operation is a single-issue operation or a multiple-issue operation (
Pflum discloses, “The instruction categorization scheme includes three categories: single dispatch, multiple dispatch, and microcode. Single dispatch instructions are performed in one functional unit. Conversely, multiple dispatch instructions are conveyed to multiple functional units, each of which perform a portion of the multiple dispatch instruction,” Col 2, Lines 66-67 and Col 3, Lines 1-5,
“Having multiple control vectors per functional unit may also increase performance without undue complexity increase in the functional unit. Moderately complex instructions may be categorized as single dispatch by employing the multiple control vectors. Instructions which might otherwise be categorized as microcode instructions may be categorized as multiple dispatch by employing the multiple control vectors available in the multiple functional units. The variable dispatch, variable control vector protocol thereby allows considerable freedom in optimizing the complexity and performance of a microprocessor employing the apparatus. High operating frequencies may be enabled due to the simplification of hardware while maintaining instruction throughput at rates higher than a single dispatch/microcode approach may allow,” Col 3, Lines 40-54,
“Broadly speaking, the present invention contemplates a method for efficient instruction execution in a microprocessor comprising several steps. An instruction is classified into one of at least three categories. The categories include a single dispatch category, a multiple dispatch category, and a microcode instruction category. The instruction is routed to a single issue position if the instruction is in the single dispatch category. The issue position executes the instruction via at least one control vector. Similarly, the instruction is routed to at least two issue positions if the instruction is in the multiple dispatch category. Each issue position executes a portion of the instruction via at least one control vector,” Col 3, Lines 55-67.
“Coupled to the microcode unit and coupled to provide instructions to the first and second issue positions, the instruction scanning unit is configured to categorize the instruction as in one of a single dispatch category, the multiple dispatch category, and the microcode instruction category,” Col 4, Lines 19-23.
The claimed “variable-issue operation” is mapped to a disclosed “variable dispatch instruction”.
The claimed “single-issue operation” is mapped to the disclosed “single dispatch instruction”. This is a single issue operation because it is routed to a single issue position.
The claimed “multiple-issue operation” is mapped to the disclosed “multiple dispatch instruction”. This is a multiple issue operation because it is routed to at least two issue positions, which is multiple issue.
The disclosed “instruction scanning unit” determines whether an identified instruction is a single dispatch instruction or a multiple dispatch instruction.
This is consistent with Pages 5 and 7 of the present application’s specification, which state that “an operation may only be performed (e.g. issued) if there are no other operations being performed (e.g. issued) in the same cycle(s) (referred to as a single- issue operation herein)… In other examples, an operation may be performed alongside other operations in the same cycle(s) (referred to as a multiple- issue operation herein),” and “A variable-issue operation is an operation that could be scheduled as either a single-issue operation or multiple-issue operation, for example in dependence on the state of the program at runtime. For example, in some circumstances the variable-issue operation can be scheduled as a multiple-issue operation, whereas in other circumstances the same variable-issue operation is only able to be scheduled as a single-issue operation.”);
the scheduling circuitry is configured to schedule the variable-issue operation to be performed in at least the given cycle (
Pflum discloses, “Superscalar microprocessors achieve high performance by executing multiple instructions during a clock cycle and by specifying the shortest possible clock cycle consistent with the design,” Col 1, Lines 13-16.),
and in response to the determination being that the variable-issue operation is the multiple-issue operation, the determination circuitry is configured to cause the scheduling circuitry to schedule at least one of the one or more operations other than the variable-issue operation to be performed in at least the given cycle (
Pflum discloses, “The apparatus described herein enhances the performance of the microprocessor without introducing undue complication in the functional units included therein. Where conventional methods would categorize all instructions as either single dispatch or microcode, the apparatus allows for more flexibility by including a multiple dispatch instruction category. The flexibility may be used to significant advantage by the apparatus. For example, instruction throughput may be enhanced by dispatching single dispatch instructions concurrently with multiple dispatch instructions. Because the multiple dispatch instruction occupy a predefined fixed number of functional units, single dispatch instructions may be concurrently dispatched upon detection of the multiple dispatch instructions,” Col 3, Lines 24-37, and
“Instruction scanning unit 52 identifies multiple dispatch instructions by partially decoding the instructions and routes them to instruction alignment unit 18 or MROM unit 34, depending upon the embodiment. The multiple dispatch instructions are tagged as being multiple dispatch such that they are routed to the appropriate number of issue positions,” Col 14, Lines 33-39.
In response to the disclosed “instruction scanning unit” determining that the instructions are multiple dispatch instructions, it allows other instructions to be performed concurrently in order to enhance instruction throughput.).
Pflum does not teach wherein in response to the determination being that the variable-issue operation is the single-issue operation, the determination circuitry is configured to cause the scheduling circuitry to suppress scheduling of the one or more operations other than the variable- issue operation to be performed in at least the given cycle.
However, Hill teaches wherein in response to the determination being that the variable-issue operation is the single-issue operation, the determination circuitry is configured to cause the scheduling circuitry to suppress scheduling of the one or more operations other than the variable- issue operation to be performed in at least the given cycle (
Hill discloses, “In one embodiment, the data processing apparatus is operable to issue multiple instructions in a single processing cycle, the decode/issue logic is operable to receive and decode the multiple instructions, the execution logic comprises multiple execution pipelines operable to execute the multiple instructions concurrently and the issue logic is responsive to the determination made by the throttle logic to issue only a single decoded instruction during a single processing cycle,” ¶ 0031,
“Hence, when it is determined that the issue of multiple instructions in the same cycle will result in the capacity being exceeded, the throttle logic causes only a single instruction to be issued to the execution logic in a single processing cycle. Typically, one of the execution pipelines will be designated for handling such single-issue instructions,” ¶ 0032.
Here, if the number of instructions that would be scheduled in a cycle exceeds a threshold, a single instruction is issued instead, while the other instructions are suppressed.
This is consistent with pages 5 and 7 of the present application’s specification, which state that “When a single-issue operation is scheduled to a processing queue, the scheduling of other operations to be performed in the same cycle is suppressed,” and “in response to the variable-issue operation requiring use of a threshold number of the operational units, the determination circuitry is configured to perform the determination such that the determination is that the variable-issue operation is a single-issue operation.”
After the combination of Pflum with Hill, Pflum’s scheduling of operations can be suppressed until another operation is complete, as specified by Hill.).
Pflum and Hill are both considered to be analogous to the claimed invention because they are in the same field of computer task scheduling. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pflum to incorporate the teachings of Hill and provide wherein the determination circuitry is configured to cause the scheduling circuitry to suppress scheduling of the one or more operations other than the variable-issue operation to be performed in at least the given cycle. Doing so would help prevent the circuitry from becoming overloaded due to taking in too many instructions at a time. (Hill discloses, “Hence, when it is determined that the issue of multiple instructions in the same cycle will result in the capacity being exceeded, the throttle logic causes only a single instruction to be issued to the execution logic in a single processing cycle. Typically, one of the execution pipelines will be designated for handling such single-issue instructions,” ¶ 0032.).
Claims 19 and 20 are a method claim and a non-transitory computer-readable medium claim, respectively, corresponding to the apparatus Claim 1 (Col 1, Lines 13-24 of Pflum.). Therefore, Claims 19 and 20 are rejected for the same reasons set forth in the rejection of Claim 1.
Regarding Claim 2, Pflum in view of Hill teaches the apparatus of claim 1, comprising: execution circuitry configured to perform scheduled operations (
Pflum discloses, “Superscalar microprocessors achieve high performance by executing multiple instructions during a clock cycle and by specifying the shortest possible clock cycle consistent with the design,” Col 1, Lines 13-16, and “Instruction scanning unit 52 identifies multiple dispatch instructions by partially decoding the instructions and routes them to instruction alignment unit 18 or MROM unit 34, depending upon the embodiment,” Col 14, Lines 33-36.);
and the determination circuitry is configured to perform the determination by detecting whether the variable-issue operation and the at least one of the one or more operations other than the variable-issue operation can be performed by the execution circuitry in at least the given cycle (
Pflum discloses, “The number of concurrently dispatched single dispatch instructions may be up to the number of issue positions minus the number of issue positions occupied by the multiple dispatch instruction. Because multiple dispatch instructions occupy a predetermined fixed number of issue positions, the number of concurrently dispatched single dispatch instructions may be determined upon detection of the multiple dispatch instruction. In contrast, microcode instructions may be dispatched to any number of issue positions according to the routine stored in MROM unit 34. Therefore, microcode instructions are dispatched without concurrent dispatch of other instructions,” Col 14, Lines 61-67, Col 15, Lines 1-6.
Here, the variable issue operation can be any one of the instructions being dispatched in the current cycle. The at least one of the one or more operations other than the variable-issue operation refer to all of the other instructions being dispatched in the same cycle as the variable-issue operation.
Here, a number of issue positions occupied by a multiple-dispatch instruction is detected, and then it is determined whether there are remaining available issue positions for other instructions to occupy. If the number of unoccupied issue positions is 0, then other single dispatch instructions cannot be performed concurrently in the same cycle as the multiple dispatch instruction.).
Regarding Claim 3, Pflum in view of Hill teaches the apparatus of claim 2, wherein the execution circuitry comprises a plurality of operational units (
Pflum discloses, “Turning now to FIG. 1, a block diagram of one embodiment of a microprocessor 10 is shown. Microprocessor 10 includes a prefetch/predecode unit 12, a branch prediction unit 14, an instruction cache 16, an instruction alignment unit 18, a plurality of decode units 20A-20C, a plurality of reservation stations 22A-22C, a plurality of functional units 24A-24C, a load/store unit 26, a data cache 28, a register file 30, a reorder buffer 32, and an MROM unit 34,” Col 3, Lines 32-39.);
and in response to the variable-issue operation requiring use of a threshold number of the operational units, the determination circuitry is configured to perform the determination such that the determination is that the variable-issue operation is a single- issue operation (
Hill discloses, “In one embodiment, the data processing apparatus is operable to issue multiple instructions in a single processing cycle, the decode/issue logic is operable to receive and decode the multiple instructions, the execution logic comprises multiple execution pipelines operable to execute the multiple instructions concurrently and the issue logic is responsive to the determination made by the throttle logic to issue only a single decoded instruction during a single processing cycle,” ¶ 0031,
“Hence, when it is determined that the issue of multiple instructions in the same cycle will result in the capacity being exceeded, the throttle logic causes only a single instruction to be issued to the execution logic in a single processing cycle. Typically, one of the execution pipelines will be designated for handling such single-issue instructions,” ¶ 0032.
Here, if the number of instructions that would be scheduled in a cycle exceeds a threshold, or all of the operational units of the circuitry would end up being used, a single instruction is issued instead, while the other instructions are suppressed.
This is consistent with pages 5 and 7 of the present application’s specification, which state that “When a single-issue operation is scheduled to a processing queue, the scheduling of other operations to be performed in the same cycle is suppressed,” and “in response to the variable-issue operation requiring use of a threshold number of the operational units, the determination circuitry is configured to perform the determination such that the determination is that the variable-issue operation is a single-issue operation.”.).
Pflum and Hill are both considered to be analogous to the claimed invention because they are in the same field of computer task scheduling. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pflum to incorporate the teachings of Hill and provide in response to the variable-issue operation requiring use of a threshold number of the operational units, the determination circuitry is configured to perform the determination such that the determination is that the variable-issue operation is a single- issue operation. Doing so would help prevent the circuitry from becoming overloaded due to taking in too many instructions at a time. (Hill discloses, “Hence, when it is determined that the issue of multiple instructions in the same cycle will result in the capacity being exceeded, the throttle logic causes only a single instruction to be issued to the execution logic in a single processing cycle. Typically, one of the execution pipelines will be designated for handling such single-issue instructions,” ¶ 0032.).
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Pflum (US 5822560 A) in view of Hill (US 20070050600 A1) and Anderson (US 20200210198 A1).
Regarding Claim 4, Pflum in view of Hill teaches the apparatus of claim 1, wherein in response to the variable-issue operation: being decodedperform the determination and determine that the variable-issue operation is the multiple-issue operation (
Pflum discloses, “Instruction scanning unit 52 identifies multiple dispatch instructions by partially decoding the instructions and routes them to instruction alignment unit 18 or MROM unit 34, depending upon the embodiment. The multiple dispatch instructions are tagged as being multiple dispatch such that they are routed to the appropriate number of issue positions,” Col 14, Lines 33-39.).
Pflum does not teach that the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to the variable-issue operation: being logically equivalent to a NOP, being operationally null, or having nothing to do.
However, Anderson teaches an operation being logically equivalent to a NOP, being operationally null, or having nothing to do (
Anderson discloses, “The instructions executing in parallel constitute an execute packet. In this example, an execute packet can contain up to sixteen 32-bit wide slots for sixteen instructions. No two instructions in an execute packet may use the same functional unit. A slot is one of five types: 1) a self-contained instruction executed on one of the functional units of processor core 110 (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, D2 unit 226, L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245 and P unit 246); 2) a unitless instruction such as a NOP (no operation) instruction or multiple NOP instructions; 3) a branch instruction; 4) a constant field extension; and 5) a conditional code extension. Some of these slot types will be further explained hereinbelow,” ¶ 0060.
Here, a unitless instruction comprising multiple NOP instructions can be considered a multiple-issue operation.
After the combination of Pflum in view of Hill, with Anderson, the multiple-issue operation can be equivalent to multiple NOP instructions, and in response to the variable-issue operation being received and then determined that it is logically equivalent to a NOP, as specified by Anderson, it can then be determined that the variable-issue operation is the multiple-issue operation.).
Pflum in view of Hill, and Anderson are both considered to be analogous to the claimed invention because they are in the same field of computer task scheduling. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pflum in view of Hill to incorporate the teachings of Anderson and provide that the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to the variable-issue operation: being logically equivalent to a NOP, being operationally null, or having nothing to do. Doing so would help improve parallel processing by allowing other operations to be performed in the same cycle as a null operation. (Anderson discloses, “By overlapping the execution of instructions, we increase the rate at which the processor can execute instructions,” ¶ 0004.).
Regarding Claim 6, Pflum in view of Hill teaches the apparatus of claim 1, wherein in response to the determination that the variable-issue operation is the multiple-issue operation (
Pflum discloses, “Instruction scanning unit 52 identifies multiple dispatch instructions by partially decoding the instructions and routes them to instruction alignment unit 18 or MROM unit 34, depending upon the embodiment. The multiple dispatch instructions are tagged as being multiple dispatch such that they are routed to the appropriate number of issue positions,” Col 14, Lines 33-39.).
Pflum in view of Hill does not teach that the scheduling circuitry is configured to schedule the variable-issue operation as a null operation to be performed in at least the given cycle.
However, Anderson teaches that the scheduling circuitry is configured to schedule the variable-issue operation as a null operation to be performed in at least the given cycle (
Anderson discloses, “For an instruction which takes multiple cycles to complete, if a subsequent instruction attempts to read the destination of the first instruction within the delay slots of that first instruction, the CPU pipeline will automatically insert NOP cycles until the instruction which will write that register has completed,” ¶ 0070.
Pages 9-10 of the present application’s specification state that “In such examples, if the variable-issue operation is determined to be logically equivalent to a NOP, operationally null or would otherwise not do anything, it is replaced with a null operation by the scheduling circuitry. A null operation is a multiple-issue operation, since it can be executed in parallel because it does not require use of any execution resources.”
Since an NOP operation is equivalent to being operationally null, Anderson’s insertion of NOP cycles is an insertion of null operations.
After the combination of Pflum in view of Hill, with Anderson, in response to detecting a multiple-dispatch instruction according to Pflum in view of Hill, NOP operations will be scheduled to be performed in at least the given cycle as specified by Anderson.).
Pflum in view of Hill, and Anderson are both considered to be analogous to the claimed invention because they are in the same field of computer task scheduling. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pflum in view of Hill to incorporate the teachings of Anderson and provide that the scheduling circuitry is configured to schedule the variable-issue operation as a null operation to be performed in at least the given cycle. Doing so would help improve parallel processing by allowing other operations to be performed in the same cycle as a null operation. (Anderson discloses, “By overlapping the execution of instructions, we increase the rate at which the processor can execute instructions,” ¶ 0004.).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Pflum (US 5822560 A) in view of Hill (US 20070050600 A1) and Narayan (US 5822559 A).
Regarding Claim 5, Pflum in view of Hill teaches the apparatus of claim 1, wherein the variable-issue operation is configured, when executed, to operate on a controllable number of bytes of a memory (
Pflum discloses, “A floating point load/store operation may be a single precision value comprising 32 bits; a double precision value comprising 64 bits; or an extended precision value comprising 80 bits. Because integer values are at most 32 bits, microprocessor 10 executes floating point loads and stores in 32 bit portions (and a 16 bit portion for the extend precision operations). Therefore, a single precision access comprises one 32 bit portion; a double precision access comprises two 32 bit portions; and an extended precision access comprises two 32 bit accesses and one 16 bit access,” Col 24, Lines 1-10.
In Pflum, since the number of bytes of a memory being operated on by an operation varies depending on the precision mode, the number of bytes of a memory is thus controllable.);
and the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to being decoded (
Pflum discloses, “Instruction scanning unit 52 identifies multiple dispatch instructions by partially decoding the instructions and routes them to instruction alignment unit 18 or MROM unit 34, depending upon the embodiment. The multiple dispatch instructions are tagged as being multiple dispatch such that they are routed to the appropriate number of issue positions,” Col 14, Lines 33-39.).
Pflum in view of Hill does not teach that the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to the controllable number of bytes on which the variable-issue operation is performed being zero.
However, Narayan teaches the controllable number of bytes on which the variable-issue operation is performed being zero (
Narayan discloses, “The way prediction should provide the byte position of the return instruction so that the ICPDAT can invalidate all followed instructions. For speed, another 4 bits are needed to indicate the byte position pointer for the instruction after the taken branch instruction for ICPDAT. The ICPDAT can decode and invalidate the pre-decode data directly from this 4-bit branch pointer. If the 4-bit branch pointer is all zeros, no invalidation of the pre-decode data is needed,” Col 46, Lines 28-36.
Here, an invalidation operation is performed on pre-code data from a 4-bit branch pointer. If the bits are all zeroes, the controllable number of bytes on which this operation is performed is thus zero.
Since this is essentially a NOP operation, this can be considered a multiple-issue operation, based on the rejection analysis for the previous Claim 4.
After the combination of Pflum in view of Hill, with Narayan, in response to the controllable number of bytes on which the variable-issue operation is performed being zero, as specified by Narayan, it can then be determined that the variable-issue operation is the multiple-issue operation.).
Pflum in view of Hill, and Narayan are both considered to be analogous to the claimed invention because they are in the same field of computer task scheduling. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to have modified Pflum in view of Hill to incorporate the teachings of Narayan and provide that the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to the controllable number of bytes on which the variable-issue operation is performed being zero. Doing so would help prevent unnecessary operations from being executed by scheduling the operation as a null operation, in order to allow for other operations to be performed in the same cycle to increase parallelism and efficiency (Narayan discloses, “If the 4-bit branch pointer is all zeros, no invalidation of the pre-decode data is needed,” Col 46, Lines 35-36.).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Pflum (US 5822560 A) in view of Hill (US 20070050600 A1) and Brown (US 6240508 B1).
Regarding Claim 7, Pflum in view of Hill teaches the apparatus of claim 1, wherein the determination circuitry is configured to identify a prologue operation preceding the variable-issue operation (
Pflum discloses, “Instruction alignment unit 18 utilizes the scanning data to align an instruction to each of decode units 20. In one embodiment, instruction alignment unit 18 aligns instructions from three sets of eight instruction bytes to decode units 20. Instructions are selected independently from each set of eight instruction bytes into preliminary issue positions. The preliminary issue positions are then merged to a set of aligned issue positions corresponding to decode units 20, such that the aligned issue positions contain the three instructions which are prior to other instructions within the preliminary issue positions in program order,” Col 8, Lines 58-67 and Col 9, Line 1.
The claimed “prologue operation” is mapped to the disclosed alignment operation performed on the instruction, before the instruction is executed.
This is in line with Page 12 of the present application’s specification, which states that “In some examples, the prologue operation is configured to perform an alignment process such that the variable-issue operation, when performed, is aligned with a memory boundary…”),
and the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to being decoded (
Pflum discloses, “Instruction scanning unit 52 identifies multiple dispatch instructions by partially decoding the instructions and routes them to instruction alignment unit 18 or MROM unit 34, depending upon the embodiment. The multiple dispatch instructions are tagged as being multiple dispatch such that they are routed to the appropriate number of issue positions,” Col 14, Lines 33-39.).
Pflum in view of Hill does not teach that the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to an extent to which the prologue operation is performed.
However, Brown teaches an extent to which the prologue operation is performed (
Brown discloses, “When write data is latched in the EM-latch 74, the 4-way byte barrel shifter 263 associated with the EM-latch 74 rotates the data into proper alignment based on the lower two bits of the corresponding address. The result of this data rotation is that all bytes of data are now in the correct byte positions relative to memory longword boundaries,” Col 43, Lines 43-48.
Here, an alignment operation is performed on data.
The claimed “extent to which the prologue operation is performed” is mapped to the number of bytes that are now in the correct byte positions after the alignment operation.
After the combination of Pflum in view of Hill, with Brown, in response to detecting that all the number of bytes are already in the correct positions, according to Brown, the current instruction is determined to be a multiple-issue operation according to Pflum in view of Hill.).
Pflum in view of Hill, and Brown are both considered to be analogous to the claimed invention because they are in the same field of computer task scheduling. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to have modified Pflum in view of Hill to incorporate the teachings of Brown and provide that the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to an extent to which the prologue operation is performed. Doing so would help ensure that the data of the instruction is aligned so that execution of the instruction does not result in erroneous results. (Brown discloses, “When write data is latched in the EM-latch 74, the 4-way byte barrel shifter 263 associated with the EM-latch 74 rotates the data into proper alignment based on the lower two bits of the corresponding address. The result of this data rotation is that all bytes of data are now in the correct byte positions relative to memory longword boundaries,” Col 43, Lines 43-48.).
Regarding Claim 8, Pflum in view of Hill, and Brown teaches the apparatus of claim 7, wherein the prologue operation is configured, when performed, to operate on an initial number of bytes of the memory (
Pflum discloses, “Instruction alignment unit 18 utilizes the scanning data to align an instruction to each of decode units 20. In one embodiment, instruction alignment unit 18 aligns instructions from three sets of eight instruction bytes to decode units 20. Instructions are selected independently from each set of eight instruction bytes into preliminary issue positions. The preliminary issue positions are then merged to a set of aligned issue positions corresponding to decode units 20, such that the aligned issue positions contain the three instructions which are prior to other instructions within the preliminary issue positions in program order,” Col 8, Lines 58-67 and Col 9, Line 1.
The claimed “prologue operation” is mapped to the disclosed alignment operation performed on the instruction, before the instruction is executed.
This is in line with Page 12 of the present application’s specification, which states that “In some examples, the prologue operation is configured to perform an alignment process such that the variable-issue operation, when performed, is aligned with a memory boundary…”);
and the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to the initial number of bytes being such that there is nothing left for the variable-issue operation to do (
Pflum teaches that the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to being decoded, disclosing, “Instruction scanning unit 52 identifies multiple dispatch instructions by partially decoding the instructions and routes them to instruction alignment unit 18 or MROM unit 34, depending upon the embodiment. The multiple dispatch instructions are tagged as being multiple dispatch such that they are routed to the appropriate number of issue positions,” Col 14, Lines 33-39.
Brown teaches the initial number of bytes being such that there is nothing left for the variable-issue operation to do, disclosing, “When the Dest-Addr command completes in S5, it is turned into a NOP command in S6 because no further processing can take place without the actual write data,” Col 44, Lines 14-17.
Here, there is nothing left for subsequent operations to do without the actual write data.
After the combination of Pflum in view of Hill, with Brown, in response to detecting the initial number of bytes being such that there is nothing left for subsequent operations to do, according to Brown, the current instruction is determined to be a multiple-issue operation according to Pflum in view of Hill.).
Pflum in view of Hill, and Brown are both considered to be analogous to the claimed invention because they are in the same field of computer task scheduling. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to have modified Pflum in view of Hill to incorporate the teachings of Brown and provide that the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to the initial number of bytes being such that there is nothing left for the variable-issue operation to do. Doing so would help allow for scheduling the operation as a null operation in order to enable scheduling other operations in the same cycle, which increases parallelism and efficiency. (Brown discloses, “When the Dest-Addr command completes in S5, it is turned into a NOP command in S6 because no further processing can take place without the actual write data,” Col 44, Lines 14-17.).
Claims 9, and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Pflum (US 5822560 A) in view of Hill (US 20070050600 A1), Brown (US 6240508 B1), and Mukherjee (US 20200133680 A1).
Regarding Claim 9, Pflum in view of Hill and Brown teaches the apparatus of claim 7, wherein the prologue operation and the variable-issue operation are generated (
Pflum discloses, “Instructions fetched from instruction cache 16 are conveyed to instruction alignment unit 18. As instructions are fetched from instruction cache 16, the corresponding predecode data is scanned to provide information to instruction alignment unit 18 (and to MROM unit 34) regarding the instructions being fetched. Instruction alignment unit 18 utilizes the scanning data to align an instruction to each of decode units 20,” Col 8, Lines 53-60.).
Pflum in view of Hill and Brown does not teach wherein the prologue operation and the variable-issue operation are generated in response to decoding of at least one memory block instruction indicating a total number of bytes of the memory.
However, Mukherjee teaches decoding of at least one memory block instruction indicating a total number of bytes of the memory (
Mukherjee discloses, “At each level, the cache system will load blocks of data or instructions into entries and evict blocks of data or instructions from entries in units of memory blocks (also called “cache lines” or “cache blocks”). Each memory block includes a number of words of data or instructions, each word consisting of a predetermined number of bytes. A memory page typically has data or instructions from many memory blocks,” ¶ 0002.
After the combination of Pflum in view of Hill and Brown, with Mukherjee, the prologue operation and the variable-issue operation from Pflum in view of Hill and Brown, are generated in response to decoding of at least one memory block instruction indicating a total number of bytes of the memory, as specified by Muhkerjee.).
Pflum in view of Hill and Brown, and Mukherjee are both considered to be analogous to the claimed invention because they are in the same field of computer processor instructions. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to have modified Pflum in view of Hill and Brown to incorporate the teachings of Mukherjee and provide wherein the prologue operation and the variable-issue operation are generated in response to decoding of at least one memory block instruction indicating a total number of bytes of the memory. Doing so would help provide an efficient means of storing the instructions. (Mukherjee discloses, “At each level, the cache system will load blocks of data or instructions into entries and evict blocks of data or instructions from entries in units of memory blocks (also called “cache lines” or “cache blocks”). Each memory block includes a number of words of data or instructions, each word consisting of a predetermined number of bytes. A memory page typically has data or instructions from many memory blocks,” ¶ 0002.).
Regarding Claim 11, Pflum in view of Hill, Brown, and Mukherjee teaches the apparatus of claim 9, wherein the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to the prologue operation operating on all of the total number of bytes of the memory (
Pflum teaches that the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to being decoded, disclosing, “Instruction scanning unit 52 identifies multiple dispatch instructions by partially decoding the instructions and routes them to instruction alignment unit 18 or MROM unit 34, depending upon the embodiment. The multiple dispatch instructions are tagged as being multiple dispatch such that they are routed to the appropriate number of issue positions,” Col 14, Lines 33-39.
Brown teaches the prologue operation operating on all of the total number of bytes of the memory, disclosing, “When write data is latched in the EM-latch 74, the 4-way byte barrel shifter 263 associated with the EM-latch 74 rotates the data into proper alignment based on the lower two bits of the corresponding address. The result of this data rotation is that all bytes of data are now in the correct byte positions relative to memory longword boundaries,” Col 43, Lines 43-48.
Here, an alignment operation is performed on all bytes of the data.
After the combination of Pflum in view of Hill, with Brown, in response to detecting that all the number of bytes are aligned, according to Brown, the current instruction is determined to be a multiple-issue operation according to Pflum in view of Hill.).
Pflum in view of Hill, and Brown are both considered to be analogous to the claimed invention because they are in the same field of computer task scheduling. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to have modified Pflum in view of Hill to incorporate the teachings of Brown and provide wherein the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to the prologue operation operating on all of the total number of bytes of the memory. Doing so would help allow for scheduling the operation as a null operation in order to enable scheduling other operations in the same cycle, which increases parallelism and efficiency. (Brown discloses, “When the Dest-Addr command completes in S5, it is turned into a NOP command in S6 because no further processing can take place without the actual write data,” Col 44, Lines 14-17.).
Regarding Claim 12, Pflum in view of Hill, Brown, and Mukherjee teaches the apparatus of claim 9, wherein the prologue operation is configured to perform an alignment process such that the variable-issue operation, when performed, is aligned with a memory boundary (
Brown discloses, “The supplied data is properly rotated via rotator 258 to the memory aligned longword boundary,” Col 43, Lines 26-28.
Here, an alignment is performed so that the data is then aligned with a memory aligned longward boundary.
This is in line with Page 12 of the present application’s specification, which states that “In some examples, the prologue operation is configured to perform an alignment process such that the variable-issue operation, when performed, is aligned with a memory boundary…”),
and the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to the alignment process comprising operating on all of the total number of bytes of memory (
Pflum teaches that the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to being decoded, disclosing, “Instruction scanning unit 52 identifies multiple dispatch instructions by partially decoding the instructions and routes them to instruction alignment unit 18 or MROM unit 34, depending upon the embodiment. The multiple dispatch instructions are tagged as being multiple dispatch such that they are routed to the appropriate number of issue positions,” Col 14, Lines 33-39.
Brown teaches the alignment process comprising operating on all of the total number of bytes of the memory, disclosing, “When write data is latched in the EM-latch 74, the 4-way byte barrel shifter 263 associated with the EM-latch 74 rotates the data into proper alignment based on the lower two bits of the corresponding address. The result of this data rotation is that all bytes of data are now in the correct byte positions relative to memory longword boundaries,” Col 43, Lines 43-48.
Here, an alignment operation is performed on all bytes of the data.
After the combination of Pflum in view of Hill, with Brown, in response to detecting that all the number of bytes are aligned, according to Brown, the current instruction is determined to be a multiple-issue operation according to Pflum in view of Hill.).
Pflum in view of Hill, and Brown are both considered to be analogous to the claimed invention because they are in the same field of computer task scheduling. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to have modified Pflum in view of Hill to incorporate the teachings of Brown and provide wherein the prologue operation is configured to perform an alignment process such that the variable-issue operation, when performed, is aligned with a memory boundary, and the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to the alignment process comprising operating on all of the total number of bytes of memory. Doing so would help allow for scheduling the operation as a null operation in order to enable scheduling other operations in the same cycle, which increases parallelism and efficiency. (Brown discloses, “When the Dest-Addr command completes in S5, it is turned into a NOP command in S6 because no further processing can take place without the actual write data,” Col 44, Lines 14-17.).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Pflum (US 5822560 A) in view of Hill (US 20070050600 A1), Brown (US 6240508 B1), Mukherjee (US 20200133680 A1), and Ashwathnarayan (US 20200364088 A1).
Regarding Claim 10, Pflum in view of Hill, Brown, and Mukherjee teaches the apparatus of claim 9. Pflum in view of Hill, Brown, and Mukherjee does not teach wherein the memory block instruction is either a memory block copy instruction or a memory block set instruction.
However, Ashwathnarayan teaches wherein the memory block instruction is either a memory block copy instruction or a memory block set instruction (
Ashwathnarayan discloses, “In at least one embodiment, once mapped as a parallel computing platform and application programming interface model object, applications can use pointers/arrays as regular ones and perform parallel computing platform and application programming interface model operations like memcpy or memset and pass to parallel computing platform and application programming interface model kernels,” ¶ 0094.).
Pflum in view of Hill, Brown, and Mukherjee, and Ashwathnarayan are both considered to be analogous to the claimed invention because they are in the same field of computer resources. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to have modified Pflum in view of Hill, Brown, and Mukherjee to incorporate the teachings of Ashwathnarayan and provide wherein the memory block instruction is either a memory block copy instruction or a memory block set instruction. Doing so would help allow for more efficient memory operations. (Ashwathnarayan discloses, “In at least one embodiment, once mapped as a parallel computing platform and application programming interface model object, applications can use pointers/arrays as regular ones and perform parallel computing platform and application programming interface model operations like memcpy or memset and pass to parallel computing platform and application programming interface model kernels,” ¶ 0094.).
Claims 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Pflum (US 5822560 A) in view of Hill (US 20070050600 A1), Brown (US 6240508 B1), and ARM (“ARM Exception Handling”).
Regarding Claim 13, Pflum in view of Hill and Brown teaches the apparatus of claim 7, wherein the determination circuitry is configured to identify an epilogue operation following the variable-issue operation (
Pflum discloses, “A completed instruction is deleted from reservation station 22A by shifting down the instruction information stored within subsequent reservation station entries 90. For example, if the instruction stored within reservation station entry 90A is completed, then the instruction information in reservation station entries 90B and 90C are moved into reservation station entries 90A and 90B, respectively,” Col 18, Lines 1-7.
The claimed “epilogue operation” is mapped to the disclosed deletion of the instruction, after it has completed, from the reservation station by shifting down the instruction information stored within subsequent reservation station entries.);
the determination circuitry is configured to perform an action in response to a behavior of the variable-issue operation (
Pflum discloses, “The apparatus described herein enhances the performance of the microprocessor without introducing undue complication in the functional units included therein. Where conventional methods would categorize all instructions as either single dispatch or microcode, the apparatus allows for more flexibility by including a multiple dispatch instruction category. The flexibility may be used to significant advantage by the apparatus. For example, instruction throughput may be enhanced by dispatching single dispatch instructions concurrently with multiple dispatch instructions. Because the multiple dispatch instruction occupy a predefined fixed number of functional units, single dispatch instructions may be concurrently dispatched upon detection of the multiple dispatch instructions,” Col 3, Lines 24-37, and
“Instruction scanning unit 52 identifies multiple dispatch instructions by partially decoding the instructions and routes them to instruction alignment unit 18 or MROM unit 34, depending upon the embodiment. The multiple dispatch instructions are tagged as being multiple dispatch such that they are routed to the appropriate number of issue positions,” Col 14, Lines 33-39.
In response to the disclosed “instruction scanning unit” determining that the instructions of the variable-issue operation are multiple dispatch instructions, it allows other instructions to be performed concurrently in order to enhance instruction throughput.)
Pflum in view of Hill and Brown does not teach that the determination circuitry is configured to perform a further determination of whether the epilogue operation is the single-issue operation or the multiple-issue operation in response to a behaviour of the variable-issue operation.
However, ARM teaches a further determination of whether the epilogue operation is the single-issue operation or the multiple-issue operation (
ARM discloses, “Single-instruction epilogues don't have to be encoded at all, either as scopes or as unwind codes. If an unwind takes place before that instruction is executed, then it's safe to assume it's from within the body of the function. Just executing the prologue unwind codes is sufficient. When the unwind takes place after the single instruction is executed, then by definition it takes place in another region,” Page 18,
“Multi-instruction epilogues don't have to encode the first instruction of the epilogue, for the same reason as the previous point: if the unwind takes place before that instruction executes, a full prologue unwind is sufficient. If the unwind takes place after that instruction, then only the later operations have to be considered,” Page 18.
Here, it can be determined whether the epilogue operation is the single-issue operation (single-instruction epilogue) or the multiple-issue operation (multi-instruction epilogue).
After the combination of Pflum in view of Hill and Brown, with ARM, it is determined whether the epilogue operation is the single-issue operation or the multiple-issue operation in response to the behavior of the variable-issue operation, as specified by Pflum in view of Hill and Brown.).
Pflum in view of Hill and Brown, and ARM are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to have modified Pflum in view of Hill and Brown to incorporate the teachings of ARM and provide that the determination circuitry is configured to perform a further determination of whether the epilogue operation is the single-issue operation or the multiple-issue operation in response to a behaviour of the variable-issue operation. Doing so would help allow for using different epilogues in each fragment of the function if it is split, in order to increase flexibility of the overall operation (ARM discloses, “Depending on the number of epilogues, each fragment may contain zero or more epilogues,” Page 15.).
Regarding Claim 14, Pflum in view of Hill, Brown, and ARM teaches the apparatus of claim 13, wherein the determination circuitry is configured to perform the further determination and determine that the epilogue operation is the multiple-issue operation in response to the determination being that the variable-issue operation is the multiple-issue operation (
Pflum teaches wherein the determination circuitry is configured to perform an action in response to the determination being that the variable-issue operation is the multiple-issue operation, disclosing, “The apparatus described herein enhances the performance of the microprocessor without introducing undue complication in the functional units included therein. Where conventional methods would categorize all instructions as either single dispatch or microcode, the apparatus allows for more flexibility by including a multiple dispatch instruction category. The flexibility may be used to significant advantage by the apparatus. For example, instruction throughput may be enhanced by dispatching single dispatch instructions concurrently with multiple dispatch instructions. Because the multiple dispatch instruction occupy a predefined fixed number of functional units, single dispatch instructions may be concurrently dispatched upon detection of the multiple dispatch instructions,” Col 3, Lines 24-37, and
“Instruction scanning unit 52 identifies multiple dispatch instructions by partially decoding the instructions and routes them to instruction alignment unit 18 or MROM unit 34, depending upon the embodiment. The multiple dispatch instructions are tagged as being multiple dispatch such that they are routed to the appropriate number of issue positions,” Col 14, Lines 33-39.
In response to the disclosed “instruction scanning unit” determining that the instructions of the variable-issue operation are multiple dispatch instructions, it allows other instructions to be performed concurrently in order to enhance instruction throughput.
ARM teaches to perform the further determination and determine that the epilogue operation is the multiple-issue operation, disclosing, “Single-instruction epilogues don't have to be encoded at all, either as scopes or as unwind codes. If an unwind takes place before that instruction is executed, then it's safe to assume it's from within the body of the function. Just executing the prologue unwind codes is sufficient. When the unwind takes place after the single instruction is executed, then by definition it takes place in another region,” Page 18,
“Multi-instruction epilogues don't have to encode the first instruction of the epilogue, for the same reason as the previous point: if the unwind takes place before that instruction executes, a full prologue unwind is sufficient. If the unwind takes place after that instruction, then only the later operations have to be considered,” Page 18.
Here, it can be determined whether the epilogue operation is the single-issue operation (single-instruction epilogue) or the multiple-issue operation (multi-instruction epilogue).
After the combination of Pflum in view of Hill and Brown, with ARM, it is determined whether the epilogue operation is the single-issue operation or the multiple-issue operation in response to the to whether the variable-issue operation is a multiple-issue operation, as specified by Pflum in view of Hill and Brown.).
Pflum in view of Hill and Brown, and ARM are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to have modified Pflum in view of Hill and Brown to incorporate the teachings of ARM and provide wherein the determination circuitry is configured to perform the further determination and determine that the epilogue operation is the multiple-issue operation in response to the determination being that the variable-issue operation is the multiple-issue operation. Doing so would help allow for using different epilogues in each fragment of the function, in order to increase flexibility of the overall operation (ARM discloses, “Depending on the number of epilogues, each fragment may contain zero or more epilogues,” Page 15.).
Regarding Claim 15, Pflum in view of Hill, Brown, and ARM teaches the apparatus of claim 13, wherein the determination circuitry is configured to perform the further determination and determine that the epilogue operation is the multiple-issue operation in response to the variable-issue operation being performed to an extent such that there is nothing left for the epilogue operation to do (
PNG
media_image1.png
490
721
media_image1.png
Greyscale
ARM discloses, “Unwind codes 0xFD and 0xFE are equivalent to the regular end code 0xFF, but account for one extra nop opcode in the epilogue case, either 16-bit or 32-bit. For prologues, codes 0xFD, 0xFE and 0xFF are exactly equivalent. This accounts for the common epilogue endings bx lr or b <tailcall-target>, which don't have an equivalent prologue instruction. This increases the chance that unwind sequences can be shared between the prologue and the epilogues,” Page 12.
Here, the unwind codes 0xFD and 0xFE mean that an epilogue consists of an NOP, meaning that the main operation has been performed to an extent that the epilogue has nothing left to do.
After the combination of Pflum in view of Hill and Brown, with ARM, it is determined whether the epilogue operation is the single-issue operation or the multiple-issue operation in response to whether the variable-issue operation has been performed to an extent that there is nothing left to do, as defined by Pflum in view of Hill and Brown.).
Pflum in view of Hill and Brown, and ARM are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to have modified Pflum in view of Hill and Brown to incorporate the teachings of ARM and provide wherein the determination circuitry is configured to perform the further determination and determine that the epilogue operation is the multiple-issue operation in response to the variable-issue operation being performed to an extent such that there is nothing left for the epilogue operation to do. Doing so would help allow for scheduling the epilogue operation as a null operation in order to enable scheduling other epilogue operations in the same cycle, which increases parallelism and efficiency.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Pflum (US 5822560 A) in view of Hill (US 20070050600 A1), Brown (US 6240508 B1), ARM (“ARM Exception Handling”), Mukherjee (US 20200133680 A1), and Petrick (US 6148391 A).
Regarding Claim 16, Pflum in view of Hill, Brown, and ARM teaches the apparatus of claim 14, wherein the prologue operation, the variable-issue operation and the epilogue operation are generated (
Pflum discloses, “Instructions fetched from instruction cache 16 are conveyed to instruction alignment unit 18. As instructions are fetched from instruction cache 16, the corresponding predecode data is scanned to provide information to instruction alignment unit 18 (and to MROM unit 34) regarding the instructions being fetched. Instruction alignment unit 18 utilizes the scanning data to align an instruction to each of decode units 20,” Col 8, Lines 53-60, and
“A completed instruction is deleted from reservation station 22A by shifting down the instruction information stored within subsequent reservation station entries 90. For example, if the instruction stored within reservation station entry 90A is completed, then the instruction information in reservation station entries 90B and 90C are moved into reservation station entries 90A and 90B, respectively,” Col 18, Lines 1-7.
The claimed “prologue operation” is the disclosed alignment operation performed on the instruction, before the instruction is executed. This is in line with Page 12 of the present application’s specification, which states that “In some examples, the prologue operation is configured to perform an alignment process such that the variable-issue operation, when performed, is aligned with a memory boundary…”
The claimed “epilogue operation” is the disclosed deletion of the instruction, after it has completed, from the reservation station by shifting down the instruction information stored within subsequent reservation station entries.);
the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to being decoded (
Pflum discloses, “Instruction scanning unit 52 identifies multiple dispatch instructions by partially decoding the instructions and routes them to instruction alignment unit 18 or MROM unit 34, depending upon the embodiment. The multiple dispatch instructions are tagged as being multiple dispatch such that they are routed to the appropriate number of issue positions,” Col 14, Lines 33-39.);
and the determination circuitry is configured to perform the further determination and determine that the epilogue operation is the multiple-issue operation (
ARM discloses, “Multi-instruction epilogues don't have to encode the first instruction of the epilogue, for the same reason as the previous point: if the unwind takes place before that instruction executes, a full prologue unwind is sufficient. If the unwind takes place after that instruction, then only the later operations have to be considered,” Page 18.).
Pflum in view of Hill and Brown, and ARM are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to have modified Pflum in view of Hill and Brown to incorporate the teachings of ARM and provide that the determination circuitry is configured to perform the further determination and determine that the epilogue operation is the multiple-issue operation. Doing so would help allow for scheduling the epilogue operation as a null operation in order to enable scheduling other epilogue operations in the same cycle, which increases parallelism and efficiency.
Pflum in view of Hill, Brown, and ARM does not teach wherein the prologue operation, the variable-issue operation and the epilogue operation are generated in response to decoding of at least one memory block instruction indicating a total number of bytes of the memory,
the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to the total number of bytes being less than or equal to 1,
and the determination circuitry is configured to perform the further determination and determine that the epilogue operation is the multiple-issue operation in response to the total number of bytes being less than or equal to an alignment boundary interval plus 1.
However, Mukherjee teaches decoding of at least one memory block instruction indicating a total number of bytes of the memory (
Mukherjee discloses, “At each level, the cache system will load blocks of data or instructions into entries and evict blocks of data or instructions from entries in units of memory blocks (also called “cache lines” or “cache blocks”). Each memory block includes a number of words of data or instructions, each word consisting of a predetermined number of bytes. A memory page typically has data or instructions from many memory blocks,” ¶ 0002.
After the combination of Pflum in view of Hill, Brown, and ARM, with Mukherjee, the prologue operation, the variable-issue operation, and the epilogue operation from Pflum in view of Hill, Brown, and ARM, are generated in response to decoding of at least one memory block instruction indicating a total number of bytes of the memory, as specified by Muhkerjee.).
Pflum in view of Hill, Brown, and ARM, and Mukherjee are both considered to be analogous to the claimed invention because they are in the same field of computer processor instructions. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to have modified Pflum in view of Hill, Brown, and ARM to incorporate the teachings of Mukherjee and provide wherein the prologue operation, the variable-issue operation and the epilogue operation are generated in response to decoding of at least one memory block instruction indicating a total number of bytes of the memory. Doing so would help provide an efficient means of storing the instructions. (Mukherjee discloses, “At each level, the cache system will load blocks of data or instructions into entries and evict blocks of data or instructions from entries in units of memory blocks (also called “cache lines” or “cache blocks”). Each memory block includes a number of words of data or instructions, each word consisting of a predetermined number of bytes. A memory page typically has data or instructions from many memory blocks,” ¶ 0002.).
Pflum in view of Hill, Brown, ARM, and Mukherjee does not teach that the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to the total number of bytes being less than or equal to 1,
and the determination circuitry is configured to perform the further determination and determine that the epilogue operation is the multiple-issue operation in response to the total number of bytes being less than or equal to an alignment boundary interval plus 1.
However, Petrick teaches an operation with the total number of bytes being less than or equal to 1 (
Petrick discloses, “In an exemplary hardware processor 100 embodiment, a single-byte first instruction can be folded with a second instruction,” Col 13, Lines 32-34.
Here, a “single-byte first instruction” has a total number of bytes equal to 1.
After the combination of Pflum in view of Hill, Brown, ARM, and Mukherjee, with Petrick, it is determined that the variable-issue operation is the multiple-issue operation, as specified by Pflum in view of Hill, Brown, ARM, and Mukherjee, based on the condition that the total number of bytes of the operation is less than or equal to 1, as specified by Petrick.);
and the determination circuitry is configured to perform the further determination and determine that the epilogue operation is the multiple-issue operation in response to the total number of bytes being less than or equal to an alignment boundary interval plus 1 (
Petrick discloses, “The front end of hardware processor 100 is largely separate from the rest of hardware processor 100. Ideally, one instruction per cycle is delivered to the execution pipeline. The instructions are aligned on an arbitrary eight-bit boundary by byte aligner circuit 122 in response to a signal from instruction decode unit 130,” Col 11, Lines 23-28.
Here, each instruction is aligned on an 8-bit boundary, with the total number of bytes for each instruction being 1 byte (8 bits). This means that the subsequent instruction after the current instruction will be located at most on the alignment boundary interval plus 1.
After the combination of Pflum in view of Hill, Brown, ARM, and Mukherjee, with Petrick, it is determined that the epilogue operation is the multiple-issue operation, as specified by Pflum in view of Hill, Brown, ARM, and Mukherjee, based on the condition that the total number of bytes of the epilogue operation being less than or equal to an alignment boundary interval plus 1, as specified by Petrick.).
Pflum in view of Hill, Brown, ARM, and Mukherjee, and Petrick are both considered to be analogous to the claimed invention because they are in the same field of computer architecture. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to have modified Pflum in view of Hill, Brown, ARM, and Mukherjee to incorporate the teachings of “Petrick and provide that the determination circuitry is configured to perform the determination and determine that the variable-issue operation is the multiple-issue operation in response to the total number of bytes being less than or equal to 1, and the determination circuitry is configured to perform the further determination and determine that the epilogue operation is the multiple-issue operation in response to the total number of bytes being less than or equal to an alignment boundary interval plus 1. Doing so would help allow for both aligning the operations, and allow easier access of a variable-issue operation from its epilogue, or vice-versa, by simply shifting bytes. Doing so would also help allow for fetching from any byte position (Petrick discloses, “The instructions are aligned on an arbitrary eight-bit boundary by byte aligner circuit 122 in response to a signal from instruction decode unit 130. Thus, the front end of hardware processor 100 efficiently deals with fetching from any byte position,” Col 11, Lines 26-30.).
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Pflum (US 5822560 A) in view of Hill (US 20070050600 A1) and Zaidy (US 20210303358 A1).
Regarding Claim 17, Pflum in view of Hill teaches a system comprising: the apparatus of claim 1. Pflum in view of Hill does not teach that the apparatus is implemented in at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board.
However, Zaidy teaches that an apparatus is implemented in at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board (
Zaidy discloses, “FIG. 1 is a block diagram of a representative embodiment of an inference engine circuit architecture (or system) 50 comprising a matrix-matrix (MM) processor circuit 200 and one or more matrix-matrix (MM) accelerator circuits 100. The inference engine circuit architecture 50, as a system, further comprises a memory interface 60 for read (load) and write (store) access to a memory circuit 25, which access may be through a memory controller 40 optionally. As another option, the inference engine circuit architecture 50 may also comprise a general purpose processor 75…,” ¶ 0037.
The claimed “packaged chip” is mapped to the disclosed “general purpose processor 75”.
The claimed “system component” is mapped to the disclosed “memory interface 60”.
The claimed “board” is mapped to the disclosed “interface engine circuit architecture 50”.).
Pflum in view of Hill, and Zaidy are both considered to be analogous to the claimed invention because they are in the same field of computer task scheduling. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pflum in view of Hill to incorporate the teachings of Zaidy and provide that an apparatus is implemented in at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board. Doing so would help improve the efficiency of the overall system (Zaidy discloses, “Such a computing architecture should have a comparatively high efficiency, with significant utilization, and should have a comparatively low bandwidth for access to any memory integrated circuit storing the maps and kernel data,” ¶ 0004.).
Regarding Claim 18, Pflum in view of Hill and Zaidy teaches a chip-containing product comprising the system of claim 17 assembled on a further board with at least one other product component (
Zaidy discloses, “The inference engine circuit architecture 50 also typically includes a communication interface (or other input-output interface) 45, described in greater detail below, for communication between the inference engine circuit architecture 50 and other, typically off-chip components which may be part of a larger system or board 15 (e.g., a rack-mounted board of a server, for example and without limitation), such as the memory circuit 25 (via a communication bus 20, which may have any type of kind of communication bus structure, for example and without limitation),” ¶ 0037.
The claimed “further board” is mapped to the disclosed “larger system or board 15”.
The claimed “at least one other product component” is mapped to the disclosed “off-chip components”.).
Pflum in view of Hill, and Zaidy are both considered to be analogous to the claimed invention because they are in the same field of computer task scheduling. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pflum in view of Hill to incorporate the teachings of Zaidy and provide a chip-containing product comprising the system of claim 17 assembled on a further board with at least one other product component. Doing so would help provide better capability for integration with other components. (Zaidy discloses, “The inference engine circuit architecture 50 also typically includes a communication interface (or other input-output interface) 45, described in greater detail below, for communication between the inference engine circuit architecture 50 and other, typically off-chip components which may be part of a larger system or board 15 (e.g., a rack-mounted board of a server, for example and without limitation)…,” ¶ 0037.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Frank et al. (US 20040244000 A1): General Purpose Embedded Processor
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW SUN whose telephone number is (571)272-6735. The examiner can normally be reached Monday-Friday 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Aimee Li can be reached at (571) 272-4169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANDREW NMN SUN/Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195