DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 27, 2026 has been entered.
Response to Amendment
Claims 1-20 remain pending in the application. Examiner acknowledges arguments, but they were found not persuasive and rejections under 35 U.S.C. 103 have been maintained. Examiner further acknowledges amendments to claims 1 and 8, however the amended claims have been rejected upon further search and consideration.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kruckemyer et al (U.S. Patent Pub. No. 2002/0147889), hereinafter referred to as Kruckemyer, in view of Hendry et al (U.S. Patent Pub. No. 2012/0317362), hereinafter referred to as Hendry, Waugh et al (U.S. Patent Pub. No. 2020/0250094), hereinafter referred to as Waugh, and Arimilli et al (U.S. Patent No. 6,519,649), hereinafter referred to as Arimilli.
In regard to independent claim 1, Kruckemyer teaches A computer-implemented method comprising: performing a local snoop operation for a plurality of processors in response to receiving a fetch request. Kruckemyer discloses multiple "agents" (processors) which may cache data (Kruckemyer Paragraph 0009, lines 2-4). These agents can respond to a read transaction with a snoop of their cached data (e.g. a local snoop, Kruckemyer Paragraph 0009, lines 4-6). Kruckemyer also teaches upon determining that the local snoop operation is successful, generating a snoop tracing message comprising information associated with the local snoop operation. Kruckemyer discloses that agents can include indications in snoop responses to represent exclusive and modified states associated with read data (Kruckemyer Paragraph 0009, lines 8-12).
Kruckemyer does not disclose transmitting the snoop tracing message to a storage device, but Hendry describes populating a block tracking entry table in a block of a memory sharing device using responses to snoop requests to reduce repeated snoops (Hendry Paragraph 0036, lines 6-11). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Hendry in order to "efficiently maintain cache coherence between memory-sharing devices" (Hendry Paragraph 0005, lines 1-3).
The previously cited references do not teach generating and transmitting a consolidated snoop response and may not explicitly disclose operating within a cluster among multiple clusters, but Waugh Paragraphs 0044-0045 disclose a master node snoop response which represents a consolidated snoop response from devices in a cluster. This is disclosed in Paragraph 0043, lines 8-13 as being received by (e.g. transmitted to) cache coherency circuitry, achieving the claimed limitation. Waugh additionally teaches utilizing a controller for local snoops as well as for generating and transmitting consolidated snoops (cache coherency circuitry 614 in Fig. 7 is a form of control node which can issue requests and responses (Paragraph 0020, Paragraph 0085, lines 1-6), e.g. a form of controller; Fig. 7 shows coherency circuitry managing snoops from several CPUs and providing a single response e.g. consolidated snoop response; Paragraph 0085 lines 18-19 cache coherency circuitry issues snoop requests; Paragraph 0085 lines 19-26 generates and transmits consolidated snoop response which includes information on local snoop) and if combined with Hendry the controller would transmit snoop tracing messages to a storage device, achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Waugh with those of Kruckemyer and Hendry in order to consolidate snoop responses and "reduce the latency of [an] interconnect in order to improve the performance of a system that incorporates that interconnect" (Waugh Paragraph 0003, lines 5-7).
The previously cited references do not explicitly disclose generating a consolidated snoop response (and therefore some snoop tracing message) after receiving snoop responses from each processor in a cluster, however Arimilli Column 2, lines 6-12 disclose a system of multiple nodes containing one or more agents, wherein a consolidated snoop is generated by response logic (e.g. implemented in a controller in the cited combination) after receiving snoop responses from each local agent. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Arimilli in order to guarantee snoop data on all local agents and address issues related to latency for transactions between physically remote processors (Column 1, lines 54-58).
As for dependent claim 2, Kruckemyer, Hendry, and Waugh teach the computer-implemented method of claim 1. Hendry additionally discloses an embodiment wherein the information comprises at least one of (i) an indication of which processor of the plurality of processors had a cache line indicated in the fetch request, (ii) an address of the cache line, (iii) a state of the cache line according to a cache coherency protocol, or (iv) metadata associated with the local snoop operation. Hendry discloses block tracking entries transmitted in response to snoop operations which include cache line states (e.g. metadata associated with the snoop; Hendry Paragraph 0036, lines 6-11). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Hendry in order to "efficiently maintain cache coherence between memory-sharing devices" (Hendry Paragraph 0005, lines 1-3).
As for dependent claim 5, Kruckemyer, Hendry, and Waugh disclose the computer-implemented method of claim 1. Hendry additionally discloses an embodiment wherein the storage device comprises one or more partitions of memory dedicated for storing information from snoop tracing messages. Hendry describes populating a block tracking entry table in a block of a memory sharing device using responses to snoop requests (Hendry Paragraph 0036, lines 6-11). A specified area of memory for storing these block tracking entries would be functionally identical to a partition of memory containing snoop trace information.
As for dependent claim 6, Kruckemyer, Hendry, and Waugh teach the computer-implemented method of claim 1. Kruckemyer additionally discloses an embodiment wherein performing the local snoop operation comprises: sending, in response to a trigger message, a snoop request to each processor of the plurality of processors (Kruckemyer Paragraph 0007, lines 1-4 disclose each agent in a distributed system performing snoop operations in response to a transaction.); and receiving, from each processor of the plurality of processors in response to the snoop request sent to the processor, a snoop response indicating whether the processor has a cache line indicated in the fetch request. Kruckemyer Paragraph 0007, lines 15-20 disclose that each agent may report the state of data within the agent, including data states (e.g. cache line ownership; Kruckemyer Paragraph 0007, lines 4-6) which may be updated in response to a transaction and subsequent snoop.
As for dependent claim 7, Kruckemyer, Hendry, and Waugh teach the computer-implemented method of claim 6. Kruckemyer, Hendry, and Waugh in combination additionally teach an embodiment wherein determining that the local snoop operation is successful comprises determining that a processor of the plurality of processors has the cache line indicated in the fetch request. Kruckemyer Paragraph 0073, lines 5-8 disclose altering cache line states in response to a snoop hit resulting from a fetch request received by another processor. These cache states can be taken with the disclosure of Hendry wherein block tracking entries are transmitted in response to snoop operations which include cache line states (e.g. metadata associated with the snoop, Hendry Paragraph 0036, lines 6-11). This combination would then functionally achieve the claimed limitations by providing cache ownership data in snoop responses.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kruckemyer, Hendry, Waugh, and Arimilli, and further in view of Cherukuri (U.S. Patent No. 6,006,307).
Kruckemyer, Hendry, and Waugh teach the computer-implemented method of claim 1. They do not teach the remaining limitations of claim 3. However, Cherukuri in combination discloses an embodiment wherein the snoop tracing message is transmitted to the storage device via a fetch request channel or a store request channel. Cherukuri discloses a multiprocessor system wherein processors utilize dedicated fetch channels for "non-speculative memory operations in response to instructions being executed by [a] microprocessor" (Cherukuri Column 3, lines 44-46). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize dedicated fetch channels for entire fetch operations (including snoops) in order to keep bandwidth consumed by fetches independent from other operations (pre fetch operations in the case of Cherukuri, Column 3, line 52).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kruckemyer, Hendry, Waugh, and Arimilli, and further in view of Qureshi (U.S. Patent Pub. No. 2011/0191546).
Kruckemyer, Hendry, and Waugh teach the computer-implemented method of claim 1. Neither discloses an embodiment wherein the snoop tracing message is transmitted to the storage device via a bus dedicated for sending snoop tracing messages. However, Qureshi Paragraph 0015, lines 6-9 describe a snoop bus 18 connecting caches 14 in Fig. 1, which is also shown connecting via another bus 28 to a shared memory. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Qureshi in order to "reduce memory latency by accessing memory in parallel with snooping the other processors" (Qureshi Paragraph 0003, lines 15-17).
Claims 8-11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Qureshi in view of Tarui et al (U.S. Patent No. 5,606,686), hereinafter referred to as Tarui.
In regard to independent claim 8, Qureshi teaches a computer-implemented method comprising: receiving a fetch request from a first processor of a plurality of processors in a first cluster of a plurality of clusters within a computing system (Qureshi Paragraph 0015, lines 11-15 disclose clusters 24 containing processors 12 each with a snoop bus 18 in Fig. 1, wherein each processor has individual cache snooping capability and can issue fetch requests for cache lines (Qureshi Paragraph 0017)); determining a component of the computing system where the fetch request resolves (Qureshi Paragraph 0017 discloses a memory request process wherein a cache miss results in a determination of where the requested data can be found, including in system memory, wherein a fetch request is issued to retrieve the data, which would include determining the location of the data in memory).
Qureshi does not teach encoding, at the first cluster and in response to determining the component of the computing system that resolves the fetch request (though in the cited combination, a fetch response would only be encoded after the resolution step of Qureshi sends a fetch request), information within a fetch response, wherein the encoded information indicates at least the component of the computing system that resolves the fetch request; and transmitting the fetch response comprising the encoded information to the first processor. However, Tarui Column 10, line 55 to Column 11, line 10 discloses an embodiment of a reply to a fetch command which includes an accessed main memory address and a destination processing unit encoded into a packet transmitted to a network of processors. By combining several of the grouped PUs of Tarui as in the clusters of Qureshi (i.e. PU of Tarui as processor system of Qureshi Fig. 2), fetch responses would be transmitted within clusters, between processors, achieving the claimed limitation. Additionally, Tarui Column 7, lines 35-39 disclose that the address specified in a command is used to determine the destination PU for that command, meaning the included accessed address in the fetch response would indicate the component of the computing system that resolves the request. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Tarui with that of Qureshi in order to achieve the claimed limitation and reduce the amount of memory needed for storage of directory structure (Tarui Column 2, lines 56-59).
As for dependent claim 9, Qureshi and Tarui teach The computer-implemented method of claim 8, and Qureshi additionally discloses an embodiment further comprising: triggering a local snoop operation for the plurality of processors in the first cluster in response to receiving the fetch request (Qureshi Paragraph 0026 discloses a process wherein a fetch triggers a cache snoop (via a prediction based on an indicator bit; Qureshi Paragraph 0026, lines 1-3)); and upon determining that the local snoop operation is successful, generating the fetch response, wherein the fetch response further comprises a cache line indicated in the fetch request. The triggered snoop is carried out within the cluster to locate and fetch a data item (used interchangeably with cache line in Qureshi; Paragraph 0017, line 9) for the requesting processor.
As for dependent claim 10, Qureshi and Tarui teach the computer-implemented method of claim 9. Qureshi additionally discloses an embodiment wherein the component is a second processor of the plurality of processors in the first cluster. Qureshi Paragraph 0026 discloses a process wherein a fetch triggers a cache snoop (via a prediction based on an indicator bit; Qureshi Paragraph 0026, lines 1-3) carried out within the cluster to locate and fetch a data item (used interchangeably with cache line in Qureshi; Paragraph 0017, line 9) which may be present in another processor in the cluster (Qureshi Paragraph 0026, lines 4-6).
As for dependent claim 11, Applicant is directed to the rejections of claims 9 and 10 set forth above, as they address the instant limitation and therefore claim 11 is rejected based on the same rationale.
As for dependent claim 17, Qureshi and Tarui teach the computer-implemented method of claim 8, and Qureshi additionally discloses an embodiment wherein one or more counters associated with the first processor are incremented based on the encoded information in the fetch response. Qureshi Paragraph 0022, lines 1-8 disclose decrementing or incrementing a counter associated with a processor based on where a fetch resolves.
Claims 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Qureshi and Tarui, and further in view of Park et al (U.S. Patent Pub. No. 2016/0203083), hereinafter referred to as Park.
In regard to independent claim 12, Qureshi and Tarui teach The computer-implemented method of claim 8, and Qureshi additionally discloses an embodiment further comprising: triggering a local snoop operation for the plurality of processors in the first cluster in response to receiving the fetch request (Qureshi Paragraph 0026 discloses a process wherein a fetch triggers a cache snoop (via a prediction based on an indicator bit; Qureshi Paragraph 0026, lines 1-3) carried out within the cluster to locate and fetch a data item (used interchangeably with cache line in Qureshi; Paragraph 0017, line 9)). Qureshi and Tarui do not teach the remaining limitations of claim 12. However, Qureshi in combination with Park teaches an embodiment wherein upon determining that the local snoop operation is unsuccessful: forwarding the fetch request to a first upper level cache associated with the first cluster; and receiving the fetch response from the first upper level cache, wherein the fetch response further comprises a cache line indicated in the fetch request. Qureshi Paragraph 0026, lines 6-9 disclose forwarding a fetch request outside of the processors of a cluster to another memory. Park Paragraph 0027, lines 1-4 disclose a cache in each cluster that is shared by the included processors (112, 118, and 124 in Fig. 1). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine the disclosure of Park in order to "reduce the average time to access data from a main memory" (Park Paragraph 0027, lines 3-4) and allow snooping and fetching in upper level shared caches.
As for dependent claim 13, Qureshi, Tarui, and Park teach the computer-implemented method of claim 12, and Park additionally discloses an embodiment wherein the component is a second cluster of the plurality of clusters. Park Paragraph 0036 discloses an embodiment wherein a processor cluster can fetch data stored in a shared cache located in and associated with another processor cluster (lines 1-5).
As for dependent claim 14, Applicant is referred to the rejection of claim 13, as it addresses the instant limitation of claim 14.
As for dependent claim 15, Qureshi, Tarui, and Park teach the computer-implemented method of claim 12, and Qureshi additionally discloses an embodiment wherein the component is main memory of the computing system. Qureshi Paragraph 0026, lines 6-9 disclose forwarding a fetch request outside of the processors of a cluster to a physical memory external to the cluster, which is coupled to the clusters in the same manner described in the discussion of Figure 2 of the instant application.
As for dependent claim 16, Qureshi, Tarui, and Park teach the computer-implemented method of claim 12, and Qureshi additionally discloses an embodiment wherein determining that the local snoop operation is unsuccessful comprises determining that none of the plurality of processors in the first cluster has the cache line. Qureshi Paragraph 0026 discloses a process wherein a fetch triggers a cache snoop (via a prediction based on an indicator bit; Qureshi Paragraph 0026, lines 1-3) carried out within the cluster to locate and fetch a data item (used interchangeably with cache line in Qureshi; Paragraph 0017, line 9). Qureshi Paragraph 0026, lines 6-9 disclose forwarding a fetch request outside of the processors of a cluster to another memory in the case of a snoop miss. This determination is functionally identical to the claimed limitation.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Qureshi, Tarui, Hendry, Chiu et al (U.S. Patent Pub. No. 2009/0007134), hereinafter referred to as Chiu, and McKenney (U.S. Patent Pub. No. 2002/0166030).
In regard to independent claim 18, Qureshi teaches a computer-implemented method comprising: transmitting, from a processor in a first cluster of a plurality of clusters in a computing system, a fetch request for a cache line (Qureshi Paragraph 0015, lines 11-15 disclose clusters 24 containing processors 12 each with a snoop bus 18 in Fig. 1, wherein each processor has individual cache snooping capability and can issue fetch requests for cache lines (Qureshi Paragraph 0017)); receiving, in response to the fetch request, a fetch response comprising (i) the cache line and (ii) encoded snoop activity information. Qureshi Paragraph 0026 additionally discloses a process wherein a fetch triggers a cache snoop (via a prediction based on an indicator bit; Qureshi Paragraph 0026, lines 1-3) carried out to locate and fetch a data item (used interchangeably with cache line in Qureshi; Paragraph 0017, line 9).
Qureshi does not disclose the fetch response of the instant limitation, but Tarui Column 10, line 55 to Column 11, line 10 describes an embodiment of a reply to a fetch command which includes an accessed main memory address and a destination processing unit encoded into a packet transmitted to a network of processors. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Tarui with that of Qureshi in order to achieve the claimed limitation and reduce the amount of memory needed for storage of directory structure (Tarui Column 2, lines 56-59).
Tarui additionally teaches decoding the fetch response (Tarui Column 14, lines 47-54 disclose that responses to fetch commands are deconstructed by a packet receiver and deconstructor when sent to processors) but not to obtain decoded snoop activity information. However, Hendry describes populating a block tracking entry table using responses to snoop requests (Hendry Paragraph 0036, lines 6-11), which in combination would result in decoding snoop activity contained in fetch responses. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Hendry in order to "efficiently maintain cache coherence between memory-sharing devices" (Hendry Paragraph 0005, lines 1-3).
Qureshi additionally discloses incrementing a counter of a plurality of counters based on the decoded snoop activity information, wherein the plurality of counters tracks a number of times that a fetch resolved in a different location in memory of the computing system. Qureshi Paragraph 0022, lines 1-8 disclose decrementing or incrementing a counter associated with a processor based on where a fetch resolves. As shown in Qureshi Figure 2, each cache controller 16 has a saturation counter 30. Qureshi Figure 1 additionally shows a plurality of cache controllers attached to processors in clusters (e.g. a plurality of counters).
Qureshi does not teach a plurality of counters in the processor, but this is a known aspect of prior art processors, as shown in Chiu Paragraph 0009, which discloses several known processors with support for a plurality of counters. Therefore, the limitation of a plurality of counters in the processor is applying a known technique in the art to achieve the expected result of having several different counters for each processor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the known disclosure of Chiu in order to “allow counting processor events and system events on the chip” (Chiu Paragraph 0006, lines 2-3).
The previously cited references do not teach an embodiment wherein a first counter of the plurality of counters in the processor tracks a number of times that a fetch resolved within the first cluster and a second counter of the plurality of counters in the processor tracks a number of times that a fetch resolved within a second cluster of the plurality of clusters. However, McKenney discloses a distributed reference counter with multiple different count values stored by processors in a multi-cluster system (Paragraph 0035; Paragraph 0062 values are manipulated in the processors; Fig. 5 shows quad i.e. cluster accesses are counted) that tracks cache memory accesses by each CPU (Paragraph 0009, lines 9-12 known use of a distributed reference counter). Storing these reference counter values in the multiple counters of a processor as disclosed by Chiu achieves the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of McKenney in order to reduce the possibility of a cache overflow situation (Paragraph 0066).
As for dependent claim 19, the previously cited references teach the computer-implemented method of claim 18. Tarui additionally discloses an embodiment wherein the decoded snoop activity information indicates a location in memory where the fetch request resolved. Tarui Column 10, line 55 to Column 11, line 10 describes an embodiment of a reply to a fetch command which includes an accessed main memory address and a destination processing unit encoded into a packet transmitted to a network of processors.
As for dependent claim 20, the previously cited references teach the computer-implemented method of claim 19. Qureshi additionally teaches an embodiment wherein the location in memory indicated by the decoded snoop activity information is (i) another processor in the first cluster, (ii) a second cluster of the plurality of clusters, (iii) an upper level cache associated with the first cluster, (iv) an upper level cache associated with a second cluster of the plurality of clusters, or (v) main memory of the computing system. Qureshi Paragraph 0026 discloses a process wherein a fetch triggers a cache snoop (via a prediction based on an indicator bit; Qureshi Paragraph 0026, lines 1-3) carried out within the cluster to locate and fetch a data item (used interchangeably with cache line in Qureshi; Paragraph 0017, line 9). Qureshi Paragraph 0026, lines 6-9 disclose forwarding a fetch request outside of the processors of a cluster to another memory in the case of a snoop miss. This functionality combined with the references cited in the rejection of claim 19 (fetch responses disclosed by Tarui Column 10, line 55 to Column 11, line 10) would result in a system wherein decoded snoop activity can provide a location in memory from any of the listed memory components.
Response to Arguments
Applicant’s arguments with respect to the rejection of claim 1 and its dependents (see pages 7-11 of response filed 2 December, 2025) were considered but have not been found persuasive. Hendry’s BTE table is populated based on snoop responses, as indicated by Applicant. BTEs include coherency data and “snoop-required” indicators as indicated by Applicant. Since BTEs are generated using information from snoop responses and transferred to storage in some manner (i.e. moved as a form of message/request), they could reasonably be interpreted as “snoop tracing message[s] comprising information associated with the local snoop operation” by one of ordinary skill in the art. Applicant’s arguments regarding the reference Waugh have been considered, but in light of the amendments to the claim, newly added reference Arimilli is seen to address all deficiencies pointed out by Applicant, as Arimilli explicitly discloses generating a consolidated snoop response from each local agent at a form of control logic, and sending the response to other nodes.
Applicant’s arguments with respect to the rejection of claim 8 and its dependents (see pages 10-11 of response) were considered but have not been found persuasive. The addresses of Tarui indicate the component that resolves a memory request, as explained in the updated rejection of claim 8. Additionally, the data in command packets in Tarui is first deconstructed from and then constructed into another response packet, which would qualify as encoding even if this simply entails adding additional header data before the command data. As mentioned, the disclosure of Qureshi would result in this packet manipulation occurring in response to some determination of which component resolves the fetch, as a fetch request is only broadcast if it is determined that the data resides in a remote component and not a local one (see ¶ 0017). Additionally, Qureshi’s disclosure is fundamentally directed to predicting where fetch requests will resolve before broadcasting a request (see ¶ 0025, lines 1-6), which also means that the determination step would be performed entirely before the fetch request is sent, and therefore the encoded reply would functionally be in response to the determination.
Applicant’s arguments with respect to the rejection of claim 18 and its dependents (see pages 11-12 of response) were considered but have not been found persuasive. McKenney’s counters may track accesses of memory, as is known in prior art and explained by McKenney ¶ 0009, lines 9-12. Additionally, McKenney’s disclosure tracks a number of decrements and increments of the reference counters explicitly, which would be tracking a number of write accesses to the CPUs and Quads at minimum, given that the reference counters are meant to track allocations of data items (see ¶0038). Despite McKenney’s disclosure focusing on allocation, a person of ordinary skill in the art could easily apply McKenney’s counters to track fetch resolutions in combination with previously cited references, as fetches are a form of access or use of memory structures.
Conclusion
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/ZAKARIA MOHAMMED BELKHAYAT/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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