CTFR 18/457,066 CTFR 86353 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This action is in response to the amendments filed on February 3, 2026. Claims 30-31 are newly added; and claims 1-31 are pending and examined below. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1-10, 13-18 and 21-31 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hureau et al. (U.S. 2021/0089114) . With regard to claim 1, Hureau teaches an apparatus for vehicle operation (Figs. 1-2; [0002] Automotive applications may include, for example, gateways (e.g., in-vehicle networking and telematics)) , comprising: a system on a chip (SoC) (Fig. 2, processor 106; [0002] A semiconductor device or integrated circuit (IC) configured for such applications may be implemented with a significant amount of computing capacity. A processing system, such as including a microprocessor, microcontroller, system on chip or any other processing configuration) comprising a main domain (Fig. 2, low power domain 216) and a safety domain (Fig. 2, processor supply circuitry 208) ; at least one main domain (MD) power management integrated circuit (PMIC) (Fig. 2, master PMIC 202; [0028] two or more power management ICs (PMICs)) ; at least one MD power supply rail (Fig. 2, one or more supply voltages (VSUP)) coupled between the at least one MD PMIC and the main domain of the SoC for supplying power to the main domain of the SoC (Fig. 2, FROM 202 TO 216) ; at least one safety domain (SD) PMIC (Fig. 2, slave PMIC 204) ; at least one SD power supply rail (Fig. 2, VCOR) coupled between the at least one SD PMIC and the safety domain of the SoC for supplying power to the safety domain of the SoC (Fig. 2, the VCOR runs from 204 to 208) ; a MD PMIC power supply rail coupled to the at least one MD PMIC for supplying power to the at least one MD PMIC (Fig. 2, source voltage (VSRC); [0029] VSRC may originate from an external power source) ; and a SD PMIC power supply rail (Fig. 2, one or more supply voltages (VSUP)) coupled to the at least one SD PMIC for supplying power to the at least one SD PMIC, wherein the at least one MD PMIC has an input coupled to the SD PMIC power supply rail for monitoring the SD PMIC power supply rail (Fig. 2, one or more supply voltages (VSUP); [0031] The master PMIC 202 includes comparator circuitry 212 that monitors the voltage levels of VSUP_S and VCOR (via VMON)) . With regard to claim 2, the limitations are addressed above and Hureau teaches wherein the at least one MD PMIC has an output coupled to an input of the main domain of the SoC for indicating a state of the SD PMIC power supply rail (Fig. 2, one or more supply voltages (VSUP) from 202 coupled to 216) . With regard to claim 3, the limitations are addressed above and Hureau teaches wherein the at least one MD PMIC has an output for coupling to an input of a control unit external to the apparatus for indicating a state of the SD PMIC power supply rail ([0031] The master PMIC 202 has a slave enable output S_EN provided to an enable input EN of the slave PMIC 204) . With regard to claim 4, the limitations are addressed above and Hureau teaches wherein the input of the at least one MD PMIC is coupled to an analog-to-digital converter (ADC) channel or remote sense pins of the at least one MD PMIC (Fig. 2, comparator circuitry 212; [0036] The compare circuitry 212 may also monitor the voltage level of VCOR via the VMON input) . With regard to claim 5, the limitations are addressed above and Hureau teaches wherein the at least one SD PMIC has an input coupled to the MD PMIC power supply rail for monitoring the MD PMIC power supply rail (Fig. 2, slave PMIC 204 receives supply voltages (VSUP) from 202) . With regard to claim 6, the limitations are addressed above and Hureau teaches wherein the at least one SD PMIC has an output coupled to an input of the safety domain of the SoC for indicating a state of the MD PMIC power supply rail (Fig. 2, the VCOR runs from slave PMIC 204 to 208, and indicates power supply from MD PMIC 202) . With regard to claim 7, the limitations are addressed above and Hureau teaches wherein the input of the at least one SD PMIC is coupled to an analog-to-digital converter (ADC) channel or remote sense pins of the at least one SD PMIC (Fig. 2, check of input voltage via an ADC or additional sense pin) . With regard to claim 8, the limitations are addressed above and Hureau teaches wherein the at least one SD PMIC has an output for coupling to an input of a control unit or of a safety monitor, external to the apparatus for indicating a state of the MD PMIC power supply rail (Fig. 2, the VCOR output) . With regard to claim 9, the limitations are addressed above and Hureau teaches wherein the safety domain of the SoC is independent from the main domain of the SoC (Fig. 2, processor supply circuitry 208 which is separate from the low power domain 216) . With regard to claim 10, the limitations are addressed above and Hureau teaches wherein the safety domain of the SoC is configured to support a more stringent safety standard than the main domain of the SoC (Fig. 2, voltage VCOR is additionally supervised by comparator 212) . With regard to claim 13, Hureau teaches an apparatus for operating a vehicle (Figs. 1-2; [0002] Automotive applications may include, for example, gateways (e.g., in-vehicle networking and telematics)) , comprising: a system on a chip (SoC) (Fig. 2, processor 106; [0002] A semiconductor device or integrated circuit (IC) configured for such applications may be implemented with a significant amount of computing capacity. A processing system, such as including a microprocessor, microcontroller, system on chip or any other processing configuration) comprising a main domain (Fig. 2, low power domain 216) and a safety domain (Fig. 2, processor supply circuitry 208) ; at least one main domain (MD) power management integrated circuit (PMIC) (Fig. 2, master PMIC 202; [0028] two or more power management ICs (PMICs)) ; at least one MD power supply rail (Fig. 2, one or more supply voltages (VSUP)) coupled between the at least one MD PMIC and the main domain of the SoC for supplying power to the main domain of the SoC (Fig. 2, FROM 202 TO 216) ; at least one safety domain (SD) PMIC (Fig. 2, slave PMIC 204) ; at least one SD power supply rail (Fig. 2, VCOR) coupled between the at least one SD PMIC and the safety domain of the SoC for supplying power to the safety domain of the SoC (Fig. 2, the VCOR runs from 204 to 208) ; a MD PMIC power supply rail coupled to the at least one MD PMIC for supplying power to the at least one MD PMIC (Fig. 2, source voltage (VSRC); [0029] VSRC may originate from an external power source) ; and a SD PMIC power supply rail (Fig. 2, one or more supply voltages (VSUP)) coupled to the at least one SD PMIC for supplying power to the at least one SD PMIC, wherein the at least one SD PMIC has an input coupled to the MD PMIC power supply rail for monitoring the MD PMIC power supply rail (Fig. 2, one or more supply voltages (VSUP); [0031] The master PMIC 202 includes comparator circuitry 212 that monitors the voltage levels of VSUP_S and VCOR (via VMON)) . With regard to claim 14, the limitations are addressed above and Hureau teaches wherein the at least one SD PMIC has an output coupled to an input of the safety domain of the SoC for indicating a state of the MD PMIC power supply rail (Fig. 2, one or more supply voltages (VSUP) from 202 coupled to 216) . With regard to claim 15, the limitations are addressed above and Hureau teaches wherein the input of the at least one SD PMIC is coupled to an analog-to-digital converter (ADC) channel or remote sense pins of the at least one SD PMIC (Fig. 2, comparator circuitry 212; [0036] The compare circuitry 212 may also monitor the voltage level of VCOR via the VMON input) . With regard to claim 16, the limitations are addressed above and Hureau teaches wherein the at least one SD PMIC has an output for coupling to an input of a control unit or of a safety monitor, external to the apparatus for indicating a state of the MD PMIC power supply rail (Fig. 2, the VCOR runs from slave PMIC 204 to 208, and indicates power supply from MD PMIC 202) . With regard to claim 17, the apparatus claim corresponds to the apparatus claim 9, respectively, and therefore is rejected with the same rationale. With regard to claim 18, the apparatus claim corresponds to the apparatus claim 10, respectively, and therefore is rejected with the same rationale. With regard to claim 21, Hureau teaches a method of power supply monitoring ([0001] ensuring that power mode transitions take place in a robust, safe and secure manner to reduce potential of failure for a cascaded power supply) , comprising: regulating power to a main domain (Fig. 2, low power domain 216 and power regulation via the power regulator circuitry 206) of a system on a chip (SoC) ([0002] A processing system, such as including a microprocessor, microcontroller, system on chip or any other processing configuration, may be used to process any type of data or information to control certain parameters, functions or operations associated with a particular application) using at least one main domain (MD) power management integrated circuit (PMIC) (Fig. 2, a master PMIC 202 and core supply circuitry 210) ; regulating power to a safety domain of the SoC (Fig. 2, an input of processor supply circuitry 208) using at least one safety domain (SD) PMIC (Fig. 2, slave PMIC 204) ; powering the at least one SD PMIC using a SD PMIC power supply rail (Fig. 2, one or more supply voltages (VSUP) to the slave PMIC 204) ; and monitoring the SD PMIC power supply rail using the at least one MD PMIC (Fig. 2, comparator circuitry 212 monitoring VSUP_S which is part of VSUP input to slave PMIC 204) . With regard to claim 22, the limitations are addressed above and Hureau teaches further comprising sending an indication of a state of the SD PMIC power supply rail from the at least one MD PMIC to the main domain of the SoC (Fig. 2, processor supply circuitry 208 which is separate from the low power domain 216) . With regard to claim 23, the limitations are addressed above and Hureau teaches further comprising sending an indication of a state of the SD PMIC power supply rail from the at least one MD PMIC to a control unit external to a module that includes the SoC ([0031] The master PMIC 202 has a slave enable output S_EN provided to an enable input EN of the slave PMIC 204) . With regard to claim 24, the limitations are addressed above and Hureau teaches further comprising: powering the at least one MD PMIC using a MD PMIC power supply rail (Fig. 2, one or more supply voltages (VSUP) to the slave PMIC 204) ; and monitoring the MD PMIC power supply rail using the at least one SD PMIC (Fig. 2, comparator circuitry 212 monitoring VSUP_S which is part of VSUP input to slave PMIC 204) . With regard to claim 25, the limitations are addressed above and Hureau teaches further comprising sending an indication of a state of the MD PMIC power supply rail from the at least one SD PMIC to the safety domain of the SoC ([0031] The master PMIC 202 has a slave enable output S_EN provided to an enable input EN of the slave PMIC 204) . With regard to claim 26, the limitations are addressed above and Hureau teaches further comprising sending an indication of a state of the MD PMIC power supply rail from the at least one SD PMIC to a control unit or to a safety monitor, external to a module that includes the SoC ([0031] The master PMIC 202 has a slave enable output S_EN provided to an enable input EN of the slave PMIC 204) . With regard to claim 27, Hureau teaches a method of power supply monitoring ([0001] ensuring that power mode transitions take place in a robust, safe and secure manner to reduce potential of failure for a cascaded power supply) , comprising: regulating power to a main domain (Fig. 2, low power domain 216 and power regulation via the power regulator circuitry 206) of a system on a chip (SoC) ([0002] A processing system, such as including a microprocessor, microcontroller, system on chip or any other processing configuration, may be used to process any type of data or information to control certain parameters, functions or operations associated with a particular application) using at least one main domain (MD) power management integrated circuit (PMIC) (Fig. 2, a master PMIC 202 and core supply circuitry 210) ; regulating power to a safety domain of the SoC (Fig. 2, an input of processor supply circuitry 208) using at least one safety domain (SD) PMIC (Fig. 2, slave PMIC 204) ; powering the at least one MD PMIC using a MD PMIC power supply rail (Fig. 2, one or more supply voltages (VSUP) to the slave PMIC 204) ; and monitoring the MD PMIC power supply rail using the at least one SD PMIC (Fig. 2, comparator circuitry 212 monitoring VSUP_S which is part of VSUP input to slave PMIC 204) . With regard to claim 28, the limitations are addressed above and Hureau teaches further comprising sending an indication of a state of the MD PMIC power supply rail from the at least one SD PMIC to the safety domain of the SoC (Fig. 2, processor supply circuitry 208 which is separate from the low power domain 216) . With regard to claim 29, the limitations are addressed above and Hureau teaches further comprising sending an indication of a state of the MD PMIC power supply rail from the at least one SD PMIC to a control unit or to a safety monitor, external to a module that includes the SoC ([0031] The master PMIC 202 has a slave enable output S_EN provided to an enable input EN of the slave PMIC 204) . With regard to claim 30, the limitations are addressed above and Hureau teaches wherein the SD PMIC power supply rail is separate and independent from the MD PMIC power supply rail (Fig. 2, Master PMIC 202 and Slave PMIC 204; [0030] the cascaded PMIC system 104 includes a master PMIC 202 and a slave PMIC 204) . With regard to claim 31, the apparatus claim corresponds to the apparatus claim 30, respectively, and therefore is rejected with the same rationale . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claims 11-1 2 and 19-20 are reje cted under 35 U.S.C. 103 as being unpatentable over Hure au et al. (U.S. 2021/0089114) in view of Alexander et al. (U.S. 2023/0192100) . With regard to claim 11, the limitations are addressed above and Hureau teaches a safe method to transition between a normal mode of operation and one or more low power modes of operation between two or more power management ICs (PMICs) [0028]. However, Hureau does not specifically teach: - wherein the safety domain of the SoC is configured to comply with up to Automotive Safety Integrity Level (ASIL) D requirements and wherein the main domain of the SoC is configured to comply with up to ASIL B requirements Alexander teaches a driver assistance systems for implementing an awareness checker for enhancing collaborative driving supervision [0001]. Alexander also teaches the safety domain of the SoC ([0084] The module 800 may be configured as a chipset, a system on chip (SoC) and/or a discrete device) is configured to comply with up to Automotive Safety Integrity Level (ASIL) D requirements ([0018] Automotive Safety Integrity Level (ASIL) is a risk classification scheme defined by the ISO 26262—Functional Safety for Road Vehicles standard…The ASILs range from. ASIL D, representing the highest degree of risk of a hazardous scenario turning into a mishap and highest degree of rigor needed to be applied in the assurance of the resultant safety requirements, to QM, representing applications with no automotive hazardous scenarios with unacceptable risk and, therefore, no safety requirements to manage under the ISO 26262 safety processes) and wherein the main domain of the SoC is configured to comply with up to ASIL B requirements ([0018] Automotive Safety Integrity Level (ASIL) is a risk classification scheme defined by the ISO 26262—Functional Safety for Road Vehicles standard. This is an adaptation of the Safety Integrity Level (SIL) used in IEC 61508 for the automotive industry…The intervening levels (ASIL C, ASIL B, and ASIL A) are simply a range of varying degrees of hazard risk levels and degrees of assurance and engineering rigor required) . Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to have modified the system and method taught by Hureau, with the driver assistance system having Automotive Safety Integrity Level (ASIL) taught by Alexander, to have achieved a robust and safe method to transition between a normal mode of operation and one or more low power modes of operation between two or more power management ICs (PMICs). With regard to claim 12, the limitations are addressed above and Hureau teaches at least one SD PMIC (Fig. 2, slave PMIC 204) . However, Hureau does not specifically teach: - configured to comply with up to the ASIL D requirements and wherein the at least one MD PMIC is configured to comply with up to the ASIL B requirements Alexander teaches a driver assistance systems for implementing an awareness checker for enhancing collaborative driving supervision [0001]. Alexander also teaches the configured to comply with up to the ASIL D requirements ([0018] Automotive Safety Integrity Level (ASIL) is a risk classification scheme defined by the ISO 26262—Functional Safety for Road Vehicles standard…The ASILs range from. ASIL D, representing the highest degree of risk of a hazardous scenario turning into a mishap and highest degree of rigor needed to be applied in the assurance of the resultant safety requirements, to QM, representing applications with no automotive hazardous scenarios with unacceptable risk and, therefore, no safety requirements to manage under the ISO 26262 safety processes) and wherein the at least one MD PMIC is configured to comply with up to the ASIL B requirements ([0018] Automotive Safety Integrity Level (ASIL) is a risk classification scheme defined by the ISO 26262—Functional Safety for Road Vehicles standard. This is an adaptation of the Safety Integrity Level (SIL) used in IEC 61508 for the automotive industry…The intervening levels (ASIL C, ASIL B, and ASIL A) are simply a range of varying degrees of hazard risk levels and degrees of assurance and engineering rigor required) . Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to have modified the system and method taught by Hureau, with the driver assistance system having Automotive Safety Integrity Level (ASIL) taught by Alexander, to have achieved a robust and safe method to transition between a normal mode of operation and one or more low power modes of operation between two or more power management ICs (PMICs). With regard to claim 19, the apparatus claim corresponds to the apparatus claim 11, respectively, and therefore is rejected with the same rationale. With regard to claim 20, the apparatus claim corresponds to the apparatus claim 12, respectively, and therefore is rejected with the same rationale . Response to Arguments 07-37 AIA Applicant's arguments filed 2-3-2026 have been fully considered but they are not persuasive. In the remarks, Applicant argues that the Hureau reference fails to an SD power supply rail being coupled between an SD PMIC and regulating power to a safety domain of an SoC . Examiner respectfully disagrees with Applicant: The Hureau reference discloses a power system including a master power management circuit including a master power management circuitry and a slave power management circuitry [abstract]. Hureau teaches that the master circuitry includes a master power regulator, a comparator circuitry and a control circuitry [abstract]. In addition to the master power regulator, there is also a slave power management circuitry which provides core voltage when the slave signal is asserted for normal mode [0005]. The system includes a master power management integrated circuit (PMIC) and a slave power management integrated circuit (PMIC), which are ‘separate’ and ‘independent’ from each other and also carry out different jobs. For instance, the master power management integrated circuit (PMIC) controls power mode transitions for the peripheral system and the memory & storage system [0030]. The slave power management integrated circuit (PMIC) includes core supply circuitry that converts VSUP to a core voltage VCOR provided to a CORE voltage input of the processor supply, and may further separately receive and convert VSRC to VCOR [0030]. As such, the master power management integrated circuit (PMIC) and the slave power management integrated circuit (PMIC) are two distinct members having various different functions. Additionally, the claim requires for “at least one safety domain (SD) PMIC”. As mentioned, Hureau teaches the slave power management integrated circuit (PMIC) [abstract]. Figure 2 displays a safety domain of the SoC for supplying power to the safety domain of the SoC by showing the core voltage VCOR which runs from the slave PMIC (204) to an input of processor supply circuitry of the processor (208). Figure 2 shows where the processor supply circuitry (208) is separate from the low power domain (216). Examiner suggests adding more language to the independent claims to point out the different between the safety domain. Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREA C. LEGGETT whose telephone number is (571)270-7700. The examiner can normally be reached M-F 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kieu Vu can be reached at 571-272-4057. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANDREA C LEGGETT/Primary Examiner, Art Unit 2171 Application/Control Number: 18/457,066 Page 2 Art Unit: 2171 Application/Control Number: 18/457,066 Page 3 Art Unit: 2171
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