DETAILED ACTION
This Office Action is in response to Applicant’s amendments and arguments submitted on June 11, 2026 for Application # 18/457,171 filed on August 28, 2023 in which claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The Provisional Application# 63/415,476 filed on October 12, 2022.
Status of claims
Claims 1-20 are pending, of which claims 1-20 are rejected under 35 U.S.C. 103.
Claims 1 and 11 are amended.
No claims are canceled.
No claims are newly added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Heaton et al. US 11,875,247 B1 (hereinafter ‘Heaton’) in view of Theodorou et al. US 2024/0105292 A1 (hereinafter ‘Theodorou’) as applied, and further in view of Yanada et al. US 2019/0149734 A1 (hereinafter ‘Yanada’).
As per claim 1, Heaton disclose, A training system comprising (Heaton: Col 8 Lines 52-53: disclose training a neural network model in which the weight values):
a dynamic random access memory (DRAM) configured to buffer training data (Heaton: Col 11 Lines 36-38: disclose DRAM, and may provide additional storage capacity for the neural network acceleration engine and Col 16 Lines 65-66 and Fig. 7: disclose input data and/or program code for the accelerators 702a-702n can be stored in the DRAM);
a central processing unit (CPU) coupled to the DRAM and configured to downsample the training data and provide the DRAM with the downsampled training data (Heaton: Fig. 7 and Col 18 Lines 14-20: disclose chip interconnect 720. The chip interconnect 720 primarily includes wiring for routing data between the components of the acceleration engine 700. In some cases, the chip interconnect 720 can include a minimal amount of logic, such as multiplexors to control the direction of data, flip-flops for handling clock domain crossings, and timing logic. Examiner equates chip interconnect to CPU as chip interconnect has built in amount of logic); and
a graphic processing unit (GPU) (Heaton: Col 3 Lines 32-35: disclose the acceleration engine 112 can be a graphics processing unit (GPU), and may be optimized to perform the computations needed for graphics rendering) configured to perform training on the training data batches (Heaton: Col 11 Lines 12-14: disclose neural network computations such as matrix multiplication, and the batches of input data can be tensors or feature maps).
It is noted, however, Heaton did not specifically detail the aspects of
a computational storage consisting of a solid-state drive (SSD) and field-programmable gate array (FPGA) and configured to perform dimensionality reduction on the downsampled training data to generate training data batches as recited in claim 1.
On the other hand, Theodorou achieved the aforementioned limitations by providing mechanisms of
a computational storage consisting of a solid-state drive (SSD) (Theodorou: paragraph 0209: disclose Solid-State Drive (SSD)) and field-programmable gate array (FPGA) (Theodorou: paragraph 0177: disclose a field programmable gate array (FPGA)) and configured to perform dimensionality reduction on the downsampled training data to generate training data batches (Theodorou: paragraph 0046: disclose GANs struggle with high dimensional, sparse data, causing existing synthetic EHR approaches to produce relatively low-dimensional data through the aggregation of visits, combination of codes, removal of rare codes, and/or other dimensionality reductions).
The motivation for doing so would have been to provide the necessary amount of utility for real-world use, there is a need for a generative AI model that can produce suitable high-dimensional synthesized EHR data (Theodorou: paragraph 0016).
It is noted, however, neither Heaton nor Theodorou specifically detail the aspects of
performing near-storage data processing couple to the DRAM as recited in claim 1.
On the other hand, Yanada achieved the aforementioned limitations by providing mechanisms of
performing near-storage data processing couple to the DRAM (Yanada: paragraph 0040: disclose pre-processing section stores (writes) image data generated through the pre-processing (hereinafter referred to as “pre-processed image data”) in the DRAM).
The motivation for doing so would have been to an image processing device, for example, a storage device, for example, such as a dynamic random access memory (DRAM), configured to temporarily store image data to be subjected to image processing is connected (Yanada: paragraph 0003).
Heaton, Yanada and Theodorou are analogous art because they are from the “same field of endeavor” and both from the same “problem-solving area”. Namely, they are both from the field of “Machine Learning System”.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine the systems of Heaton, Yanada and Theodorou because they are both directed to machine learning system and both are from the same field of endeavor. The skilled person would therefore regard it as a normal option to include the restriction features of Theodorou and Yanada with the method described by Heaton in order to solve the problem posed.
Therefore, it would have been obvious to combine Theodorou and Yanada with Heaton to obtain the invention as specified in instant claim 1.
As per claim 2, most of the limitations of this claim have been noted in the rejection of claim 1 above.
It is noted, however, Heaton did not specifically detail the aspects of
wherein the dimensionality reduction includes random projection as recited in claim 2.
On the other hand, Theodorou achieved the aforementioned limitations by providing mechanisms of
wherein the dimensionality reduction includes random projection (Theodorou: paragraph 0097: disclose random or pseudo-random sampling throughout the generation process may be used to add diversity, as sampling the same sequence from the same starting point will yield different results).
As per claim 3, most of the limitations of this claim have been noted in the rejection of claim 1 above. In addition, Heaton disclose, wherein the computational storage provides the GPU with the training data batches through a peer-to-peer direct memory access (P2P-DMA) operation (Heaton: Fig. 7 Elements 746a and 746d: disclose a Peer to Peer DMA operation).
As per claim 4, most of the limitations of this claim have been noted in the rejection of claim 1 above. In addition, Heaton disclose, wherein the computational storage includes multiple computing units, each computing unit including: buffer blocks configured to store input tiles of the downsampled training data and an output tile of the training data batches; and a digital signal processing (DSP) unit configured to multiply and add the input tiles to generate the output tile (Heaton: Fig. 7: disclose multiple computing units and I/O Device Element 732 for output).
As per claim 5, most of the limitations of this claim have been noted in the rejection of claims 1 and 4 above. In addition, Heaton disclose, wherein the buffer blocks store two of the input tiles (Heaton: Col 5 Lines 49-52: disclose multiple processing engines arranged in a matrix of rows and columns to perform computations used in neural networks such as integration, convolution, correlation, and/or matrix multiplication).
As per claim 6, most of the limitations of this claim have been noted in the rejection of claims 1, 4 and 5 above. In addition, Heaton disclose, wherein the input tiles are double-buffered simultaneously by the buffer blocks (Heaton: Col 5 Lines 52-54: disclose State buffer can be used to temporarily store data for loading into processing engine array).
As per claim 7, most of the limitations of this claim have been noted in the rejection of claims 1 and 4 above. In addition, Heaton disclose, wherein a data access pattern of the two input tiles is sequential (Heaton: Col 10 Lines 59-60: disclose set of shared data can be similarly loaded into subsequent accelerators in a sequence).
As per claim 8, most of the limitations of this claim have been noted in the rejection of claims 1 and 4 above. In addition, Heaton disclose, wherein the input tiles have a tiled data format, which are reordered from a row-major layout to a data layout for input matrices where the input tiles are in a contiguous region of memory (Heaton: Col 5 Lines 49-52: disclose multiple processing engines arranged in a matrix of rows and columns to perform computations used in neural networks such as integration, convolution, correlation, and/or matrix multiplication).
As per claim 9, most of the limitations of this claim have been noted in the rejection of claims 1 and 4 above.
It is noted, however, Heaton did not specifically detail the aspects of
wherein the downsampled training data include data processed through image resize, data argumentation and/or dimension reshape for the training data as recited in claim 9.
On the other hand, Theodorou achieved the aforementioned limitations by providing mechanisms of
wherein the downsampled training data include data processed through image resize, data argumentation and/or dimension reshape for the training data (Theodorou: paragraph 0046: disclose GANs struggle with high dimensional, sparse data, causing existing synthetic EHR approaches to produce relatively low-dimensional data through the aggregation of visits, combination of codes, removal of rare codes, and/or other dimensionality reductions).
As per claim 10, most of the limitations of this claim have been noted in the rejection of claims 1 and 4 above.
It is noted, however, Heaton did not specifically detail the aspects of
wherein the training data is partitioned and then buffered in the DRAM as recited in claim 10.
On the other hand, Theodorou achieved the aforementioned limitations by providing mechanisms of
wherein the training data is partitioned and then buffered in the DRAM (Theodorou: paragraph 0102: disclose generate discrete versions of continuous variables, such as lab values and temporal gaps, the range of each variable is divided into a plurality of “buckets”).
As per claim 11, Heaton disclose, A method for operating a training system (Heaton: Col 8 Lines 52-53: disclose training a neural network model in which the weight values), the method comprising: remaining limitations in this claim 11 are similar to the limitations in claim 1. Therefore, examiner rejects these remaining limitations under the same rationale as limitations rejected under claim 1.
As per claim 12, limitations of this claim are similar to claim 2. Therefore, examiner rejects claim 12 limitations under the same rationale as claim 2.
As per claim 13, limitations of this claim are similar to claim 3. Therefore, examiner rejects claim 13 limitations under the same rationale as claim 3.
As per claim 14, limitations of this claim are similar to claim 4. Therefore, examiner rejects claim 14 limitations under the same rationale as claim 4.
As per claim 15, limitations of this claim are similar to claim 5. Therefore, examiner rejects claim 15 limitations under the same rationale as claim 5.
As per claim 16, limitations of this claim are similar to claim 6. Therefore, examiner rejects claim 16 limitations under the same rationale as claim 6.
As per claim 17, limitations of this claim are similar to claim 7. Therefore, examiner rejects claim 17 limitations under the same rationale as claim 7.
As per claim 18, limitations of this claim are similar to claim 8. Therefore, examiner rejects claim 18 limitations under the same rationale as claim 8.
As per claim 19, limitations of this claim are similar to claim 9. Therefore, examiner rejects claim 19 limitations under the same rationale as claim 9.
As per claim 20, limitations of this claim are similar to claim 10. Therefore, examiner rejects claim 20 limitations under the same rationale as claim 10.
Response to Arguments
Examiner withdraws 35 U.S.C. 101 rejection due to applicant’s arguments and amendments.
Applicant’s arguments with respect to claims 1 and 11 regrading 35 U.S.C. 103 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Pub. US 2022/0405005 A1 disclose “Three Dimensional Circuit Systems And Methods Having Memory Hierarchies”
US Pub. US 2015/0370697 A1 disclose “MEMORY SWITCHING PROTOCOL WHEN SWITCHING OPTICALLY-CONNECTED MEMORY”
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PAVAN MAMILLAPALLI/
Primary Examiner, Art Unit 2159
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