DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the amendment filed July 27, 2026, claims 1, 4-8, 10-11 and 13-20 have been amended, claims 1 - 20 are currently pending for examination.
Response to Arguments
Regarding claim objections applicant’s arguments, see page 10 paragraphs 2, filed July 27, 2026, with respect to claims 1-20 have been fully considered and are persuasive. The claim objections of claims 1-20 have been withdrawn.
Regarding 35 U.S.C. 112 applicant’s arguments, see page 10 paragraphs 4, filed July 27, 2026, with respect to claim 10 have been fully considered and are persuasive. Therefore, the 112 rejection has been withdrawn.
Regarding 35 U.S.C. 103 applicant’s arguments, see page 10 paragraphs 6 - page 15, filed July 27, 2026, with respect to claims 1, 14 and 15 have been fully considered and are not persuasive.
Regarding claims 1, 14 and 15, the applicant argued that, see page 14 lines 15-22, “…The Office cites pages 27 and 49-50 of Xilinx and maps the virtual machine bridge block in Applicant's claim to the USB/CAN blocks (Fig. 1-1) in Xilinx, asserting that the USB/CAN in Xilinx provides "a MAC frame layer interfacing with Central Interconnect VMs / SoCs whose software is organized in VMs." Office Action at 4. Applicant respectfully disagrees. See, e.g., id. at p. 50. Neither passage nor the Fig. 1-1 block diagram itself contains any reference to a virtual machine, a hypervisor, or software organized into VMs. The disclosure at these citations is limited to hardware bus topology and protocol-level peripheral connectivity. The phrase "SOCs whose software is organized in VMs" does not appear in any of the cited passages in Xilinx. It is unclear to Applicant how the Office has determined that Xilinx teaches VM bridge blocks, virtual machines that run on a System-on-Chip, and VM bridge blocks that interface with virtual machines running on a System-on-Chip. A rejection must be supported by what a reference actually describes, not by a label attached to a reference citation that does not itself contain the corresponding teaching. If the Office is to maintain the rejection, Applicant respectfully requests what the Office has mapped to each of these components in Xilinx and where in Xilinx the interfacing between the two components is described.
In response to applicant's argument, the examiner respectfully disagrees with the argument above. See sections 7 and 8 below.
Regarding amended claims 1, 14 and 15, Xilinx discloses, media access control (MAC) controllers (see Fig.1-1, GigE/GEM/MAC controllers, I/O peripherals) configured to provide a MAC port layer controlling exchange of information over a data link (see page 479, section 16.1, the registers are used to configure the features of the MAC port layer controlling exchange of information over a data link interfaces); virtual machine (VM) bridge blocks (see Fig.1-1, USB/CAN) configured to provide a MAC frame layer interfacing with System-on-Chip VMs (see page 27, 49-50, USB/CAN provides a MAC frame layer interfacing with Central Interconnect VMs / SoCs whose software is organized in VMs, the MAC layer is the link layer, or L2, which is included in the USB or CAN interfaces. The data communication that comes from other Socs whose software is organized in VMs, is indistinguishable from data communication that comes from any other source, therefore the technical features of the Socs and VMs do not further limit the MAC layer of the blocks); a host port (see Fig.1-1, High-Performance Ethernet port) configured to receive, from a host (see Fig.1-1, USB host controller), programming/configuration information for the system (see Fig.1-1, page 479-480, the port receiving programming and configuration information); a local memory controller (see Fig. 1-1, Memory Interfaces and DDR2/3 Controller), configured to facilitate the MAC controllers, the VM bridge blocks and the SW Ethernet port in cooperating with a local memory (see Fig. 1-1, the MAC controllers, the VM bridge blocks and the SW Ethernet port in connecting/interfacing with L2 Cache and controller/a local memory); and queue handlers (see Fig.1-1, Fig. 10-4, DDRC queue handlers) configured to provide queue management for the MAC controllers, the VM bridge blocks and the host port during cooperation of the MAC controllers, the VM bridge blocks and the host port with the local memory via the local memory controller (see page 299, section 10.3., para. 1, the DDRC is comprised of queues for pending read and write transactions and a scheduler that pops off the queues / queue management and sends the next transaction to the DDR PHY, between the DDRI and the DDRC, there is arbitration logic to decide which transaction is sent to the DDRC next / cooperation/ scheduling interface of MAC, VM, port and memory).
Regarding claims 1, 9 and 17, the applicant further argued that, see page 14 lines 15-22, “…The Office concedes that Xilinx fails to teach this limitation and cites Xu for curing this deficiency. Office Action at 5. Specifically, the Office maps the configuration host port (previously SW Ethernet Port) and the host in Applicant's claim to virtual network interface cards 52a-d and host 14(1) in Xu, through a physical Ethernet port. Id. The Office further cites host 14(1)/virtual switch 52/VSM 54 as mapping a port profile to each physical network interface. Id. This mapping does not correspond to what Xu describes. See, e.g., Xu, Figures 1 and 2a- b. In Xu, host 14(1) is the server being configured and not an external host transmitting configuration information to a separate system. Id. … The Office's mapping therefore requires host 14(1) to simultaneously stand in for both "the host" and the claimed "system" receiving information from that host, which is a reading not supported by Xu's actual disclosure of a single self-configuring server. Thus, Xilinx and Xu, individually or in combination, do not teach, suggest, or in any way render obvious the features of independent claim 1.
In response to applicant's argument, the examiner respectfully disagrees with the argument above. See sections 7 and 8 below.
Regarding amended claims 1, 14 and 15, Xu discloses, a configuration host port (see Fig.1, para. 0014, Fig.2A-2B, Virtual network interface cards 52a, 52b, 52c, 52d are mapped to a physical port, such as an Ethernet port, associated with host 14(1) / a configuration host port) configured to receive, from a host (see Fig.2A-B, host 14(1)), programming/configuration information for the system (see para. 0019, 0020, host 14(1), virtual switch 52, and/or VSM 54 maps a port profile to each physical network interface / receiving programming/configuration information for the system, see also para. 0021, an operating system 95, portions of which is resident in memory 85 and executed by the processor 80, functionally organize host 14(1), invoking network operations in support of software processes and/or services executing on the device, clearly “an ethernet port” associated/maps to a host 14(1) are different hardware).
Under the broadest reasonable interpretation, the combination of the systems as disclosed by Xilinx and Xu reads upon “media access control (MAC) controllers configured to provide a MAC port layer controlling exchange of information over a data link; virtual machine (VM) bridge blocks configured to provide a MAC frame layer interfacing with System-on-Chip VMs; a configuration host port configured to receive, from a host, programming information, configuration information, or both, for the system; a local memory controller configured to facilitate the MAC controllers, the VM bridge blocks and the configuration host port in cooperating with a local memory; and queue handlers configured to provide queue management for the MAC controllers, the VM bridge blocks and the configuration host port during cooperation of the MAC controllers, the VM bridge blocks and the configuration host port with the local memory via the local memory controller” as recites in the claim.
Claim Objections
Claims 1-20 are objected to because of the following informalities:
Claim 1 recites “MAC controllers" and "VM bridge blocks". The terms "MAC controllers" and "VM bridge blocks" in claim 1, do not clearly define how many items are meant. If 2 or more items are meant, then "a plurality of" is recommended, which is the interpretation followed below.
Claims 14 and 15 are also objected for the same reason as set forth above for claim 1.
Claims 2-13 and 16-20 are also objected to since they are dependent on the objected base independent claims 1 and 15, respectfully, as set forth above.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
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Claim 1 has been amended to recite in lines 6-8, " ... a configuration host port configured to receive, from a host, programming information, configuration information, or both, for the system”. Neither the claim nor the specification further describe, “… a configuration host port configured to receive, from a host, programming information, configuration information, or both, for the system”. Paragraph 0103 of instant application disclose, “Reference 1008 in FIG. 4 denotes a L2/L2+ forwarding database (static DA tables, dynamic DA hash tables, VLAN ID hash tables, IP address routing tables, ARP table) configured to cooperate with the SW port 1005, e.g., for receiving therefrom configuration and management instructions from the host.” Figure 4 of instant applicant, shown above, of instant application showing, “[0102] a (single) queue handler 1006C (#(N+M+1)) for the host port 1005”. The claims and the specification of the instant application does not describe the method/step, “... a configuration host port configured to receive, from a host, programming information, configuration information, or both, for the system.” Therefore claim 1 is rejected under 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement
The subject matter was not described in the specification (see paragraphs 0102, 0103) in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and /or use the invention.
Claims 14 and 15 are also rejected for the same reason as set forth above for claim 1.
Claims 2-13, and 16-20 are also rejected since they are dependent on the rejected dependent claims 1 and 15, respectfully, as set forth above.
Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 has been amended to recite in lines 6-8, " ... a configuration host port configured to receive, from a host, programming information, configuration information, or both, for the system”. It is unclear whether a system comprising: a configuration host port configured to receive, from a host.
Claims 14 and 15 are also rejected for the same reason as set forth above for claim 1.
Claims 2-13, and 16-20 are also rejected since they are dependent on the rejected dependent claims 1 and 15, respectfully, as set forth above.
For purpose of examination, the examiner interprets the limitation as best understood.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-10, 12, 14-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over XILINX (XILINX: "Zynq-7000AII Programmable SoCTechnical Reference
ManualUG585 (v1.10) February 23, 2015",INTERNET CITATION, 22 January 2016 (2016-01-22), IDS submitted 8/28/2023), and further in view of Xu et al. (US Pub. No.: 2016/0254956).
As per claim 1, XILINX disclose A system (see Fig. 1-1, page 27, Zynq-7000 AP SoC), comprising:
media access control (MAC) controllers (see Fig.1-1, GigE/GEM/MAC controllers, I/O peripherals) configured to provide a MAC port layer controlling exchange of information over a data link (see page 479, section 16.1, the registers are used to configure the features of the MAC port layer controlling exchange of information over a data link interfaces);
virtual machine (VM) bridge blocks (see Fig.1-1, USB/CAN) configured to provide a MAC frame layer interfacing with System-on-Chip VMs (see page 27, 49-50, USB/CAN provides a MAC frame layer interfacing with Central Interconnect VMs / SoCs whose software is organized in VMs, the MAC layer is the link layer, or L2, which is included in the USB or CAN interfaces. The data communication that comes from other Socs whose software is organized in VMs, is indistinguishable from data communication that comes from any other source, therefore the technical features of the Socs and VMs do not further limit the MAC layer of the blocks, see also page 61, 66 );
a host port (see Fig.1-1, High-Performance Ethernet port) configured to receive, from a host (see Fig.1-1, USB host controller), programming/configuration information for the system (see Fig.1-1, page 479-480, the port receiving programming and configuration information);
a local memory controller (see Fig. 1-1, Memory Interfaces and DDR2/3 Controller), configured to facilitate the MAC controllers, the VM bridge blocks and the SW Ethernet port in cooperating with a local memory (see Fig. 1-1, the MAC controllers, the VM bridge blocks and the SW Ethernet port in connecting/interfacing with L2 Cache and controller/a local memory, the MAC layer is the link layer, or L2, which is included in the USB or CAN interfaces. The data communication that comes from other Socs whose software is organized in VMs, is indistinguishable from data communication that comes from any other source, therefore the technical features of the Socs and VMs do not further limit the MAC layer of the blocks); and
queue handlers (see Fig.1-1, Fig. 10-4, DDRC queue handlers) configured to provide queue management for the MAC controllers, the VM bridge blocks and the host port during cooperation of the MAC controllers, the VM bridge blocks and the host port with the local memory via the local memory controller (see page 299, section 10.3., para. 1, the DDRC is comprised of queues for pending read and write transactions and a scheduler that pops off the queues / queue management and sends the next transaction to the DDR PHY, between the DDRI and the DDRC, there is arbitration logic to decide which transaction is sent to the DDRC next / cooperation/ scheduling interface of MAC, VM, port and memory, the MAC layer is the link layer, or L2, which is included in the USB or CAN interfaces. The data communication that comes from other Socs whose software is organized in VMs, is indistinguishable from data communication that comes from any other source, therefore the technical features of the Socs and VMs do not further limit the MAC layer of the blocks).
Although XILINX disclose a host port configured to receive, from a host programming/configuration information for the system;
XILINX however does not explicitly disclose “a configuration host port” configured to receive, from a host, programming information, configuration information, or both, for the system;
Xu however disclose a configuration host port (see Fig.1, para. 0014, Fig.2A-2B, Virtual network interface cards 52a, 52b, 52c, 52d are mapped to a physical port, such as an Ethernet port, associated with host 14(1) / a configuration host port) configured to receive, from a host (see Fig.2A-B, host 14(1)), programming information, configuration information, or both, for a system (see para. 0019, 0020, host 14(1), virtual switch 52, and/or VSM 54 maps a port profile to each physical network interface / receiving programming information, configuration information, or both, for the system, see also para. 0021, an operating system 95, portions of which is resident in memory 85 and executed by the processor 80, functionally organize host 14(1), invoking network operations in support of software processes and/or services executing on the device, clearly “an ethernet port” associated/maps to a host 14(1) are different hardware);
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the functionality of “a configuration host port” configured to receive, from a host, programming information, configuration information, or both, for the system, as taught by Xu, in the system of Xilinx, so as to automatically detect and configure server uplink network interfaces in a network environment and protects the applications and services against disruptions, see Xu, paragraphs 0003, 0009.
As per claim 2, the combination of Xilinx and Xu disclose the system of claim 1.
Xilinx further disclose the system further comprising MAC wrappers between the MAC controllers and the queue handlers, the MAC wrappers including MAC translator and frame router features, wherein the MAC translator features act between the MAC controllers and the frame router features (see page 77, 80, MAC translator/wrappers between the MAC controllers and the queue handlers, the table/MAC translator between the MAC controllers and the frame router, see also page 86-87).
As per claim 3, the combination of Xilinx and Xu disclose the system of claim 1.
Xilinx further disclose the system further comprising VM wrappers between the VM bridge blocks and the queue handlers, the VM wrappers including MAC translator and frame router features, wherein the MAC translator features act between the VM bridge blocks and the frame router features (see page 77, 80, VM translators/ wrappers between the VM bridge and the queue handlers, the table/MAC translator between the MAC controllers and the frame router, see also page 86-87).
As per claim 4, the combination of Xilinx and Xu disclose the system of claim 1.
Xilinx further disclose wherein the host port is configured to receive programming information, configuration programming/configuration information, or both for the system via an Advanced eXtensible Interface slave port or embedded direct memory access (DMA) (see Fig. 1-1, page 27, the host port is configured to receive the programming and configuration information for the system via an Advanced eXtensible Interface (AXI) slave port, see data flow, master to slave), and
Xu further disclose the configuration host port is configured to receive programming information, configuration programming/configuration information, or both for the system via an Advanced eXtensible Interface slave port or embedded direct memory access (DMA) (see para. 0020, Host 14(1) can communicate upstream to a network fabric, such as network 12, via physical network interface cards 60a, 60b, and/or 60c. In the present example, physical network interface cards 60a, 60b, and/or 60c can communicatively connect host 14(1) to leaf switch 20(1). Each physical network interface card 60a, 60b, and 60c may include one or more Ethernet ports, which can physically connect host 14(1) to various network elements, including leaf switch 20(1). Virtual machines 50 may have associated virtual network interface cards (vNICs), which virtual switch 52 associates with network interface 60).
As per claim 5, the combination of Xilinx and Xu disclose the system of claim 1.
Xilinx further disclose wherein the local memory controller is a multi-port memory controller configured to access a static random access memory serving as a frame buffer in the local memory (see Fig.1-1, Fig.15-2, page 27, 394, a multi-port memory controller configured to access a static random access memory/frame buffer in the local memory).
As per claim 7, the combination of Xilinx and Xu disclose the system of claim 1.
Xilinx further disclose the system further comprising a forwarding database configured to cooperate with the host port in receiving configuration and management instructions (see Fig.1-1, page 479-480, AHB interfacing with DMA controller/ a forwarding database, FIFO, the port receiving programming and configuration information); and
Xu further disclose the system further comprising a forwarding database configured to cooperate with the configuration host port in receiving configuration and management instructions (see Fig. 2A-B, para. 0019, 0020, a port profile manager 56 / a forwarding database is provisioned for managing port profiles, where each port profile is configured for application to one or more network interfaces associated with providing virtual machines 50 network capability, virtual switch 52 and/or VSM 54 defines each port profile).
Motivation same as claim 1.
As per claim 8, the combination of Xilinx and Xu disclose the system of claim 7.
Xilinx further disclose wherein the forwarding database is configured to be selectively bypassed for frames coming from host ports, virtual machine ports or both (see page 61, transactions to bypass for frames coming from host/virtual machine ports).
As per claim 9, the combination of Xilinx and Xu disclose the system of claim 8.
Xilinx further disclose wherein the forwarding database is configured to be selectively bypassed via a software-configurable destination port (see page 61, transactions to bypass virtual machine ports / SW ports).
As per claim 10, the combination of Xilinx and Xu disclose the system of claim 1.
Xilinx further disclose wherein one or more of the queue handlers comprise: a write subsection supporting concurrent incoming frames received from MAC ports, VM ports, or both in the system (see page 85, 89, a write subsection for incoming frames received from MAC and VM ports in the system, ); a read subsection implementing quality-of-service priorities for outgoing frames to MAC ports in the system (see page 32, 33, read section/read support to implement quality-of-service priorities for outgoing frames to MAC ports in the system, the MAC layer is the link layer, or L2, which is included in the USB or CAN interfaces. The data communication that comes from other Socs whose software is organized in VMs, is indistinguishable from data communication that comes from any other source, therefore the technical features of the Socs and VMs do not further limit the MAC layer of the blocks).
As per claim 12, the combination of Xilinx and Xu disclose the system of claim 1.
Xilinx further disclose the system comprising functional safety mechanisms including a fault collector feature (see page 78, 82, a fault entry/collector) and a debug feature (see page 90, 108, 109, debug logic/feature).
As per claim 14, XILINX disclose A vehicle (see section 1.1, page 26, an automotive / a vehicle), comprising:
an on-board communication network (see Fig.1-1, page 27, 28, 479, Zynq-7000 AP SoC with Gigabit Ethernet Controller (GEM) / an on-board communication network), wherein the network comprises a system configured to provide media access control (MAC) (MAC) features, router features, switch features, gateway features, or a combination thereof, for the on-board communication network (see Fig.1-1, page 27, 28, 479, the Gigabit Ethernet Controller (GEM) implements a 10/100/1000 Mb/s Ethernet MAC), the system comprising:
MAC controllers (see Fig.1-1, GigE/GEM/MAC controllers, I/O peripherals) configured to provide a MAC port layer controlling exchange of information over a data link (see page 479, section 16.1, the registers are used to configure the features of the MAC port layer controlling exchange of information over a data link interfaces);
virtual machine (VM) bridge blocks (see Fig.1-1, USB/CAN) configured to provide a MAC frame layer interfacing with System-on-Chip VMs (see page 27, 49-50, USB/CAN provides a MAC frame layer interfacing with Central Interconnect VMs / SoCs whose software is organized in VMs);
a host port (see Fig.1-1, High-Performance Ethernet port) configured to receive, from a host (see Fig.1-1, USB host controller), programming information, configuration information or both for the system (see Fig.1-1, page 479-480, the port receiving programming and configuration information);
a local memory controller (see Fig. 1-1, Memory Interfaces and DDR2/3 Controller), configured to facilitate the MAC controllers, the VM bridge blocks and the host port in cooperating with a local memory (see Fig. 1-1, the MAC controllers, the VM bridge blocks and the SW Ethernet port in connecting/interfacing with L2 Cache and controller/a local memory); and
queue handlers (see Fig.1-1, Fig. 10-4, DDRC queue handlers) configured to provide queue management for the MAC controllers, the VM bridge blocks and the host port during cooperation of the MAC controllers, the VM bridge blocks and the host port with the local memory via the local memory controller (see page 299, section 10.3., para. 1, the DDRC is comprised of queues for pending read and write transactions and a scheduler that pops off the queues / queue management and sends the next transaction to the DDR PHY, between the DDRI and the DDRC, there is arbitration logic to decide which transaction is sent to the DDRC next / cooperation/ scheduling interface of MAC, VM, port and memory).
Although XILINX disclose a host port configured to receive, from a host programming/configuration information for the system;
XILINX however does not explicitly disclose “a configuration host port” configured to receive, from a host, programming/configuration information for the system;
Xu however does not explicitly disclose a configuration host port (see Fig.1, para. 0014, Fig.2A-2B, Virtual network interface cards 52a, 52b, 52c, 52d are mapped to a physical port, such as an Ethernet port, associated with host 14(1) / a software (SW) Ethernet port) configured to receive, from a host (see Fig.2A-B, host 14(1)), programming/configuration information for the system (see para. 0019, 0020, host 14(1), virtual switch 52, and/or VSM 54 maps a port profile to each physical network interface / receiving programming/configuration information for the system, see also para. 0021, an operating system 95, portions of which is resident in memory 85 and executed by the processor 80, functionally organize host 14(1), invoking network operations in support of software processes and/or services executing on the device);
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the functionality of a configuration host port configured to receive, from a host, programming/configuration information for the system, as taught by Xu, in the system of Xilinx, so as to automatically detect and configure server uplink network interfaces in a network environment and protects the applications and services against disruptions, see Xu, paragraphs 0003, 0009.
As per claim 15, XILINX disclose A networking (see Fig. 1-1, page 27, Zynq-7000 AP SoC) method, comprising:
controlling exchange of information over a data link via a media access control (MAC) port layer comprising MAC controllers (see Fig.1-1, GigE/GEM/MAC controllers, I/O peripherals, see page 479, section 16.1, the registers are used to configure the features of the MAC port layer controlling exchange of information over a data link interfaces);
providing a MAC frame layer interfacing with System-on-Chip virtual machines (VMs) via VM bridge blocks (see Fig.1-1, USB/CAN, see page 27, 49-50, USB/CAN provides a MAC frame layer interfacing with Central Interconnect VMs / SoCs whose software is organized in VMs);
receiving programming information, configuration information or both , via a host port (see Fig.1-1, High-Performance Ethernet port, page 479-480, the port receiving programming and configuration information);
facilitating cooperation with a local memory of the MAC controllers, the VM bridge blocks and the host port via a local memory controller (see Fig. 1-1, Memory Interfaces and DDR2/3 Controller, see page 27, the MAC controllers, the VM bridge blocks and the SW Ethernet port in connecting/interfacing with L2 Cache and controller/a local memory); and
providing queue management for the MAC controllers, the VM bridge blocks and the host port, during cooperation of the MAC controllers, the VM bridge blocks and the host port with the local memory via the local memory controller (see Fig.1-1, Fig. 10-4, DDRC queue handlers, see page 299, section 10.3., para. 1, the DDRC is comprised of queues for pending read and write transactions and a scheduler that pops off the queues / queue management and sends the next transaction to the DDR PHY, between the DDRI and the DDRC, there is arbitration logic to decide which transaction is sent to the DDRC next / cooperation/ scheduling interface of MAC, VM, port and memory).
Although XILINX disclose receiving programming information, configuration information or both via a host port;
XILINX however does not explicitly disclose receiving programming information, configuration information or both via “a configuration host port”;
Xu however does not explicitly disclose a configuration host port (see Fig.1, para. 0014, Fig.2A-2B, Virtual network interface cards 52a, 52b, 52c, 52d are mapped to a physical port, such as an Ethernet port, associated with host 14(1) / a software (SW) Ethernet port) receiving programming information, configuration information or both via “a configuration host port” (see Fig.2A-B, host 14(1)), programming information, configuration information or both for the system (see para. 0019, 0020, host 14(1), virtual switch 52, and/or VSM 54 maps a port profile to each physical network interface / programming information, configuration information or both for the system, see also para. 0021, an operating system 95, portions of which is resident in memory 85 and executed by the processor 80, functionally organize host 14(1), invoking network operations in support of software processes and/or services executing on the device);
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the functionality of receiving programming information, configuration information or both for the system, as taught by Xu, in the system of Xilinx, so as to automatically detect and configure server uplink network interfaces in a network environment and protects the applications and services against disruptions, see Xu, paragraphs 0003, 0009.
As per claim 16, claim 16 is rejected the same way as claim 4.
As per claim 17, claim 17 is rejected the same way as claim 5.
As per claim 19, claim 19 is rejected the same way as claim 7.
Allowable Subject Matter
Claims 6, 11, 13, 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lovett (US Pub. No.:2013/0107872) – see para. 0197, “Enterprise Manager 530 supports multi-chassis management, complex provisioning, interfaces to client GUIs, and generally operates at a relatively high level of abstraction, as does CLI 532. Platform Manager 531 generally performs in-chassis (or single-chassis) management operations and tends to manipulate system objects directly at a relatively low level of abstraction. Several SW modules operate in close cooperation with the Platform Manager, including Chassis Manager (CM) 533, Query Engine 534, Repository Manager 535, VIOC Manager 536, Interface Manager 537, L2 Forwarding DataBase (FDB) Manager 538, VLAN Manager 539, and Other Management Code 540”.
Beecroft (US Pub. No.:2016/0337146) – see para. 0031, “ … an Ethernet bridge or router comprising a network fabric adapted to provide interconnectivity to a plurality of Ethernet ports, each of the Ethernet ports being adapted to receive and/or transmit Ethernet frames, and wherein the Ethernet bridge or router further comprises software instructions for operating an encapsulator to generate a Fabric Protocol Data Unit from a received Ethernet Protocol Data Unit, the Fabric Protocol Data Unit comprising a header portion, and a payload portion which comprises the Ethernet Protocol Data Unit concerned, and wherein the encapsulator is operable to transform Ethernet destination address information from the Ethernet Protocol Data Unit into a routing definition for the network fabric, and to include this routing definition in the header portion of the Fabric Protocol Data Unit”.
Rumyankov (US Pub. No.:2018/0359181) – see para. 0002, “The present technology relates to the data transmission technology in packet-switched Software Defined Networks (SDN), comprising switches with Ethernet ports and controlled by software controllers”.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAKERAM JANGBAHADUR whose telephone number is (571)272-1335. The examiner can normally be reached on M-F 7 am - 4 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ian Moore can be reached on 571-272-3085. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAKERAM JANGBAHADUR/
Primary Examiner, Art Unit 2469
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