DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in Instant Application.
Priority
Examiner acknowledges Applicant’s claim to priority benefits of IT 102022000019233 filed September 20, 2022.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 8/28/2023 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered if signed and initialed by the Examiner.
Specification
The disclosure is objected to because of the following informalities: Configuration Host Port 1005 of Fig. 4 is named with different terminology in the description (e.g. "SW port 1005", paragraph 0103, or "host port 1005" paragraphs 0099, 0132) and consistent terminology should be used. The port 1005 includes AXIS and IRQ interfaces, but no Ethernet interface, and no mention of "Ethernet" for port 1005 is cited in the description. The terms are interpreted as a communication port
Claim Objections
Claims 1-20 are objected to because of the following informalities:
Claim 1 recites, “programming/configuration information for the system”, in line 7. For clarity it is suggested to replace the operator "/" with words, for example “at least one A or B”.
Claims 4, 5, 8, 10, 11, 13-17 and 20 are also objected for the same reason as set forth above for claim 1.
Claims 2-3, 6-7, 9, 12 and 18-19 are also objected since there are dependent on the objected base independent claim 1 and 15, respectfully.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “some” in claim 10 is a relative term which renders the claim indefinite. The term “wherein at least some of the queue handlers comprise” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-10, 12, 14-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over XILINX (XILINX: "Zynq-7000AII Programmable SoCTechnical Reference
ManualUG585 (v1.10) February 23, 2015",INTERNET CITATION, 22 January 2016 (2016-01-22), IDS submitted 8/28/2023), and further in view of Xu et al. (US Pub. No.: 2016/0254956).
As per claim 1, XILINX disclose A system (see Fig. 1-1, page 27, Zynq-7000 AP SoC), comprising:
media access control (MAC) controllers (see Fig.1-1, GigE/GEM/MAC controllers, I/O peripherals) configured to provide a MAC port layer controlling exchange of information over a data link (see page 479, section 16.1, the registers are used to configure the features of the MAC port layer controlling exchange of information over a data link interfaces);
virtual machine (VM) bridge blocks (see Fig.1-1, USB/CAN) configured to provide a MAC frame layer interfacing with System-on-Chip VMs (see page 27, 49-50, USB/CAN provides a MAC frame layer interfacing with Central Interconnect VMs / SoCs whose software is organized in VMs);
a Ethernet port (see Fig.1-1, High-Performance Ethernet port) configured to receive, from a host (see Fig.1-1, USB host controller), programming/configuration information for the system (see Fig.1-1, page 479-480, the port receiving programming and configuration information);
a local memory controller (see Fig. 1-1, Memory Interfaces and DDR2/3 Controller), configured to facilitate the MAC controllers, the VM bridge blocks and the SW Ethernet port in cooperating with a local memory (see Fig. 1-1, the MAC controllers, the VM bridge blocks and the SW Ethernet port in connecting/interfacing with L2 Cache and controller/a local memory); and
queue handlers (see Fig.1-1, Fig. 10-4, DDRC queue handlers) configured to provide queue management for the MAC controllers, the VM bridge blocks and the SW Ethernet port during cooperation of the MAC controllers, the VM bridge blocks and the SW Ethernet port with the local memory via the local memory controller (see page 299, section 10.3., para. 1, the DDRC is comprised of queues for pending read and write transactions and a scheduler that pops off the queues / queue management and sends the next transaction to the DDR PHY, between the DDRI and the DDRC, there is arbitration logic to decide which transaction is sent to the DDRC next / cooperation/ scheduling interface of MAC, VM, port and memory).
Although XILINX disclose a Ethernet port configured to receive, from a host programming/configuration information for the system;
XILINX however does not explicitly disclose “a software (SW) Ethernet port” configured to receive, from a host, programming/configuration information for the system;
Xu however does not explicitly disclose a software (SW) Ethernet port (see Fig.1, para. 0014, Fig.2A-2B, Virtual network interface cards 52a, 52b, 52c, 52d are mapped to a physical port, such as an Ethernet port, associated with host 14(1) / a software (SW) Ethernet port) configured to receive, from a host (see Fig.2A-B, host 14(1)), programming/configuration information for the system (see para. 0019, 0020, host 14(1), virtual switch 52, and/or VSM 54 maps a port profile to each physical network interface / receiving programming/configuration information for the system, see also para. 0021, an operating system 95, portions of which is resident in memory 85 and executed by the processor 80, functionally organize host 14(1), invoking network operations in support of software processes and/or services executing on the device);
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the functionality of a software (SW) Ethernet port configured to receive, from a host, programming/configuration information for the system, as taught by Xu, in the system of Xilinx, so as to automatically detect and configure server uplink network interfaces in a network environment and protects the applications and services against disruptions, see Xu, paragraphs 0003, 0009.
As per claim 2, the combination of Xilinx and Xu disclose the system of claim 1.
Xilinx further disclose the system further comprising MAC wrappers between the MAC controllers and the queue handlers, the MAC wrappers including MAC translator and frame router features, wherein the MAC translator features act between the MAC controllers and the frame router features (see page 77, 80, MAC translator/wrappers between the MAC controllers and the queue handlers, the table/MAC translator between the MAC controllers and the frame router, see also page 86-87).
As per claim 3, the combination of Xilinx and Xu disclose the system of claim 1.
Xilinx further disclose the system further comprising VM wrappers between the VM bridge blocks and the queue handlers, the VM wrappers including MAC translator and frame router features, wherein the MAC translator features act between the VM bridge blocks and the frame router features (see page 77, 80, VM translators/ wrappers between the VM bridge and the queue handlers, the table/MAC translator between the MAC controllers and the frame router, see also page 86-87).
As per claim 4, the combination of Xilinx and Xu disclose the system of claim 1.
Xilinx further disclose wherein the Ethernet port is configured to receive the programming/configuration information for the system via an Advanced eXtensible Interface slave port or embedded direct memory access (DMA) (see Fig. 1-1, page 27, the Ethernet port is configured to receive the programming and configuration information for the system via an Advanced eXtensible Interface (AXI) slave port, see data flow, master to slave).
As per claim 5, the combination of Xilinx and Xu disclose the system of claim 1.
Xilinx further disclose wherein the local memory controller is a multi-port memory controller configured to access a static random access memory/frame buffer in the local memory (see Fig.1-1, Fig.15-2, page 27, 394, a multi-port memory controller configured to access a static random access memory/frame buffer in the local memory).
As per claim 7, the combination of Xilinx and Xu disclose the system of claim 1.
Xilinx further disclose the system further comprising a forwarding database configured to cooperate with the Ethernet port in receiving configuration and management instructions (see Fig.1-1, page 479-480, AHB interfacing with DMA controller/ a forwarding database, FIFO, the port receiving programming and configuration information); and
Xu further disclose the system further comprising a forwarding database configured to cooperate with the SW Ethernet port in receiving configuration and management instructions (see Fig. 2A-B, para. 0019, 0020, a port profile manager 56 / a forwarding database is provisioned for managing port profiles, where each port profile is configured for application to one or more network interfaces associated with providing virtual machines 50 network capability, virtual switch 52 and/or VSM 54 defines each port profile).
Motivation same as claim 1.
As per claim 8, the combination of Xilinx and Xu disclose the system of claim 7.
Xilinx further disclose wherein the forwarding database is configured to be selectively bypassed for frames coming from host/virtual machine ports (see page 61, transactions to bypass for frames coming from host/virtual machine ports).
As per claim 9, the combination of Xilinx and Xu disclose the system of claim 8.
Xilinx further disclose wherein the forwarding database is configured to be selectively bypassed via a software-configurable destination port (see page 61, transactions to bypass virtual machine ports / SW ports).
As per claim 10, the combination of Xilinx and Xu disclose the system of claim 1.
Xilinx further disclose wherein at least some of the queue handlers comprise: a write subsection supporting concurrent incoming frames received from MAC/VM ports in the system (see page 85, 89, a write subsection for incoming frames received from MAC/VM ports in the system); and/or a read subsection implementing quality-of-service priorities for outgoing frames to MAC ports in the system (see page 32, 33, read section/read support to implement quality-of-service priorities for outgoing frames to MAC ports in the system).
As per claim 12, the combination of Xilinx and Xu disclose the system of claim 1.
Xilinx further disclose the system comprising functional safety mechanisms including a fault collector feature (see page 78, 82, a fault entry/collector) and a debug feature (see page 90, 108, 109, debug logic/feature).
As per claim 14, XILINX disclose A vehicle (see section 1.1, page 26, an automotive / a vehicle), comprising:
an on-board communication network (see Fig.1-1, page 27, 28, 479, Zynq-7000 AP SoC with Gigabit Ethernet Controller (GEM) / an on-board communication network), wherein the network comprises a system configured to provide media access control (MAC)/router/switch/gateway features for the on-board communication network (see Fig.1-1, page 27, 28, 479, the Gigabit Ethernet Controller (GEM) implements a 10/100/1000 Mb/s Ethernet MAC), the system comprising:
MAC controllers (see Fig.1-1, GigE/GEM/MAC controllers, I/O peripherals) configured to provide a MAC port layer controlling exchange of information over a data link (see page 479, section 16.1, the registers are used to configure the features of the MAC port layer controlling exchange of information over a data link interfaces);
virtual machine (VM) bridge blocks (see Fig.1-1, USB/CAN) configured to provide a MAC frame layer interfacing with System-on-Chip VMs (see page 27, 49-50, USB/CAN provides a MAC frame layer interfacing with Central Interconnect VMs / SoCs whose software is organized in VMs);
a Ethernet port (see Fig.1-1, High-Performance Ethernet port) configured to receive, from a host (see Fig.1-1, USB host controller), programming/configuration information for the system (see Fig.1-1, page 479-480, the port receiving programming and configuration information);
a local memory controller (see Fig. 1-1, Memory Interfaces and DDR2/3 Controller), configured to facilitate the MAC controllers, the VM bridge blocks and the SW Ethernet port in cooperating with a local memory (see Fig. 1-1, the MAC controllers, the VM bridge blocks and the SW Ethernet port in connecting/interfacing with L2 Cache and controller/a local memory); and
queue handlers (see Fig.1-1, Fig. 10-4, DDRC queue handlers) configured to provide queue management for the MAC controllers, the VM bridge blocks and the SW Ethernet port during cooperation of the MAC controllers, the VM bridge blocks and the SW Ethernet port with the local memory via the local memory controller (see page 299, section 10.3., para. 1, the DDRC is comprised of queues for pending read and write transactions and a scheduler that pops off the queues / queue management and sends the next transaction to the DDR PHY, between the DDRI and the DDRC, there is arbitration logic to decide which transaction is sent to the DDRC next / cooperation/ scheduling interface of MAC, VM, port and memory).
Although XILINX disclose a Ethernet port configured to receive, from a host programming/configuration information for the system;
XILINX however does not explicitly disclose “a software (SW) Ethernet port” configured to receive, from a host, programming/configuration information for the system;
Xu however does not explicitly disclose a software (SW) Ethernet port (see Fig.1, para. 0014, Fig.2A-2B, Virtual network interface cards 52a, 52b, 52c, 52d are mapped to a physical port, such as an Ethernet port, associated with host 14(1) / a software (SW) Ethernet port) configured to receive, from a host (see Fig.2A-B, host 14(1)), programming/configuration information for the system (see para. 0019, 0020, host 14(1), virtual switch 52, and/or VSM 54 maps a port profile to each physical network interface / receiving programming/configuration information for the system, see also para. 0021, an operating system 95, portions of which is resident in memory 85 and executed by the processor 80, functionally organize host 14(1), invoking network operations in support of software processes and/or services executing on the device);
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the functionality of a software (SW) Ethernet port configured to receive, from a host, programming/configuration information for the system, as taught by Xu, in the system of Xilinx, so as to automatically detect and configure server uplink network interfaces in a network environment and protects the applications and services against disruptions, see Xu, paragraphs 0003, 0009.
As per claim 15, XILINX disclose A networking (see Fig. 1-1, page 27, Zynq-7000 AP SoC) method, comprising:
controlling exchange of information over a data link via a media access control (MAC) port layer comprising MAC controllers (see Fig.1-1, GigE/GEM/MAC controllers, I/O peripherals, see page 479, section 16.1, the registers are used to configure the features of the MAC port layer controlling exchange of information over a data link interfaces);
providing a MAC frame layer interfacing with System-on-Chip virtual machines (VMs) via VM bridge blocks (see Fig.1-1, USB/CAN, see page 27, 49-50, USB/CAN provides a MAC frame layer interfacing with Central Interconnect VMs / SoCs whose software is organized in VMs);
receiving programming/configuration information via a Ethernet port (see Fig.1-1, High-Performance Ethernet port, page 479-480, the port receiving programming and configuration information);
facilitating cooperation with a local memory of the MAC controllers, the VM bridge blocks and the SW Ethernet port via a local memory controller (see Fig. 1-1, Memory Interfaces and DDR2/3 Controller, see page 27, the MAC controllers, the VM bridge blocks and the SW Ethernet port in connecting/interfacing with L2 Cache and controller/a local memory); and
providing queue management for the MAC controllers, the VM bridge blocks and the SW Ethernet port, during cooperation of the MAC controllers, the VM bridge blocks and the SW Ethernet port with the local memory via the local memory controller (see Fig.1-1, Fig. 10-4, DDRC queue handlers, see page 299, section 10.3., para. 1, the DDRC is comprised of queues for pending read and write transactions and a scheduler that pops off the queues / queue management and sends the next transaction to the DDR PHY, between the DDRI and the DDRC, there is arbitration logic to decide which transaction is sent to the DDRC next / cooperation/ scheduling interface of MAC, VM, port and memory).
Although XILINX disclose receiving programming/configuration information via a Ethernet port;
XILINX however does not explicitly disclose receiving programming/configuration information via “a software (SW) Ethernet port”;
Xu however does not explicitly disclose a software (SW) Ethernet port (see Fig.1, para. 0014, Fig.2A-2B, Virtual network interface cards 52a, 52b, 52c, 52d are mapped to a physical port, such as an Ethernet port, associated with host 14(1) / a software (SW) Ethernet port) receiving programming/configuration information via “a software (SW) Ethernet port” (see Fig.2A-B, host 14(1)), programming/configuration information for the system (see para. 0019, 0020, host 14(1), virtual switch 52, and/or VSM 54 maps a port profile to each physical network interface / receiving programming/configuration information for the system, see also para. 0021, an operating system 95, portions of which is resident in memory 85 and executed by the processor 80, functionally organize host 14(1), invoking network operations in support of software processes and/or services executing on the device);
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the functionality of receiving programming/configuration information via “a software (SW) Ethernet port”, as taught by Xu, in the system of Xilinx, so as to automatically detect and configure server uplink network interfaces in a network environment and protects the applications and services against disruptions, see Xu, paragraphs 0003, 0009.
As per claim 16, claim 16 is rejected the same way as claim 4.
As per claim 17, claim 17 is rejected the same way as claim 5.
As per claim 19, claim 19 is rejected the same way as claim 7.
Allowable Subject Matter
Claims 6, 11, 13, 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lovett (US Pub. No.:2013/0107872) – see para. 0197, “Enterprise Manager 530 supports multi-chassis management, complex provisioning, interfaces to client GUIs, and generally operates at a relatively high level of abstraction, as does CLI 532. Platform Manager 531 generally performs in-chassis (or single-chassis) management operations and tends to manipulate system objects directly at a relatively low level of abstraction. Several SW modules operate in close cooperation with the Platform Manager, including Chassis Manager (CM) 533, Query Engine 534, Repository Manager 535, VIOC Manager 536, Interface Manager 537, L2 Forwarding DataBase (FDB) Manager 538, VLAN Manager 539, and Other Management Code 540”.
Beecroft (US Pub. No.:2016/0337146) – see para. 0031, “ … an Ethernet bridge or router comprising a network fabric adapted to provide interconnectivity to a plurality of Ethernet ports, each of the Ethernet ports being adapted to receive and/or transmit Ethernet frames, and wherein the Ethernet bridge or router further comprises software instructions for operating an encapsulator to generate a Fabric Protocol Data Unit from a received Ethernet Protocol Data Unit, the Fabric Protocol Data Unit comprising a header portion, and a payload portion which comprises the Ethernet Protocol Data Unit concerned, and wherein the encapsulator is operable to transform Ethernet destination address information from the Ethernet Protocol Data Unit into a routing definition for the network fabric, and to include this routing definition in the header portion of the Fabric Protocol Data Unit”.
Rumyankov (US Pub. No.:2018/0359181) – see para. 0002, “The present technology relates to the data transmission technology in packet-switched Software Defined Networks (SDN), comprising switches with Ethernet ports and controlled by software controllers”.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAKERAM JANGBAHADUR whose telephone number is (571)272-1335. The examiner can normally be reached on M-F 7 am - 4 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ian Moore can be reached on 571-272-3085. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAKERAM JANGBAHADUR/
Primary Examiner, Art Unit 2469
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