DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s arguments filed on 12/16/25.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-2, 6-8, 12-15 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Fan et al. (“Fan”, US Pat 7973521), in view of Kwong (US Pat 7619402).
Regarding independent claim 1, Fan teaches (Fig. 3-4, 6) an apparatus, comprising:
a voltage regulator circuit (voltage regulator circuit (VDC): LDO target circuit 8) configured to generate a particular voltage level (VF) on a regulated power supply node (power supply node being a node, where VF is supplied to power or sourcing load T, via R0; wherein VF is also provided to source a current back to LDO 8, using LDO 8’s Transistor on operation, which is based on compared signal of Vref & VF in LDO 8); and
a pull-down circuit (pull-down circuit (PDC): trimmer circuit 2, except for LDO 8) configured (when LDO’s 8’s transistor=off, to discharge or pull-down leakage current of VF to ground, taught PDC is initiated (includes: counter 14, periodic pulse generator/controller 13, logics ‘11-12, 15’, test signal Vt and comparator 10), to vary two or more variable resistance circuits, using switch circuit 2 (formed using 1st (M1-M3) & 2nd (M4-6) NMOS transistors) and associated resistors connection and its corresponding resistance value.),
in response to a deactivation of the voltage regulator circuit (when LDO’s transistor=off), to:
activate, for a particular time period (selective and periodical switching operation of each switch M1-6; col. 4 L29-col. 6 L21), a first transistor (i.e., when any one of M1 vs. M4 being on, which are part of switching circuit 2, which includes switches M1-6. Depending on combined operation of ‘10-15’ output(s), such as binary outputs, ranging between 000 to 111, to selectively switching each M1-6, between on/off, periodically (in another word, for a particular time period). See, col. 4 L29-col. 6 L21. Fan also teaches having each M1-6, coupled between VF (via R0) and ground; wherein each M1-6 directly or indirectly connects resistors R1-3. See, col. 4 L29-65.)
coupled between (Since, Applicant never claims any specific node or end of 1st/2nd transistor’s direct connection to either a regulated power supply node or respective 1st/2nd resistor. Therefore, under BRI, Fan teaches 2’s included plural switches M1-6, wherein each switch directly or indirectly connects between taught regulated power supply node and respective 1st/2nd resistors, as claimed.)
the regulated power supply node (power supply node being a node, where VF is supplied to power load T, via R0)
a first resistor (i.e., 1st-3rd or nth resistor(s) is when any one of corresponding R1-3 being operational, using 2’s switches. For example, 1st resistor may be when R1 being operational, 2nd resistor may be when R2 being operational &/or 3rd resistor may be when R3 being operational.)
that is further coupled to a ground supply node (GND); and
in response to a determination that the particular time period has elapsed (selective and periodical switching operation of each switch M1-6; col. 4 L29-col. 6 L21):
deactivate the first transistor (i.e., when M1 and M4 both off); and
activate a second transistor (i.e., when any one of M2 vs. M5 being on, which are part of switching circuit 2, which includes switches M1-6. Depending on combined operation of ‘10-15’ output(s), such as binary outputs, ranging between 000 to 111, to selectively switching each M1-6, between on/off, periodically (in another word, for a particular time period). See, col. 4 L29-col. 6 L21. Fan also teaches having each M1-6, coupled between VF (via R0) and ground; wherein each M1-6 directly or indirectly connects resistors R1-3. See, col. 4 L29-65.)
coupled between (Since, Applicant never claims any specific node or end of 1st/2nd transistor’s direct connection to either a regulated power supply node or respective 1st/2nd resistor. Therefore, under BRI, Fan teaches 2’s included plural switches M1-6, wherein each switch directly or indirectly connects between taught regulated power supply node and respective 1st/2nd resistors, as claimed.)
the regulated power supply node (power supply node being a node, where VF is supplied to power load T, via R0) and
a second resistor (i.e., 1st-3rd or nth resistor(s) is when any one of corresponding R1-3 being operational, using 2’s switches. For example, 1st resistor may be when R1 being operational, 2nd resistor may be when R2 being operational &/or 3rd resistor may be when R3 being operational.)
that is further coupled to the ground supply node (GND),
wherein a first value of the first resistor (i.e., 1st-3rd or nth resistor(s) is when any one of corresponding R1-3 being operational, using 2’s switches. For example, 1st resistor may be when R1 being operational, 2nd resistor may be when R2 being operational &/or 3rd resistor may be when R3 being operational. See, col. 1 L42-col. 2 L12) … a second value of the second resistor (i.e., 1st-3rd or nth resistor(s) is when any one of corresponding R1-3 being operational, using 2’s switches. For example, 1st resistor may be when R1 being operational, 2nd resistor may be when R2 being operational &/or 3rd resistor may be when R3 being operational. See, col. 1 L42-col. 2 L12).
However, Fan fails to teach a first value of the first resistor is less than a second value of the second resistor (in another word this conditional relationship is same as, having the second resistor’s 2nd resistance value being greater than the first resistor’s 1st resistance value, as claimed in claim 7).
However, Kwong teaches (Fig. 1-3, 5; col. 2 L26-col. 4 L10) a first value of the first resistor is less than a second value of the second resistor (Abstract: using programmable-decoded configuration to generate control bits that turn on select transistors that control a variable resistor network; wherein the network has selected transistors that select one resistor between the regulated voltage and an upper node, and that select one resistor between a lower node and ground. Therefore, in another word this conditional relationship is same as, having the second resistor’s 2nd resistance value being greater than the first resistor’s 1st resistance value, as claimed in claim 7).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fan’s apparatus to use the technique of one/first resistor’s value being more or less than another/second resistor’s value, using switching operation, as doing so would have provided an improved trimming resistor capability with decreased manufacturing costs, while maintaining safe, steady operation and thus meeting various larger load SoC (System-on-Chip) requirements (col. 1 L13-58).
Regarding independent claim 7, Fan teaches (Fig. 3-4, 6) a method, comprising:
sourcing a current to a regulated power supply node (power supply node being a node, where VF is supplied to power or sourcing load T, via R0; wherein VF is also provided to source a current back to LDO 8, using LDO 8’s Transistor on operation, which is based on compared signal of Vref & VF in LDO 8) in response to activating (when LDO’s transistor=on) a voltage regulator circuit (voltage regulator circuit (VDC): LDO target circuit 8);
in response to deactivating the voltage regulator circuit (when LDO’s transistor=off):
halting the sourcing of current to the regulated power supply node (power supply node being a node, where VF is halted to supply power or sourcing load T, via R0; wherein VF is also may halted to provide or to source a current back to LDO 8, using LDO 8’s Transistor on operation, which is based on compared signal of Vref & VF in LDO 8); and
discharging the regulated power supply node to a ground supply node (i.e., VF being pulled to ground, using pull-down circuit (PDC): trimmer circuit 2, except for LDO 8)
by activating (selective and periodical switching operation of each switch M1-6; col. 4 L29-col. 6 L21), a first transistor (i.e., when any one of M1 vs. M4 being on, which are part of switching circuit 2, which includes switches M1-6. Depending on combined operation of ‘10-15’ output(s), such as binary outputs, ranging between 000 to 111, to selectively switching each M1-6, between on/off, periodically (in another word, for a particular time period). See, col. 4 L29-col. 6 L21. Fan also teaches having each M1-6, coupled between VF (via R0) and ground; wherein each M1-6 directly or indirectly connects resistors R1-3. See, col. 4 L29-65.)
coupled between (Since, Applicant never claims any specific node or end of 1st/2nd transistor’s direct connection to either a regulated power supply node or respective 1st/2nd resistor. Therefore, under BRI, Fan teaches 2’s included plural switches M1-6, wherein each switch directly or indirectly connects between taught regulated power supply node and respective 1st/2nd resistors, as claimed.)
the regulated power supply node (power supply node being a node, where VF is supplied to power load T, via R0) and
a first resistor (i.e., 1st-3rd or nth resistor(s) is when any one of corresponding R1-3 being operational, using 2’s switches. For example, 1st resistor may be when R1 being operational, 2nd resistor may be when R2 being operational &/or 3rd resistor may be when R3 being operational.)
that is further coupled to the ground supply node (gnd); and
in response to determining that
a particular period of time has elapsed (selective and periodical switching operation of each switch M1-6; col. 4 L29-col. 6 L21)
since deactivating the voltage regulator circuit (i.e., when LDO’s transistor=off and both M1 and M4 being both off);
activating a second transistor (i.e., when any one of M2 vs. M5 being on, which are part of switching circuit 2, which includes switches M1-6. Depending on combined operation of ‘10-15’ output(s), such as binary outputs, ranging between 000 to 111, to selectively switching each M1-6, between on/off, periodically (in another word, for a particular time period). See, col. 4 L29-col. 6 L21. Fan also teaches having each M1-6, coupled between VF (via R0) and ground; wherein each M1-6 directly or indirectly connects resistors R1-3. See, col. 4 L29-65.)
coupled between (Since, Applicant never claims any specific node or end of 1st/2nd transistor’s direct connection to either a regulated power supply node or respective 1st/2nd resistor. Therefore, under BRI, Fan teaches 2’s included plural switches M1-6, wherein each switch directly or indirectly connects between taught regulated power supply node and respective 1st/2nd resistors, as claimed.)
the regulated power supply node (power supply node being a node, where VF is supplied to power load T, via R0) and
a second resistor (i.e., 1st-3rd or nth resistor(s) is when any one of corresponding R1-3 being operational, using 2’s switches. For example, 1st resistor may be when R1 being operational, 2nd resistor may be when R2 being operational &/or 3rd resistor may be when R3 being operational.)
that is further coupled to the ground supply node (GND),
wherein a second value of the second resistor (i.e., 1st-3rd or nth resistor(s) is when any one of corresponding R1-3 being operational, using 2’s switches. For example, 1st resistor may be when R1 being operational, 2nd resistor may be when R2 being operational &/or 3rd resistor may be when R3 being operational. See, col. 1 L42-col. 2 L12) … a first value of the first resistor (i.e., 1st-3rd or nth resistor(s) is when any one of corresponding R1-3 being operational, using 2’s switches. For example, 1st resistor may be when R1 being operational, 2nd resistor may be when R2 being operational &/or 3rd resistor may be when R3 being operational. See, col. 1 L42-col. 2 L12).
However, Fan fails to teach a second value of the second resistor is greater than a first value of the first resistor (this limitation is same as claim 14, which in another word can be interpreted as same conditional relationship, having the first resistor’s 1st resistance value being less than the second resistor’s 2nd resistance, as claimed in claim 1).
However, Kwong teaches (Fig. 1-3, 5; col. 2 L26-col. 4 L10) a second value of the second resistor is greater than a first value of the first resistor (Abstract: using programmable-decoded configuration to generate control bits, that turn on select transistors that control a variable resistor network; wherein the network has selected transistors that select one resistor between the regulated voltage and an upper node, and that select one resistor between a lower node and ground. Therefore, in another word this conditional relationship is same as, having the first resistor’s 1st resistance value being less than the second resistor’s 2nd resistance, as claimed in claim 1).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fan’s apparatus to use the technique of one/first resistor’s value being more or less than another/second resistor’s value, using switching operation, as doing so would have provided an improved trimming resistor capability with decreased manufacturing costs, while maintaining safe, steady operation and thus meeting various larger load SoC (System-on-Chip) requirements (col. 1 L13-58).
Regarding independent claim 14, Fan teaches (Fig. 3-4, 6) a system, comprising:
a load circuit (load T) coupled to a regulated power supply node (power supply node being a node, where VF is supplied or halted to power or sourcing load T, via R0; wherein VF is also provided to source or halt a current back to LDO 8, using LDO 8’s Transistor on operation, which is based on compared signal of Vref & VF in LDO 8); and
a power circuit (trimmer circuit 1) configured to:
source a current to the regulated power supply node (power supply node being a node, where VF is supplied to power or sourcing load T, via R0; wherein VF is also provided to source a current back to LDO 8, using LDO 8’s Transistor on operation, which is based on compared signal of Vref & VF in LDO 8) in response to an activation (i.e., when LDO 8’s transistor being on) of a power control signal (a power control signal being comparison output that driving gate of LDO 8’S transistor to be on or off);
in response to a deactivation of the power control signal (when LDO’s transistor=off):
halt sourcing the current to the regulated power supply node (power supply node being a node, where VF is halted to supply power or sourcing load T, via R0; wherein VF is also may halted to provide or to source a current back to LDO 8, using LDO 8’s Transistor on operation, which is based on compared signal of Vref & VF in LDO 8); and
discharge the regulated power supply node to a ground supply node (i.e., VF being pulled to ground, using pull-down circuit (PDC): trimmer circuit 2, except for LDO 8)
by activating (selective and periodical switching operation of each switch M1-6; col. 4 L29-col. 6 L21) a first transistor (i.e., when any one of M1 vs. M4 being on, which are part of switching circuit 2, which includes switches M1-6. Depending on combined operation of ‘10-15’ output(s), such as binary outputs, ranging between 000 to 111, to selectively switching each M1-6, between on/off, periodically (in another word, for a particular time period). See, col. 4 L29-col. 6 L21. Fan also teaches having each M1-6, coupled between VF (via R0) and ground; wherein each M1-6 directly or indirectly connects resistors R1-3. See, col. 4 L29-65.)
coupled between (Since, Applicant never claims any specific node or end of 1st/2nd transistor’s direct connection to either a regulated power supply node or respective 1st/2nd resistor. Therefore, under BRI, Fan teaches 2’s included plural switches M1-6, wherein each switch directly or indirectly connects between taught regulated power supply node and respective 1st/2nd resistors, as claimed.)
the regulated power supply node (power supply node being a node, where VF is supplied to power load T, via R0) and
a first resistor (i.e., 1st-3rd or nth resistor(s) is when any one of corresponding R1-3 being operational, using 2’s switches. For example, 1st resistor may be when R1 being operational, 2nd resistor may be when R2 being operational &/or 3rd resistor may be when R3 being operational.)
that is further coupled to the ground supply node (gnd); and
in response to a determination that a particular period of time has elapsed (selective and periodical switching operation of each switch M1-6; col. 4 L29-col. 6 L21) since the power control signal was deactivated (i.e., when LDO’s transistor=off and both M1 and M4 being both off),
activate a second transistor (i.e., when any one of M2 vs. M5 being on, which are part of switching circuit 2, which includes switches M1-6. Depending on combined operation of ‘10-15’ output(s), such as binary outputs, ranging between 000 to 111, to selectively switching each M1-6, between on/off, periodically (in another word, for a particular time period). See, col. 4 L29-col. 6 L21. Fan also teaches having each M1-6, coupled between VF (via R0) and ground; wherein each M1-6 directly or indirectly connects resistors R1-3. See, col. 4 L29-65.)
coupled between (Since, Applicant never claims any specific node or end of 1st/2nd transistor’s direct connection to either a regulated power supply node or respective 1st/2nd resistor. Therefore, under BRI, Fan teaches 2’s included plural switches M1-6, wherein each switch directly or indirectly connects between taught regulated power supply node and respective 1st/2nd resistors, as claimed.)
the regulated power supply node (power supply node being a node, where VF is supplied to power load T, via R0) and
a second resistor (i.e., 1st-3rd or nth resistor(s) is when any one of corresponding R1-3 being operational, using 2’s switches. For example, 1st resistor may be when R1 being operational, 2nd resistor may be when R2 being operational &/or 3rd resistor may be when R3 being operational.)
that is further coupled to the ground supply node (gnd),
wherein a second value of the second resistor (i.e., 1st-3rd or nth resistor(s) is when any one of corresponding R1-3 being operational, using 2’s switches. For example, 1st resistor may be when R1 being operational, 2nd resistor may be when R2 being operational &/or 3rd resistor may be when R3 being operational. See, col. 1 L42-col. 2 L12) … a first value of the first resistor (i.e., 1st-3rd or nth resistor(s) is when any one of corresponding R1-3 being operational, using 2’s switches. For example, 1st resistor may be when R1 being operational, 2nd resistor may be when R2 being operational &/or 3rd resistor may be when R3 being operational. See, col. 1 L42-col. 2 L12).
However, Fan fails to teach a second value of the second resistor is greater than a first value of the first resistor (this limitation is same as claim 7, which in another word can be interpreted as same conditional relationship, having the first resistor’s 1st resistance value being less than the second resistor’s 2nd resistance, as claimed in claim 1).
However, Kwong teaches (Fig. 1-3, 5; col. 2 L26-col. 4 L10) a second value of the second resistor is greater than a first value of the first resistor (Abstract: using programmable-decoded configuration to generate control bits that turn on select transistors that control a variable resistor network; wherein the network has selected transistors that select one resistor between the regulated voltage and an upper node, and that select one resistor between a lower node and ground. Therefore, in another word this conditional relationship is same as, having the first resistor’s 1st resistance value being less than the second resistor’s 2nd resistance, as claimed in claim 1).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fan’s apparatus to use the technique of one/first resistor’s value being more or less than another/second resistor’s value, using switching operation, as doing so would have provided an improved trimming resistor capability with decreased manufacturing costs, while maintaining safe, steady operation and thus meeting various larger load SoC (System-on-Chip) requirements (col. 1 L13-58).
Regarding claims 2, 8 and 15, Fan teaches (Fig. 3-4, 6) the pull-down circuit (PDC) is further configured to adjust, using a plurality of control signals (i.e., 14 vs. 15’s operational output controlling each switch M1-6), the first value of the first resistor (i.e., R1’s resistance value being adjusted using M1 vs. M4’s on/off operation) and the second value of the second resistor (i.e., R2 resistance being adjusted using M2 vs. M5’s on/off operation).
Regarding claims 6, 13, and 20, Fan teaches the voltage regulator circuit (LDO 8) includes: a control circuit (i.e., comparison means in LDO 8) configured to: perform a comparison of a reference voltage (Vref) to a voltage level of the regulated power supply node (power supply node being a node, where VF is supplied to power load T, via R0); and generate a control signal (output of comparison means in LDO that is used to drive gate of transistor in LDO 8) based on a result of the comparison; and a fourth transistor (transistor in LDO 8) coupled between an input power supply node (Vin) and the regulated power supply node(power supply node being a node, where VF is supplied to power load T, via R0), wherein the fourth transistor (transistor in LDO 8) is configured to adjust a conductance between the input power supply node (Vin) and the regulated power supply node (transistor in LDO 8) using the control signal (output of comparison means in LDO that is used to drive gate of transistor in LDO 8).
Regarding claims 12, 19, Fan teaches adjusting the second value of the second resistor, except that it is done so based on temperature.
However, Kwong teaches (Fig. 1-3, 5; col. 2 L26-col. 4 L10) adjusting the second value of the second resistor, based on temperature (col. 2 L42-45. Also see, abstract: using programmable-decoded configuration to generate control bits that turn on select transistors that control a variable resistor network; wherein the network has selected transistors that select one resistor between the regulated voltage and an upper node, and that select one resistor between a lower node and ground. Therefore, in another word this conditional relationship is same as, having the first resistor’s 1st resistance value being less than the second resistor’s 2nd resistance, as claimed in claim 1).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fan’s apparatus to use the technique of one/first resistor’s value being more or less than another/second resistor’s value, based on temperature being a parameter, using switching operation, as doing so would have provided an improved trimming resistor capability with decreased manufacturing costs, while maintaining safe, steady operation and thus meeting various larger load SoC (System-on-Chip) requirements (col. 1 L13-58).
Allowable Subject Matter
Claims 3-5, 9-11, 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 3, 9 and 16, cited art(s) failed to teach,
“the pull-down circuit includes: a decoder circuit configured to decode the plurality of control signals to generate a plurality of decoded signals” and “a third transistor” configured to couple the regulated power supply node to the ground supply node “in response to an activation of a corresponding one of the plurality of decoded signals”, as claimed in claim 3; similarly
“decoding the plurality of control signals to generate a plurality of decoded signals” and “activating at least one of a plurality of transistors” coupled to the regulated power supply node “in response to activating a corresponding one of the plurality of decoded signals”, as claimed in claim 9; and similarly again
“ decode the plurality of control signals to generate a plurality of decoded signals” and “activate at least one of a plurality of transistors” coupled to the regulated power supply node “in response to an activation of a corresponding one of the plurality of decoded signals”, as claimed in claim 16.
Regarding claims 4, 10, 17, Fan teaches (Fig. 3-4, 6) the pull-down circuit (PDC) includes:
a counter circuit (14-15) configured, in response to the deactivation of the voltage regulator circuit (when LDO’s transistor=off), to initiate a periodic incrementing of a count value (Depending on combined operation of ‘10-15’ output(s), such as binary outputs using 14-15, ranging between 000 to 111, to selectively switching each M1-6, between on/off, periodically (in another word, for a particular time period); and
a control circuit (10-13, VT) configured to activate an enable signal (i.e., test signal VT to trigger 13 to enable and may also enable to reset counter 14) in response to a determination that the particular voltage level (VF) exceeds a threshold value (VT); and
wherein the pull-down circuit (PDC) is further configured, in response to an activation of the enable signal (i.e., test signal VT to trigger 13 to enable and may also enable to reset counter 14), to: deactivate the first transistor (i.e., when M1 and M4 both off); and activate the second transistor (i.e., when any one of M2 vs. M5 being on, which are part of switching circuit 2, which includes switches M1-6. Depending on combined operation of ‘10-15’ output(s), such as binary outputs, ranging between 000 to 111, to selectively switching each M1-6, between on/off, periodically (in another word, for a particular time period). See, col. 4 L29-col. 6 L21. Fan also teaches having each M1-6, coupled between VF (via R0) and ground; wherein each M1-6 directly or indirectly connects resistors R1-3. See, col. 4 L29-65.).
However, Fan fails to teach
“a control circuit configured to activate an enable signal in response to a determination that the count value (i.e., by a counter circuit configured, in response to the deactivation of the voltage regulator circuit, to initiate a periodic incrementing of a count value) exceeds a threshold value; and wherein the pull-down circuit is further configured, in response to an activation of the enable signal, to: deactivate the first transistor; and activate the second transistor”, as claimed in claim 4; similarly
“activating an enable signal in response to determining that the count value (i.e., by a counter circuit which is in response to deactivating the voltage regulator circuit, incrementing a count value at periodic intervals) exceeds a threshold value”, as claimed in claim 10; and similarly again
“activate an enable signal in response to a determination that the count value (i.e., by a counter circuit which is in response to deactivation of the power control signal, increment a count value at periodic intervals) exceeds a threshold value”, as claimed in claim 17.
Claims ‘5’, ‘11’ and ‘18’are depending from claims 4, 10 and 17, respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Regarding independent claim 1, Chen et al. (“Chen”, US Pat 7973521) teaches (any one of Fig. 1-3; col. 2 L34-col. 4 L12) an apparatus, comprising:
a voltage regulator circuit (LDO 10, 20) configured to generate a particular voltage level on a regulated power supply node (Vout on terminal 15 at a node between 20 & R1. Vout is provided to source an output to a load. LDO’s transistor 20 is driven based on diff. amp. 10’s output, by comparing signal of Vref & Vfb); and
a pull-down circuit configured (pull down circuit being combined operation of 30, associated resistor (i.e., R3, R1a) and 40. When LDO=off, by 30’s output S2, discharging or pull-down leakage current of 15 to ground by initiating a pull-down operation),
in response to a deactivation of the voltage regulator circuit (when LDO=off, using 30’s S2 output), to:
activate (40=on), for a particular time period, a first transistor (i.e., 40) coupled between the regulated power supply node (Vout on terminal 15 at a node between 20 & R1) and a first resistor (i.e., R2) that is further coupled to a ground supply node (GND); and
in response to a determination that the particular time period has elapsed (i.e., dependent on the period corresponding to shut-down mode);
deactivate the first transistor (i.e., 40=off); and
…the regulated power supply node (Vout on terminal 15 at a node between 20 & R1) and a second resistor (R1) that is further … the ground supply node (GND), wherein a first value of the first resistor (R2’s resistance value) … a second value of the second resistor (R1’s resistance value).
However, Chen fails to teach a pull-down circuit is configured to, after deactivating the first transistor, activating a second transistor coupled between the regulated power supply node and a second resistor that is further coupled to the ground supply node, wherein a first value of the first resistor is less than a second value of the second resistor.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NUSRAT QUDDUS/Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838