Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
1. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
2. Claims 7 -10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
In claim 7, it is not clear how the terms “S11”, “S12”, “S13”, “S14” and “S1” (the term S1 is not found in any other claim and therefore it would also create an antecedent basis issue if left in the claim) or the phrase “in the step” are used or what they refer too in the limitations: “S11, forming … bit lines; S12, growing a …in the step S1; S13, growing … in the step S12, and…at intervals; and S14, growing metal at a same end of each of the bit line on the metal structure obtained in the step S13 to form the contact electrodes of the bit lines”. The inclusion of said terms make the claim indefinite and should be removed from the claim limitations. The prior art consideration sections below will apply broadest reasonable interpretation possible. Claims 10 is dependent on claim 7 and inherits the same deficiencies.
3. In claim 8, it is not clear how the terms “S21”, “S22”, “S23”, “S24” and “S3” (the term S3 is not found in any other claim and therefore it would also create an antecedent basis issue if left in the claim) or the phrase “in the step” are used or what they refer too in the limitations: “S21, growing an n-type … bit lines; S22, growing a … in the step S21; S23, growing a … in the step S22, and etching the metal structure to form word lines arranged at intervals; and S24, growing … the step S3 to form the contact electrodes of the bit lines.”. The inclusion of said terms make the claim indefinite and should be removed from the claim limitations. The prior art consideration sections below will apply broadest reasonable interpretation possible.
4. In claim 9, it is not clear how the terms “S31”, “S32”, “S33”, “S34” and “S35” are used or what they refer too in the limitations: “S31, growing a stress … equal to 2; S32, selectively … obtained in S31 and filling in an isolation layer; S33, selectively etching … obtained in S32; S34, growing a … a structure obtained in S33; S35, selectively etching …. obtained in S34, growing a metal structure to form a word line, and growing metal at a same end of each of the bit lines to form the contact electrodes of the bit lines”. The inclusion of said terms make the claim indefinite and should be removed from the claim limitations. The prior art consideration sections below will apply broadest reasonable interpretation possible.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claim(s) 1, 2, 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sills US Patent Application (20140138608), hereinafter “Sills” and Takashima et al., US Patent Application (20130329485), hereinafter “Takashima”.
Regarding claim 1 Sills teaches a diode device with programmable conducting current, The access device can be a diode … the memory cell having a resistance that is programmable to particular levels corresponding to particular data states responsive to applied programming voltage and/or current pulses, for instance. [Sills para 0017] wherein the device comprises: a metal structure, a resistance variable structure, a variable resistance storage element material … the materials may include at least one of a metal ion source layer [Sills para 0017] with a resistance capable of being adjusted, resistance variable materials that can be used to form storage elements include binary metal oxide materials [Sills para 0017] so as to achieve programmable conducting current, the memory cells of array 100 can be programmed by applying a voltage, e.g., a write voltage, across the memory cells via selected word lines 130-0, 130-1, . . . , 130-N and bit lines 120-0, 120-1, . . . , 120-M. The width and/or magnitude of the voltage pulses across the memory cells can be adjusted, e.g., varied, in order to program the memory cells to particular data states, e.g., by adjusting a resistance level of the storage element. [Sills para 0018] and a semiconductor structure comprising a semiconductor, The substrate material 201 can be a semiconductor material, [Sills para 0020]
Sills does not explicity teach but Takashima teaches wherein a state density function of the semiconductor comprises at least one peak, such that a state density near an energy level of the at least one peak is greater than a state density of an energy level of the semiconductor structure except the peak, In reset where transition from the low resistance state to the high resistance state occurs, a potential having a polarity opposite to that in the set is applied. More specifically, a negative potential is applied to the electrode layer 9, and a fixed potential (0 V) is applied to the electrode layer 11. An electric field whose polarity is opposite to that in the set is applied to the recording layer 10 to shorten the metal filament 12. The distance between the electrode layer 11 and the metal filament 12 increases, and the variable resistance element VR transits to the high resistance state (reset), as shown in FIG. 3A. N-type Si of the electrode layer 11 is depleted upon applying the negative potential to the electrode layer 9. Since the voltage applied to the variable resistance element VR is distributed to the depletion layer of the electrode layer (n-type Si) 11 and the recording layer 10, the voltage necessary for reset is large. FIG. 4 shows the current-voltage characteristic of the variable resistance element VR. This variable resistance element contains Ag in the electrode layer 9, amorphous silicon in the recording layer 10, and n-type Si in the electrode layer 11. Note that the ordinate adopts logarithmic notation. [Takashima para 0030 and 0031] (The peak is at transition or reset however the materials used deplete the energy allowing their levels to maintain a close to peak energy level between transition states.) wherein the metal structure, The electrode layer 9 contains at least one of metals such as Fe, Co, Ni, Cu, Ag, Au, Zn, and Al and silicides thereof. In this embodiment, for example, Ag is used in the electrode layer 9. [Takashima para 0028] the resistance variable structure The recording layer 10 contains one of, for example, amorphous silicon, polysilicon, and single-crystal silicon. In this embodiment, for example, amorphous silicon is used in the recording layer 10. [Takashima para 0028] and the semiconductor structure The electrode layer 11 contains an n-type semiconductor containing P or As, for example, n-type Si, n-type SiGe, or n-type Ge. In this embodiment, for example, n-type Si is used in the electrode layer 11. Electrodes (not shown) functioning as a barrier metal and an adhesive layer are arranged on the upper and lower sides of the variable resistance element VR so as to sandwich the variable resistance element VR [Takashima para 0028] are directly connected in turn. As shown in FIGS. 3A and 3B, the variable resistance element VR comprises electrode layers 9 and 11, and a recording layer (resistance change layer) 10 arranged between the electrode layers 9 and 11. [Takashima para 0028 and see Fig. 3A and 3B]
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Sills discloses memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode, a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode, and a storage element between the first electrode and the electrode contact portion of the second electrode. Sills further discloses the array of memory cells can be an array such as array which includes an electrode material formed one a substrate material. The substrate material can be a semiconductor material, for example silicon, among various other substrate materials. The electrode material can be a conductive material, such as copper and/or tungsten, among various other conductive materials. The electrode material can be a bottom electrode, e.g., a conductive line, for example, an access line such as word lines or a data line such as bit lines.
Takashima discloses a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.
Prior to the effective date of the invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Sills and Takashima in the art of memory cell structures and a method of forming the same. Takashima improves Sills’ systems, methods and/or apparatus by forming a memory structure with known materials for the metal layer, the variable resistance layer and the semiconductor layer to achieve memory cells which includes a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The reset operation is an operation of causing the memory cell to transit from a low resistance state to a high resistance state by applying a reset voltage between the first interconnection and the second interconnection.
Regarding claim 2 Sills and Takashima teach claim 1 in addition Takashima teaches wherein the metal structure comprises one or more metals, comprising TiN, Ni, W, Ti, Al, Pd, Pt, Au and Ru The electrode layer 9 contains at least one of metals such as Fe, Co, Ni, Cu, Ag, Au, Zn, and Al and silicides thereof. In this embodiment, for example, Ag is used in the electrode layer 9. [Takashima para 0028]; and the resistance variable structure is a unipolar resistance variable oxide layer, the variable resistance element VR. When performing verify using a reset voltage, … that is, a voltage having the same polarity as that of the set voltage [Takashima para 0043] and comprises one or more oxides, comprising TiO2, NiO, Ni2O3, Y203, HfO2, WO3, ZrO2 and Ta2OS. The recording layer 10 can also use HfOx, HfSiOx, MnOx, MnAlxOy, ZnMnOx, NiOx, TiOx, WOx, SiO.sub.2, SiN, or Si that are transition metal compounds. [Takashima para 0033]
Regarding claim 3 Sills and Takashima teach claim 1 in addition Takashima teaches wherein the resistance variable structure is capable of being switched from a low-resistance state to a high-resistance state, or from a high-resistance state to a low-resistance state, in a current conducting direction, by adjusting a voltage and a current limit applied to the metal structure. In reset where transition from the low resistance state to the high resistance state occurs, a potential having a polarity opposite to that in the set is applied. … Since the voltage applied to the variable resistance element VR is distributed to the depletion layer of the electrode layer (n-type Si) 11 and the recording layer 10, the voltage necessary for reset is large. FIG. 4 shows the current-voltage characteristic of the variable resistance element VR. This variable resistance element contains Ag in the electrode layer 9, amorphous silicon in the recording layer 10, and n-type Si in the electrode layer 11. Note that the ordinate adopts logarithmic notation. [Takashima para 0030 and 0031]
8. Claim(s) 4-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sills and Takashima and further in view of Hayakawa et al., US Patent Application (20120069632), hereinafter “Hayakawa”
Regarding claim 4 Sills and Takashima teach claim 1 in addition Sills and Takashima do not teach but Hayakawa teaches wherein semiconductor material of the semiconductor structure comprises Ge, SiGe, GaAs, GaN, SiC, Ga2O3, The electrode layer 11 contains an n-type semiconductor containing P or As, for example, n-type Si, n-type SiGe, or n-type Ge. In this embodiment, for example, n-type Si is used in the electrode layer 11. Electrodes (not shown) functioning as a barrier metal and an adhesive layer are arranged on the upper and lower sides of the variable resistance element VR so as to sandwich the variable resistance element VR [Takashima para 0028] and
Sills and Takashima do not explicitly teach but Hayakawa teaches the state density function comprises at least one peak located near a forbidden band. where the current steering layer 33 comprises SiN.sub.x, if a nitrogen composition in SiN.sub.x is varied, it is possible to continuously vary a forbidden band width. Therefore, by changing a value of x in SiN.sub.x, it is possible to control a size of the potential barriers between the first electrode 32 and the current steering layer 33 [Hayakawa para 0104] (The idea of a forbidden band is controlled by the composition of the structure. One of ordinary skill in the art could have designed a peak below the reset transition to be below an area in which electrons would not normally be present or move prior to an energy potential transition)
Sills discloses memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode, a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode, and a storage element between the first electrode and the electrode contact portion of the second electrode. Sills further discloses the array of memory cells can be an array such as array which includes an electrode material formed one a substrate material. The substrate material can be a semiconductor material, for example silicon, among various other substrate materials. The electrode material can be a conductive material, such as copper and/or tungsten, among various other conductive materials. The electrode material can be a bottom electrode, e.g., a conductive line, for example, an access line such as word lines or a data line such as bit lines.
Takashima discloses a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.
Hayakawa discloses a current steering element that can prevent write didturb even when an electrical pulse with different polarities is applied and that can cause a large current to flow through a variable resistance element. The current steering element includes a first electrode (32), a second electrode (31), and a current steering layer (33). The current steering layer (33) comprises SiN.sub.x (where 0<x.ltoreq.0.85) added with hydrogen or fluorine. When D (D=D.sub.0.times.10.sup.22 atoms/cm.sup.3) represents a density of hydrogen or fluorine, d (nm) represents a thickness of the current steering layer (33), and V.sub.0 (V) represents a maximum value applicable to between the first electrode (32) and The Schottky current depends on a work function of a material of the electrode. the second electrode (31), D, x, d, and V.sub. Hayakawa further discloses a current steering element is considered to have electrical conduction mechanism by which a current (known as thermionic emission current or Schottky current) flows from an electrode (comprising TaN, W, or the like) to a current steering layer (comprising SiN.sub.x). When potential barriers are formed against electrons emitted from the metal, the potential barriers are influenced by the emitted electrons (with negative charges) and coulomb electrostatic attraction (also known as image force).
Prior to the effective date of the invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Sills, Takashima and Hayakawa in the art of memory cell structures and a method of forming the same. Takashima improves Sills’ systems, methods and/or apparatus by forming a memory structure with known materials for the metal layer, the variable resistance layer and the semiconductor layer to achieve memory cells which includes a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The reset operation is an operation of causing the memory cell to transit from a low resistance state to a high resistance state by applying a reset voltage between the first interconnection and the second interconnection. Hayakawa improves Sills’ systems, methods and/or apparatus by using the Schottky diode to prevent sneak current from flowing into the variable resistance element in each of memory elements except a selected target memory element to which data is to be written.
Regarding claim 5 Sills and Takashima teach claim 1 in addition Sills and Takashima do not teach but Hayakawa teaches wherein metallic oxygen vacancy conductive filaments locally existing in the resistance variable structure is capable of being directly connected to the semiconductor structure to form a Schottky contact, and the device behaves as a self-rectifying resistive random access memory. Regarding the disclosed memory, the Schottky diode prevents sneak current from flowing into the variable resistance element in each of memory elements except a selected target memory element to which data is to be written. As a result, the crosspoint memory can prevent write didturb. Here, in the memory disclosed in Patent Literature 1, data is written to a target variable resistance element by pulsing with one polarity to the target variable resistance element. Therefore, the Schottky diode connected in series with the target variable resistance element prevents disturbance on the data writing [Hayakawa para 0009]
Regarding claim 6 Sills and Takashima teach claim 1 in addition Sills and Takashima do not teach but Hayakawa teaches, wherein when semiconductor material of the semiconductor structure is a semiconductor capable of pinning a Fermi level of a metal directly connected to the semiconductor material to vicinity of a valence band of the semiconductor material without being affected by a work function of the metal directly connected to the semiconductor material, a size of a Schottky barrier at a surface of the semiconductor material mainly depends on properties of the semiconductor material . A current steering element is considered to have electrical conduction mechanism by which a current (known as thermionic emission current or Schottky current) flows from an electrode (comprising TaN, W, or the like) to a current steering layer (comprising SiN.sub.x). The Schottky current depends on a work function of a material of the electrode. When potential barriers are formed against electrons emitted from the metal, the potential barriers are influenced by the emitted electrons (with negative charges) and coulomb electrostatic attraction (also known as image force). [Hayakawa para 0145]
Regarding claim 7 Sills and Takashima teach claim 1 in addition Sills and Takashima do not teach but Hayakawa teaches, wherein the method comprises the following steps: S11, forming strip-shaped n-type semiconductors arranged at intervals as bit lines on a p-type semiconductor substrate , SiN.sub.x gradually becomes semiconductor. Therefore, appropriately control of the nitrogen composition ratio x enables the current steering element 2 including the current steering layer 33 to serve as a MSM diode. It is also possible that SiN.sub.x is doped with a p-type or n-type dopant to adjust a resistivity [Hayakawa para 0208] Then, the readout circuit 5 reads data from the selected memory element (selected memory element 3a) and provides the data to the controller. Here, the peripheral circuits including the bit line decoder 4, the readout circuit 5, the word line decoders 6 and 7 and the like shown in FIG. 33A may be configured by metal-oxide semiconductor field-effect transistors (MOSFET), for example. It should also be noted that the memory 21 is generally manufactured by semiconductor manufacturing process. [Hayakawa para 0208] by ion implantation or spin coating doping, the method of forming the lower electrode is not limited to sputtering. The method may be so-called Chemical Vapor Deposition (CVD) method, a spin coat method, or the like. growing an isolation layer, [Hayakawa para 0092] and etching the isolation layer to form grooves arranged at intervals, the existing manufacturing equipment can be easily used in processing for SiN.sub.x, such as layer forming and etching for SiN.sub.x. In addition, the existing conditions for layer forming or etching can be applied for processing SiN.sub.x. [Hayakawa para 0105] wherein a range of the grooves is within the bit lines as shown in FIG. 33A, one end of each of the four bit lines BL0 to BL3 is connected to the bit line decoder 4. Furthermore, the other end of each of the bit lines BL0 to BL3 is connected to the readout circuit 5. [Hayakawa para 0207 and see Fig. 33A and 33B]; S12, growing a resistance variable structure on a structure obtained in the step S1 each of the memory elements 3 includes a series circuit in which a variable resistance element 1 and a current steering element 2 are connected in series to each other. The series circuit has one end connected to a bit line BLn (BL0 to BL3) at a corresponding one of the crosspoints 11, [Hayakawa para 0206]; S13, growing a metal structure on the resistance variable structure obtained in the step S12, , a size of the electrode included in the current steering element 2 is varied depending on the metal mask having the circular hole with a diameter of 100 .mu.m. [Hayakawa para 0120] and etching the metal structure to form word lines arranged at intervals one end of each of the four word lines WL0 to WL3 is connected to the word line decoder 6, and the other end of each of the four word lines WL0 to WL3 is connected to the word line decoder 7. [Hayakawa para 0207]; and S14, growing metal at a same end of each of the bit line on the metal structure obtained in the step S13 to form the contact electrodes of the bit lines. a voltage of Vw/2 is applied to both ends of each of non-selected memory elements (memory elements 3 provided at crosspoints 11 between the bit lines BL0, BL2, and BL3 and the word lines WL0, WL2, and WL3). [Hayakawa para 0224]
Regarding claim 8 Sills and Takashima teach claim 1 in addition Sills and Takashima do not teach but Hayakawa teaches, wherein the method comprises the following steps: S21, growing an n-type semiconductor on an insulating layer, SiN.sub.x gradually becomes semiconductor. Therefore, appropriately control of the nitrogen composition ratio x enables the current steering element 2 including the current steering layer 33 to serve as a MSM diode. It is also possible that SiN.sub.x is doped with a p-type or n-type dopant to adjust a resistivity [Hayakawa para 0208] Then, the readout circuit 5 reads data from the selected memory element (selected memory element 3a) and provides the data to the controller. Here, the peripheral circuits including the bit line decoder 4, the readout circuit 5, the word line decoders 6 and 7 and the like shown in FIG. 33A may be configured by metal-oxide semiconductor field-effect transistors (MOSFET), for example. It should also be noted that the memory 21 is generally manufactured by semiconductor manufacturing process. [Hayakawa para 0208] the method of forming the lower electrode is not limited to sputtering. The method may be so-called Chemical Vapor Deposition (CVD) method, a spin coat method, or the like. growing an isolation layer, [Hayakawa para 0092] and etching the n-type semiconductor to form strip regions arranged at intervals as bit lines the existing manufacturing equipment can be easily used in processing for SiN.sub.x, such as layer forming and etching for SiN.sub.x. In addition, the existing conditions for layer forming or etching can be applied for processing SiN.sub.x. [Hayakawa para 0105]; S22, growing a resistance variable structure on the bit lines obtained in the step S21 each of the memory elements 3 includes a series circuit in which a variable resistance element 1 and a current steering element 2 are connected in series to each other. The series circuit has one end connected to a bit line BLn (BL0 to BL3) at a corresponding one of the crosspoints 11, [Hayakawa para 0206]; S23, growing a metal structure on the resistance variable structure obtained in the step S22, a size of the electrode included in the current steering element 2 is varied depending on the metal mask having the circular hole with a diameter of 100 .mu.m. [Hayalawa para 0120] and etching the metal structure to form word lines arranged at intervals one end of each of the four word lines WL0 to WL3 is connected to the word line decoder 6, and the other end of each of the four word lines WL0 to WL3 is connected to the word line decoder 7. [Hayakawa para 0207]; and S24, growing metal at a same end of each of the bit lines on the metal structure obtained the step S3 to form the contact electrodes of the bit lines. a voltage of Vw/2 is applied to both ends of each of non-selected memory elements (memory elements 3 provided at crosspoints 11 between the bit lines BL0, BL2, and BL3 and the word lines WL0, WL2, and WL3). [Hayakawa para 0224]
Regarding claim 9 Sills and Takashima teach claim 1 in addition Sills and Takashima do not teach but Hayakawa teaches, which adopts Ge as the semiconductor structure, comprising the following steps: S31, growing a stress buffer layer of Ge on a semiconductor silicon substrate, and then cyclically growing SiGe and heavily-doped Ge in turn, wherein a top layer is made of SiGe, bit lines are made of the heavily-doped Ge, and a number of cycles is greater than or equal to 2 SiN.sub.x gradually becomes semiconductor. Therefore, appropriately control of the nitrogen composition ratio x enables the current steering element 2 including the current steering layer 33 to serve as a MSM diode. It is also possible that SiN.sub.x is doped with a p-type or n-type dopant to adjust a resistivity [Hayakawa para 0208]; S32, selectively etching SiGe on a structure obtained in S31 and filling in an isolation layer The method may be so-called Chemical Vapor Deposition (CVD) method, a spin coat method, or the like. [Hayakawa para 0092]; S33, selectively etching the heavily-doped Ge and filling lightly-doped Ge on a structure obtained in S32; S34, growing a resistance variable structure and a protective layer on a structure obtained in S33; S35, selectively etching the protective layer in an device area on the resistance variable structure obtained in S34, the existing manufacturing equipment can be easily used in processing for SiN.sub.x, such as layer forming and etching for SiN.sub.x. In addition, the existing conditions for layer forming or etching can be applied for processing SiN.sub.x. [Hayakawa para 0105] growing a metal structure to form a word line, one end of each of the four word lines WL0 to WL3 is connected to the word line decoder 6, and the other end of each of the four word lines WL0 to WL3 is connected to the word line decoder 7. [Hayakawa para 0207];and growing metal at a same end of each of the bit lines to form the contact electrodes of the bit lines. a voltage of Vw/2 is applied to both ends of each of non-selected memory elements (memory elements 3 provided at crosspoints 11 between the bit lines BL0, BL2, and BL3 and the word lines WL0, WL2, and WL3). [Hayakawa para 0224]
Regarding claim 10 Sills, Takashima and Hayakawa teaches claim 7 in addition Takashima teaches wherein a bit line region directly connected to the contact electrodes of the bit lines column control circuit 2 is provided at an adjacent position in the direction of bit lines BL of the memory cell array 1. [Takashima para 0019] The column control circuit 2 is part of a control circuit, and controls the bit lines BL in the memory cell array is made of a heavily-doped semiconductor, such that tunneling current dominates to ensure ohmic contact, and wherein the contact electrodes are made of a common metal. since the electrode layer (n-type Si) 11 is depleted, the voltage is distributed to the electrode layer 11. Hence, |reset voltage Vw|>|set voltage Ve| can be satisfied by, for example, making the electrode layer 11 sufficiently thick or reducing the dopant concentration in the electrode layer 11 (n-type Si). [Takashima para 0050]
Conclusion
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/ROBERT J MICHAUD/Examiner, Art Unit 2622