Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/29/2023 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97.
Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 3, 6, and 10 – 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsuji (US 20150002232 A1).
Regarding Independent Claim 1, Tsuji teaches,
A switching power supply (See Fig. 21) comprising:
a switching power supply circuit (Fig. 21, 212) that has an upper arm (Fig. 21, CONV1) and a lower arm (Fig. 21, CONV2) that are coupled in series (Fig. 21, CONV1 is coupled to CONV2);
a drive circuit (Fig. 21, MPU) that alternately turns on the upper arm (Fig. 21, CONV1) and the lower arm (Fig. 21, CONV2) across a dead time [See paragraph [0096], “MPU as a control unit if the power supply device 112 carries out digital control, and the converter switching circuit (converter switching control function) 11 constituted by a digital ON/OFF control circuit, a forced stop circuit (kill switch) 16 that forces the function of the converter switching circuit 11 to stop when a malfunction occurs, a watchdog timer circuit 15 that outputs an alarm when the computation microprocessor MPU malfunctions, and an interface unit 14 to control the device.”] in which the upper arm (Fig. 21, CONV1) and the lower arm (Fig. 21, CONV2) are turned off such that an output voltage of the switching power supply circuit (Fig. 21, 212) follows a voltage of an input signal that is an envelope signal or a subcarrier signal (Fig. 21, 9); and
an adjustment circuit (Fig. 21, 20) that adjusts the dead time according to the voltage of the input signal.
Regarding claim 2,
The switching power supply according to claim 1, wherein the adjustment circuit (Fig. 21, 20) shortens the dead time when the voltage of the input signal is higher than an average voltage of the input signal as compared with when the voltage of the input signal is lower than the average voltage of the input signal [See paragraphs [0081] and [0082], “A delay adjustment circuit 22 receives a signal that corresponds to the delay time detected by the delay time detection circuit 12 as an input and delays the output signal of the distortion correction circuit 21 to output the result to the high frequency power amplification circuit 100.” And “the RF input signal is delayed by a delay time of the power supply device 106 for a high frequency power amplification circuit and is outputted to the high frequency power amplification circuit 100. Thus, a power supply voltage that follows a signal to be amplified by the high frequency power amplification circuit 100 is applied.”].
Regarding claim 3,
The switching power supply according to claim 2, wherein the adjustment circuit (Fig. 21, 20) generates an inversion signal that is a signal obtained by vertically inverting the input signal, generates a quantization signal that is a signal obtained by quantizing the inversion signal, and shortens the dead time as the quantization signal becomes larger [See paragraphs [0081] and [0082], “A delay adjustment circuit 22 receives a signal that corresponds to the delay time detected by the delay time detection circuit 12 as an input and delays the output signal of the distortion correction circuit 21 to output the result to the high frequency power amplification circuit 100.” And “the RF input signal is delayed by a delay time of the power supply device 106 for a high frequency power amplification circuit and is outputted to the high frequency power amplification circuit 100. Thus, a power supply voltage that follows a signal to be amplified by the high frequency power amplification circuit 100 is applied.”].
Regarding claim 6,
The switching power supply according to claim 2, wherein, when the voltage of the input signal is higher than the average voltage of the input signal, the adjustment circuit (Fig. 21, 20) shortens the dead time as the voltage of the input signal is higher, and when the voltage of the input signal is lower than the average voltage of the input signal, the adjustment circuit lengthens the dead time as the voltage of the input signal is lower [See paragraphs [0081] and [0082], “A delay adjustment circuit 22 receives a signal that corresponds to the delay time detected by the delay time detection circuit 12 as an input and delays the output signal of the distortion correction circuit 21 to output the result to the high frequency power amplification circuit 100.” And “the RF input signal is delayed by a delay time of the power supply device 106 for a high frequency power amplification circuit and is outputted to the high frequency power amplification circuit 100. Thus, a power supply voltage that follows a signal to be amplified by the high frequency power amplification circuit 100 is applied.”].
Regarding independent claim 10,
An amplification device (See Fig. 21) comprising:
an extractor (Fig. 21, 9) that extracts an input signal (Fig. 21, input signal) that is an envelope signal or a subcarrier signal from a modulated wave (Fig. 21, 9 extracts envelope signals);
an amplifier (Fig. 21, 100) that amplifies the modulated wave;
a switching power supply circuit (Fig. 21, 112) that has an upper arm (Fig. 21, CONV1) and a lower arm (Fig. 21, CONV2) that are coupled in series and generates an output voltage that is a power supply voltage of the amplifier (Fig. 21, 100);
a drive circuit (Fig. 21, MPU) that alternately turns on the upper arm (Fig. 21, CONV1) and the lower arm (Fig. 21, CONV2) across a dead time [See paragraph [0096], “MPU as a control unit if the power supply device 112 carries out digital control, and the converter switching circuit (converter switching control function) 11 constituted by a digital ON/OFF control circuit, a forced stop circuit (kill switch) 16 that forces the function of the converter switching circuit 11 to stop when a malfunction occurs, a watchdog timer circuit 15 that outputs an alarm when the computation microprocessor MPU malfunctions, and an interface unit 14 to control the device.”] in which the upper arm (Fig. 21, CONV1) and the lower arm (Fig. 21, CONV2) are turned off such that the output voltage follows a voltage of the input signal; and
an adjustment circuit (Fig. 21, 20) that adjusts the dead time according to the voltage of the input signal.
Regarding claim 11,
The amplification device according to claim 10, further comprising:
a processing circuit (Fig. 21, the MPU functions as the processing circuit) that delays or equalizes the modulated wave; and
a carrier amplifier (Fig. 21, 11) that extracts a carrier signal from the modulated wave subjected to delay processing or equalization processing by the processing circuit, wherein the drive circuit (Fig. 21, MPU) includes a comparator (Fig. 21, 10) that compares the input signal with the carrier signal and outputs a first pulse signal that is a pulse width modulation signal.
Regarding independent claim 12,
A communication device (Fig. 21, 212) comprising:
an extractor (Fig. 21, 9) that extracts an input signal (Fig. 21, input signal) that is an envelope signal or a subcarrier signal from a modulated wave (Fig. 21, 9 extracts envelope signals);
an amplifier (Fig. 21, 100) that amplifies the modulated wave;
an antenna (Fig. 21, although not shown, the output of 100 is meant to be outputted to a load or an antenna. It does not depart from the scope and spirit of the present invention to include an antenna) fed by the amplifier;
a switching power supply circuit (Fig. 21, 112) that has an upper arm (Fig. 21, CONV1) and a lower arm (Fig. 21, CONV2) that are coupled in series and generates an output voltage that is a power supply voltage of the amplifier;
a drive circuit (Fig. 21, MPU) that alternately turns on the upper arm (Fig. 21, CONV1) and the lower arm (Fig. 21, CONV2) across a dead time [See paragraph [0096], “MPU as a control unit if the power supply device 112 carries out digital control, and the converter switching circuit (converter switching control function) 11 constituted by a digital ON/OFF control circuit, a forced stop circuit (kill switch) 16 that forces the function of the converter switching circuit 11 to stop when a malfunction occurs, a watchdog timer circuit 15 that outputs an alarm when the computation microprocessor MPU malfunctions, and an interface unit 14 to control the device.”] in which the upper arm (Fig. 21, CONV1) and the lower arm (Fig. 21, CONV2) are turned off such that the output voltage follows a voltage of the input signal that is the envelope signal or the subcarrier signal; and
an adjustment circuit (Fig. 21, 20) that adjusts the dead time according to the voltage of the input signal.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 5, 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Tsuji in view of Sumitomo et al. (US 20230198401 A1), hereinafter Sumitomo.
Regarding claim 4, Tsuji discloses;
The switching power supply according to claim 3, wherein the drive circuit (Fig. 21, MPU) includes:
a first delay circuit (Fig. 21, 12) that outputs a delay input signal that is a signal obtained by delaying the input signal;
a comparator (Fig. 21, 10) that compares the delay input signal with a sampling signal and outputs a first pulse signal that is a pulse width modulation signal;
a second delay circuit that outputs a second pulse signal obtained by delaying the first pulse signal by a first delay amount that corresponds to a first control voltage, and switches the upper arm;
a third delay circuit (Fig. 21, 10) that outputs a third pulse signal obtained by delaying the second pulse signal by a second delay amount that corresponds to a second control voltage; and
a negative OR circuit that outputs a fourth pulse signal that is a negative OR of the first pulse signal and the third pulse signal, and switches the lower arm, and the adjustment circuit includes:
a fourth delay circuit (Fig. 21, 22) that outputs a delay sampling signal (Fig. 21, signal from 22) that is a signal obtained by delaying the sampling signal;
a first sample hold circuit that samples the inversion signal according to the sampling signal and outputs a first quantization signal;
a second sample hold circuit that samples the inversion signal according to the delay sampling signal and outputs a second quantization signal;
a fifth delay circuit that delays the first quantization signal and outputs the first control voltage; and
a sixth delay circuit that delays the second quantization signal and outputs the second control voltage.
Tsuji is silent regarding;
a second delay circuit that outputs a second pulse signal obtained by delaying the first pulse signal by a first delay amount that corresponds to a first control voltage, and switches the upper arm;
a negative OR circuit that outputs a fourth pulse signal that is a negative OR of the first pulse signal and the third pulse signal, and switches the lower arm, and the adjustment circuit includes:
a first sample hold circuit that samples the inversion signal according to the sampling signal and outputs a first quantization signal;
a second sample hold circuit that samples the inversion signal according to the delay sampling signal and outputs a second quantization signal;
a fifth delay circuit that delays the first quantization signal and outputs the first control voltage; and
a sixth delay circuit that delays the second quantization signal and outputs the second control voltage.
Sumitomo discloses:
a second delay circuit (Fig. 4, 31) that outputs a second pulse signal obtained by delaying the first pulse signal by a first delay amount that corresponds to a first control voltage, and switches the upper arm;
a negative OR circuit (Fig. 9, 33) that outputs a fourth pulse signal that is a negative OR of the first pulse signal and the third pulse signal, and switches the lower arm, and the adjustment circuit includes:
a first sample hold circuit (Fig. 9, 35) that samples the inversion signal according to the sampling signal and outputs a first quantization signal;
a second sample hold circuit (Fig. 9, 101) that samples the inversion signal according to the delay sampling signal and outputs a second quantization signal;
a fifth delay circuit (Fig. 9, 31) that delays the first quantization signal and outputs the first control voltage; and
a sixth delay circuit (Fig. 9, 104) that delays the second quantization signal and outputs the second control voltage.
Tsuji and Sumitomo are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a plurality of delay circuits with sample and hold circuits in Tsuji‘s design in order to delay each output and sample each signal in accordance with Sumitomo‘s design.
Regarding claim 5,
The switching power supply according to claim 4, further comprising a skew controller (Fig. 21, 21) that aligns operation timings of the first delay circuit, the fourth delay circuit, the fifth delay circuit, and the sixth delay circuit.
Regarding claim 8, Tsuji discloses:
a first power supply unit that includes the switching power supply circuit, the drive circuit, and the adjustment circuit;
a second power supply unit that includes the switching power supply circuit, the drive circuit, and the adjustment circuit;
a seventh delay circuit that outputs a second delay sampling signal obtained by delaying a sampling signal;
an eighth delay circuit that outputs a second delay input signal obtained by delaying the input signal;
a signal amplifier (Fig. 21, 100) that amplifies the input signal;
a first combiner that combines the output voltage of the first power supply unit to which the input signal and the sampling signal are input with an output voltage of the signal amplifier; and
a second combiner that combines the output voltage of the second power supply unit to which the second delay input signal and the second delay sampling signal are input with an output voltage of the first combiner.
Tsuji is silent regarding:
a first power supply unit that includes the switching power supply circuit, the drive circuit, and the adjustment circuit;
a second power supply unit that includes the switching power supply circuit, the drive circuit, and the adjustment circuit;
a seventh delay circuit that outputs a second delay sampling signal obtained by delaying a sampling signal;
an eighth delay circuit that outputs a second delay input signal obtained by delaying the input signal;
a first combiner that combines the output voltage of the first power supply unit to which the input signal and the sampling signal are input with an output voltage of the signal amplifier; and
a second combiner that combines the output voltage of the second power supply unit to which the second delay input signal and the second delay sampling signal are input with an output voltage of the first combiner.
Sumitomo discloses:
a first power supply unit (Fig. 9, 31, 32, 35, 36, and 37) that includes the switching power supply circuit (Fig. 9, 36), the drive circuit (Fig. 9, 32), and the adjustment circuit (Fig. 9, 35);
a second power supply unit (Fig. 9, 33, 34, 101, 102, 103, and 104) that includes the switching power supply circuit (Fig. 9, 102), the drive circuit (Fig. 9, 34), and the adjustment circuit (Fig. 9, 101);
a seventh delay circuit (Fig. 9, 31) that outputs a second delay sampling signal obtained by delaying a sampling signal;
an eighth delay circuit (Fig. 9, 104) that outputs a second delay input signal obtained by delaying the input signal;
a first combiner (Fig. 9, 1) that combines the output voltage of the first power supply unit to which the input signal and the sampling signal are input with an output voltage of the signal amplifier; and
a second combiner (Fig. 9, 2) that combines the output voltage of the second power supply unit to which the second delay input signal and the second delay sampling signal are input with an output voltage of the first combiner.
Tsuji and Sumitomo are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a second set of the switching power supply and two combiners in Tsuji‘s design in order to have two units with a combiner in accordance with Sumitomo‘s design.
Regarding claim 9,
The switching power supply according to claim 4, The switching power supply according to wherein the input signal is an envelope signal or a subcarrier signal (The input signal is an envelope signal).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Tsuji in view of Jurkov et al. (US 20190006995 A1), hereinafter Jurkov.
Regarding claim 7, Tsuji discloses:
a plurality of power supply units (Fig. 21, plurality of 212) each of which includes the switching power supply circuit (Fig. 21, 112), the drive circuit (Fig. 21, MPU), and the adjustment circuit (Fig. 21, 20); and
a plurality of phase shifters that generates a plurality of sampling signals that has different phases, wherein the drive circuit includes a comparator (Fig. 21, 10) that compares the input signal with a corresponding sampling signal among the plurality of sampling signals and outputs a first pulse signal that is a pulse width modulation signal.
Tsuji is silent regarding:
a plurality of phase shifters that generates a plurality of sampling signals that has different phases, wherein the drive circuit includes a comparator that compares the input signal with a corresponding sampling signal among the plurality of sampling signals and outputs a first pulse signal that is a pulse width modulation signal.
Jurkov discloses:
a plurality of phase shifters (Fig. 25A, 2504) that generates a plurality of sampling signals (Fig. 25A, signals from 2504) that has different phases, wherein the drive circuit includes a comparator that compares the input signal with a corresponding sampling signal among the plurality of sampling signals and outputs a first pulse signal that is a pulse width modulation signal.
Tsuji and Jurkov are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include phase shifters in Tsuji‘s design in order to shift the signal to the corresponding phase in accordance with Jurkov‘s design.
Conclusion
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/JOSE E PINERO/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843